Merge branch 'drm-next-4.8' of git://people.freedesktop.org/~agd5f/linux into drm-next

This is the main 4.8 pull for radeon and amdgpu.  Sorry for the delay,
I meant to send this out last week, but I was moving house.  Lots of
changes here:
- ATPX improvements for better dGPU power control on PX systems
- New power features for CZ/BR/ST
- Pipelined BO moves and evictions in TTM
- GPU scheduler improvements
- GPU reset improvements
- Overclocking on dGPUs with amdgpu
- Lots of code cleanup
- Bug fixes

* 'drm-next-4.8' of git://people.freedesktop.org/~agd5f/linux: (191 commits)
  drm/amd/powerplay: don't add invalid voltage.
  drm/amdgpu: add read/write function for GC CAC programming
  drm/amd/powerplay: add definitions related to di/dt feature for fiji and polaris.
  drm/amd/powerplay: add shared definitions for di/dt feature.
  drm/amdgpu: remove gfx8 registers that vary between asics
  drm/amd/powerplay: add mvdd dpm support.
  drm/amdgpu: get number of shade engine by cgs interface.
  drm/amdgpu: remove more of the ring backup code
  drm/amd/powerplay:  Unify family defines
  drm/amdgpu: clean up ring_backup code, no need more
  drm/amdgpu: ib test first after gpu reset
  drm/amdgpu: recovery hw jobs when gpu reset V3
  drm/amdgpu: abstract amdgpu_vm_is_gpu_reset
  drm/amdgpu: add a bool to specify if needing vm flush V2
  drm/amdgpu: add amd_sched_job_recovery
  drm/amdgpu: force completion for gpu reset
  drm/amdgpu: block ttm first before parking scheduler
  drm/amd: add amd_sched_hw_job_reset
  drm/amd: add parent for sched fence
  drm/amdgpu: remove evict vram
  ...

1 files changed, 44 insertions, 0 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 9f95da4f0536..a074edd95c70 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -70,3 +70,47 @@ void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg)
 		}
 	}
 }
+
+/**
+ * amdgpu_gfx_parse_disable_cu - Parse the disable_cu module parameter
+ *
+ * @mask: array in which the per-shader array disable masks will be stored
+ * @max_se: number of SEs
+ * @max_sh: number of SHs
+ *
+ * The bitmask of CUs to be disabled in the shader array determined by se and
+ * sh is stored in mask[se * max_sh + sh].
+ */
+void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_sh)
+{
+	unsigned se, sh, cu;
+	const char *p;
+
+	memset(mask, 0, sizeof(*mask) * max_se * max_sh);
+
+	if (!amdgpu_disable_cu || !*amdgpu_disable_cu)
+		return;
+
+	p = amdgpu_disable_cu;
+	for (;;) {
+		char *next;
+		int ret = sscanf(p, "%u.%u.%u", &se, &sh, &cu);
+		if (ret < 3) {
+			DRM_ERROR("amdgpu: could not parse disable_cu\n");
+			return;
+		}
+
+		if (se < max_se && sh < max_sh && cu < 16) {
+			DRM_INFO("amdgpu: disabling CU %u.%u.%u\n", se, sh, cu);
+			mask[se * max_sh + sh] |= 1u << cu;
+		} else {
+			DRM_ERROR("amdgpu: disable_cu %u.%u.%u is out of range\n",
+				  se, sh, cu);
+		}
+
+		next = strchr(p, ',');
+		if (!next)
+			break;
+		p = next + 1;
+	}
+}