Merge tag 'drm-next-5.3-2019-06-25' of git://people.freedesktop.org/~agd5f/linux into drm-next

drm-next-5.3-2019-06-25:

Merge drm-next

amdgpu:
- SR-IOV L1 policy fixes
- Removed no longer needed vram_page_split module parameter
- Add module parameter to override default ABM level
- Gamma fixes
- No need to check return values for debugfs
- Improve HMM error handling
- Avoid possible OOM situations when lots of thread are submitting with
  memory contention
- Improve hw i2c access abritration
- DSC (Display Stream Compression) support in DC
- Initial navi10 support
  * DC support
  * GFX/Compute support
  * SDMA support
  * Power Management support
  * VCN support
- Static checker fixes
- Misc cleanups
- fix long udelay on arm

amdkfd:
- Implement priority controls for gfx9
- Enable VEGAM
- Rework mqd allocation and init
- Circular locking fix
- Fix SDMA queue allocation race condition
- No need to check return values for debugfs
- Add proc style process information
- Initial navi10 support

radeon:
- No need to check return values for debugfs

UAPI changes:
- GDDR6 added to vram type query
- New Navi10 details added gpu info query
- Navi family added to asic family query

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190625195520.3817-1-alexander.deucher@amd.com

1 files changed, 70 insertions, 1 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index a1ee19251aae..99f14fcc1460 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -25,7 +25,7 @@
 #define __AMDGPU_VCN_H__
 
 #define AMDGPU_VCN_STACK_SIZE		(128*1024)
-#define AMDGPU_VCN_CONTEXT_SIZE	(512*1024)
+#define AMDGPU_VCN_CONTEXT_SIZE 	(512*1024)
 
 #define AMDGPU_VCN_FIRMWARE_OFFSET	256
 #define AMDGPU_VCN_MAX_ENC_RINGS	3
@@ -45,6 +45,11 @@
 #define VCN_ENC_CMD_REG_WRITE		0x0000000b
 #define VCN_ENC_CMD_REG_WAIT		0x0000000c
 
+#define VCN_VID_SOC_ADDRESS_2_0 	0x1fa00
+#define VCN_AON_SOC_ADDRESS_2_0 	0x1f800
+#define VCN_VID_IP_ADDRESS_2_0		0x0
+#define VCN_AON_IP_ADDRESS_2_0		0x30000
+
 #define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel) 				\
 	({	WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); 			\
 		WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, 				\
@@ -66,8 +71,55 @@
 			(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); 		\
 	} while (0)
 
+#define SOC15_DPG_MODE_OFFSET_2_0(ip, inst, reg) 						\
+	({											\
+		uint32_t internal_reg_offset, addr;						\
+		bool video_range, aon_range;							\
+												\
+		addr = (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg);		\
+		addr <<= 2; 									\
+		video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS_2_0)) && 		\
+				((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 + 0x2600)))));	\
+		aon_range   = ((((0xFFFFF & addr) >= (VCN_AON_SOC_ADDRESS_2_0)) && 		\
+				((0xFFFFF & addr) < ((VCN_AON_SOC_ADDRESS_2_0 + 0x600)))));	\
+		if (video_range) 								\
+			internal_reg_offset = ((0xFFFFF & addr) - (VCN_VID_SOC_ADDRESS_2_0) + 	\
+				(VCN_VID_IP_ADDRESS_2_0));					\
+		else if (aon_range)								\
+			internal_reg_offset = ((0xFFFFF & addr) - (VCN_AON_SOC_ADDRESS_2_0) + 	\
+				(VCN_AON_IP_ADDRESS_2_0));					\
+		else										\
+			internal_reg_offset = (0xFFFFF & addr);					\
+												\
+		internal_reg_offset >>= 2;							\
+	})
+
+#define RREG32_SOC15_DPG_MODE_2_0(offset, mask_en) 						\
+	({ 											\
+		WREG32_SOC15(VCN, 0, mmUVD_DPG_LMA_CTL, 					\
+			(0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | 				\
+			mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | 				\
+			offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); 			\
+		RREG32_SOC15(VCN, 0, mmUVD_DPG_LMA_DATA); 					\
+	})
+
+#define WREG32_SOC15_DPG_MODE_2_0(offset, value, mask_en, indirect)				\
+	do { 											\
+		if (!indirect) { 								\
+			WREG32_SOC15(VCN, 0, mmUVD_DPG_LMA_DATA, value); 			\
+			WREG32_SOC15(VCN, 0, mmUVD_DPG_LMA_CTL, 				\
+				(0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | 			\
+				 mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | 			\
+				 offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); 		\
+		} else { 									\
+			*adev->vcn.dpg_sram_curr_addr++ = offset; 				\
+			*adev->vcn.dpg_sram_curr_addr++ = value; 				\
+		} 										\
+	} while (0)
+
 enum engine_status_constants {
 	UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0,
+	UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0 = 0xAAAA0,
 	UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002,
 	UVD_STATUS__UVD_BUSY = 0x00000004,
 	GB_ADDR_CONFIG_DEFAULT = 0x26010011,
@@ -75,6 +127,7 @@ enum engine_status_constants {
 	UVD_STATUS__BUSY = 0x5,
 	UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF = 0x1,
 	UVD_STATUS__RBC_BUSY = 0x1,
+	UVD_PGFSM_STATUS_UVDJ_PWR_ON = 0,
 };
 
 enum internal_dpg_state {
@@ -87,6 +140,15 @@ struct dpg_pause_state {
 	enum internal_dpg_state jpeg;
 };
 
+struct amdgpu_vcn_reg{
+	unsigned	data0;
+	unsigned	data1;
+	unsigned	cmd;
+	unsigned	nop;
+	unsigned	scratch9;
+	unsigned	jpeg_pitch;
+};
+
 struct amdgpu_vcn {
 	struct amdgpu_bo	*vcpu_bo;
 	void			*cpu_addr;
@@ -102,8 +164,15 @@ struct amdgpu_vcn {
 	unsigned		num_enc_rings;
 	enum amd_powergating_state cur_state;
 	struct dpg_pause_state pause_state;
+	struct amdgpu_vcn_reg	internal, external;
 	int (*pause_dpg_mode)(struct amdgpu_device *adev,
 		struct dpg_pause_state *new_state);
+
+	bool			indirect_sram;
+	struct amdgpu_bo	*dpg_sram_bo;
+	void			*dpg_sram_cpu_addr;
+	uint64_t		dpg_sram_gpu_addr;
+	uint32_t		*dpg_sram_curr_addr;
 };
 
 int amdgpu_vcn_sw_init(struct amdgpu_device *adev);