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author | Alex Deucher <alexander.deucher@amd.com> | 2025-03-27 17:46:59 -0400 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2025-04-08 16:48:13 -0400 |
commit | 9e7b08d239c2f21e8f417854f81e5ff40edbebff (patch) | |
tree | f6e5f12330d8243c3a00657f41a3b09181359a0e /drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | |
parent | da7dc714a8f8e1c9fc33c57cd63583779a3bef71 (diff) |
drm/amdgpu/mes12: optimize MES pipe FW version fetching
Don't fetch it again if we already have it. It seems the
registers don't reliably have the value at resume in some
cases.
Fixes: 785f0f9fe742 ("drm/amdgpu: Add mes v12_0 ip block support (v4)")
Reviewed-by: Shaoyun.liu <Shaoyun.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/dce_v6_0.c')
0 files changed, 0 insertions, 0 deletions