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| author | Alvin Lee <Alvin.Lee2@amd.com> | 2023-04-10 14:37:27 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-04-24 18:36:45 -0400 |
| commit | ee7be8f3de1ccc9665281fe996f9b6d45191ec1a (patch) | |
| tree | 1c5a9595e03500e72e2166cbf17181aa19216a7a /drivers/gpu/drm/amd/display/modules/power/power_helpers.c | |
| parent | 8f3589bb6fcea397775398cba4fbcc46829a60ed (diff) | |
drm/amd/display: Limit DCN32 8 channel or less parts to DPM1 for FPO
- Due to hardware related QoS issues, we need to limit certain
SKUs with less memory channels to DPM1 and above.
- At DPM0 + workload running, the urgent return latency can
exceed 15us (the expected maximum is 4us) which results in underflow
Cc: stable@vger.kernel.org
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Saaem Rizvi <SyedSaaem.Rizvi@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/modules/power/power_helpers.c')
0 files changed, 0 insertions, 0 deletions