diff options
| author | Imre Deak <imre.deak@intel.com> | 2017-07-11 23:42:35 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2017-07-27 09:38:53 +0200 |
| commit | b2891eb2531e5e0d251febd0a395d758111790d4 (patch) | |
| tree | 122b5d0206a9ce94ffd9a2b5935fadc5371a20bf /drivers/gpu/drm/i915/i915_drv.h | |
| parent | 76347c04d879267839337adc2aea6136b58c2ca7 (diff) | |
drm/i915/hsw+: Add has_fuses power well attribute
The pattern of a power well backing a set of fuses whose initialization
we need to wait for during power well enabling is common to all GEN9+
platforms. Adding support for this to the HSW power well enable helper
allows us to use the HSW/BDW power well code for GEN9+ as well in a
follow-up patch.
v2:
- Use an enum for power gates instead of raw numbers. (Ville)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170711204236.5618-6-imre.deak@intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 1a43adb22162..0ac66a4c361f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1397,6 +1397,7 @@ struct i915_power_well { u8 irq_pipe_mask; /* The pw is backing the VGA functionality */ bool has_vga:1; + bool has_fuses:1; } hsw; }; const struct i915_power_well_ops *ops; |