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authorLinus Torvalds <torvalds@linux-foundation.org>2015-09-24 15:37:06 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2015-09-24 15:37:06 -0700
commitcc8b8faea417bd264d23fa5d017da52b75bbdf94 (patch)
treea05a4b04e43c84792e1ab277b9ee522fb39b8424 /drivers/gpu/drm/i915/i915_irq.c
parentbfbaa60d186d81207e61e7f4337fa442860aef72 (diff)
parentfd03420b5624617a708fb9b13634b41b37c22cfa (diff)
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "Most of the GPU drivers people were at XDC last week, so I didn't get much to send, so I let it rollover until this week. Also Alex was away for 3 weeks so amdgpu/radeon got a bit more stuff than usual in one go. I've been trying to figure out some 4.2 issues with i915 still (that are fixed in 4.3, but bisecting ends up in a merge commit). Hopefully next week I or i915 people can work that out" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (46 commits) drm: Allow also control clients to check the drm version drm/vmwgfx: Fix uninitialized return in vmw_kms_helper_dirty() drm/vmwgfx: Fix uninitialized return in vmw_cotable_unbind() drm/layerscape: fix handling fsl_dcu_drm_plane_index result drm/mgag200: Fix driver_load error handling drm/mgag200: Fix error handling paths in fbdev driver drm/qxl: only report first monitor as connected if we have no state drm/radeon: add quirk for MSI R7 370 drm/amdgpu: Sprinkle drm_modeset_lock_all to appease locking checks drm/radeon: Sprinkle drm_modeset_lock_all to appease locking checks drm/amdgpu: sync ce and me with SWITCH_BUFFER(2) drm/amdgpu: integer overflow in amdgpu_mode_dumb_create() drm/amdgpu: info leak in amdgpu_gem_metadata_ioctl() drm/amdgpu: integer overflow in amdgpu_info_ioctl() drm/amdgpu: unwind properly in amdgpu_cs_parser_init() drm/amdgpu: Fix max_vblank_count value for current display engines drm/amdgpu: use kmemdup rather than duplicating its implementation drm/amdgpu: fix UVD suspend and resume for VI APU drm/amdgpu: fix the UVD suspend sequence order drm/amdgpu: make UVD handle checking more strict ...
Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c26
1 files changed, 26 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5a244ab9395b..39d73dbc1c47 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -640,6 +640,32 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
/*
+ * On HSW, the DSL reg (0x70000) appears to return 0 if we
+ * read it just before the start of vblank. So try it again
+ * so we don't accidentally end up spanning a vblank frame
+ * increment, causing the pipe_update_end() code to squak at us.
+ *
+ * The nature of this problem means we can't simply check the ISR
+ * bit and return the vblank start value; nor can we use the scanline
+ * debug register in the transcoder as it appears to have the same
+ * problem. We may need to extend this to include other platforms,
+ * but so far testing only shows the problem on HSW.
+ */
+ if (IS_HASWELL(dev) && !position) {
+ int i, temp;
+
+ for (i = 0; i < 100; i++) {
+ udelay(1);
+ temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
+ DSL_LINEMASK_GEN3;
+ if (temp != position) {
+ position = temp;
+ break;
+ }
+ }
+ }
+
+ /*
* See update_scanline_offset() for the details on the
* scanline_offset adjustment.
*/