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| author | Mark Brown <broonie@kernel.org> | 2025-05-01 14:43:44 +0900 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2025-05-01 14:43:44 +0900 |
| commit | 844af9911a5d1dc41f3478dc312a404b38cbc83b (patch) | |
| tree | d6aef04723f2265235c3d7fb846e522269bacbab /drivers/gpu/drm/meson/meson_drv.c | |
| parent | 7f91f012c1df07af6b915d1f8cece202774bb50e (diff) | |
| parent | cce34d113e2a592806abcdc02c7f8513775d8b20 (diff) | |
ASoC: stm32: sai: fix kernel rate configuration
Merge series from Olivier Moysan <olivier.moysan@foss.st.com>:
This patchset adds some checks on kernel minimum rate requirements.
This avoids potential clock rate misconfiguration, when setting the
kernel frequency on STM32MP2 SoCs.
Diffstat (limited to 'drivers/gpu/drm/meson/meson_drv.c')
| -rw-r--r-- | drivers/gpu/drm/meson/meson_drv.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c index 81d2ee37e773..49ff9f1f16d3 100644 --- a/drivers/gpu/drm/meson/meson_drv.c +++ b/drivers/gpu/drm/meson/meson_drv.c @@ -169,7 +169,7 @@ static const struct meson_drm_soc_attr meson_drm_soc_attrs[] = { /* S805X/S805Y HDMI PLL won't lock for HDMI PHY freq > 1,65GHz */ { .limits = { - .max_hdmi_phy_freq = 1650000, + .max_hdmi_phy_freq = 1650000000, }, .attrs = (const struct soc_device_attribute []) { { .soc_id = "GXL (S805*)", }, |