diff options
| author | Rajeev Nandan <quic_rajeevny@quicinc.com> | 2022-01-31 01:45:18 +0530 |
|---|---|---|
| committer | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2022-02-18 18:32:59 +0300 |
| commit | 0874cf8614c0ac0a3aa6f9420b39a5669fc2724e (patch) | |
| tree | 4cc740ac325ca878cb6283260743c11dcfc5ab40 /drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | |
| parent | 3bcf3d8341080a7f79d8566aeadbd3c911391cfe (diff) | |
drm/msm/dsi: Add dsi phy tuning configuration support
Add support for MSM DSI PHY tuning configuration. Current design is
to support drive strength and drive level/amplitude tuning for
10nm PHY version, but this can be extended to other PHY versions.
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/1643573719-32095-3-git-send-email-quic_rajeevny@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Diffstat (limited to 'drivers/gpu/drm/msm/dsi/phy/dsi_phy.h')
| -rw-r--r-- | drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 4c8257581bfc..dc91b43d5a38 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -25,6 +25,7 @@ struct msm_dsi_phy_ops { void (*save_pll_state)(struct msm_dsi_phy *phy); int (*restore_pll_state)(struct msm_dsi_phy *phy); bool (*set_continuous_clock)(struct msm_dsi_phy *phy, bool enable); + int (*parse_dt_properties)(struct msm_dsi_phy *phy); }; struct msm_dsi_phy_cfg { @@ -82,6 +83,8 @@ struct msm_dsi_dphy_timing { #define DSI_PIXEL_PLL_CLK 1 #define NUM_PROVIDED_CLKS 2 +#define DSI_LANE_MAX 5 + struct msm_dsi_phy { struct platform_device *pdev; void __iomem *base; @@ -99,6 +102,7 @@ struct msm_dsi_phy { struct msm_dsi_dphy_timing timing; const struct msm_dsi_phy_cfg *cfg; + void *tuning_cfg; enum msm_dsi_phy_usecase usecase; bool regulator_ldo_mode; |