diff options
| author | Tao Zhang <quic_taozha@quicinc.com> | 2024-02-04 13:30:35 +0800 |
|---|---|---|
| committer | Suzuki K Poulose <suzuki.poulose@arm.com> | 2024-02-12 10:29:47 +0000 |
| commit | a1705ffcce5268eb95a5e716ee32c9d181b8c228 (patch) | |
| tree | b1a4b65510732a9d7b264b6036fed03523074ad3 /drivers/hwtracing/coresight/coresight-tpdm.c | |
| parent | 4ed57f75898ce466ed60ce3c146290742985aa95 (diff) | |
coresight-tpdm: Add CMB dataset support
CMB (continuous multi-bit) is one of TPDM's dataset type. CMB subunit
can be enabled for data collection by writing 1 to the first bit of
CMB_CR register. This change is to add enable/disable function for
CMB dataset by writing CMB_CR register.
Reviewed-by: James Clark <james.clark@arm.com>
Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
Signed-off-by: Jinlong Mao <quic_jinlmao@quicinc.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/1707024641-22460-5-git-send-email-quic_taozha@quicinc.com
Diffstat (limited to 'drivers/hwtracing/coresight/coresight-tpdm.c')
| -rw-r--r-- | drivers/hwtracing/coresight/coresight-tpdm.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c index 4b1296d11360..1bb1d8e83501 100644 --- a/drivers/hwtracing/coresight/coresight-tpdm.c +++ b/drivers/hwtracing/coresight/coresight-tpdm.c @@ -263,6 +263,19 @@ static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata) writel_relaxed(val, drvdata->base + TPDM_DSB_CR); } +static void tpdm_enable_cmb(struct tpdm_drvdata *drvdata) +{ + u32 val; + + if (!tpdm_has_cmb_dataset(drvdata)) + return; + + val = readl_relaxed(drvdata->base + TPDM_CMB_CR); + /* Set the enable bit of CMB control register to 1 */ + val |= TPDM_CMB_CR_ENA; + writel_relaxed(val, drvdata->base + TPDM_CMB_CR); +} + /* * TPDM enable operations * The TPDM or Monitor serves as data collection component for various @@ -276,6 +289,7 @@ static void __tpdm_enable(struct tpdm_drvdata *drvdata) CS_UNLOCK(drvdata->base); tpdm_enable_dsb(drvdata); + tpdm_enable_cmb(drvdata); CS_LOCK(drvdata->base); } @@ -312,12 +326,26 @@ static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata) writel_relaxed(val, drvdata->base + TPDM_DSB_CR); } +static void tpdm_disable_cmb(struct tpdm_drvdata *drvdata) +{ + u32 val; + + if (!tpdm_has_cmb_dataset(drvdata)) + return; + + val = readl_relaxed(drvdata->base + TPDM_CMB_CR); + /* Set the enable bit of CMB control register to 0 */ + val &= ~TPDM_CMB_CR_ENA; + writel_relaxed(val, drvdata->base + TPDM_CMB_CR); +} + /* TPDM disable operations */ static void __tpdm_disable(struct tpdm_drvdata *drvdata) { CS_UNLOCK(drvdata->base); tpdm_disable_dsb(drvdata); + tpdm_disable_cmb(drvdata); CS_LOCK(drvdata->base); } |