diff options
| author | David S. Miller <davem@davemloft.net> | 2013-03-07 15:31:39 -0500 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2013-03-07 15:31:39 -0500 |
| commit | f3564b2bb5f86f42b8a068751551b6bd01325d9c (patch) | |
| tree | 1c448e4f6471dc096ffd86f51380e08cbd1d910c /drivers/net/ethernet/broadcom/tg3.h | |
| parent | a6f3587ca24da9c150269fe76cb2eabc6df96b90 (diff) | |
| parent | c4dab50697ff220e35f7b4464418c5893de4e699 (diff) | |
Merge branch 'tg3'
Nithin Nayak says:
====================
For the 57766 devices with no NVRAM, there is not enough space for the complete
boot code with EEE support. On these devices, the tg3 driver has to download
a service patch firmware to the scratchpad for the boot code to execute. This
patchset adds support to do the above.
A major portion of this patchset is refactoring the existing firmware download
section to allow a cleaner merge of the 57766 download. The 57766 firmware
differs from previous firmware in that it's not written to a contiguous area in
memory. It consists of multiple fragments to be written to different locations.
The patchset makes an attempt to make the new firmware format to be an
extension of the existing format.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/broadcom/tg3.h')
| -rw-r--r-- | drivers/net/ethernet/broadcom/tg3.h | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/drivers/net/ethernet/broadcom/tg3.h b/drivers/net/ethernet/broadcom/tg3.h index 8d7d4c2ab5d6..1cdc1b641c77 100644 --- a/drivers/net/ethernet/broadcom/tg3.h +++ b/drivers/net/ethernet/broadcom/tg3.h @@ -2222,6 +2222,12 @@ #define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000 #define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000 +#define TG3_SRAM_RXCPU_SCRATCH_BASE_57766 0x00030000 +#define TG3_SRAM_RXCPU_SCRATCH_SIZE_57766 0x00010000 +#define TG3_57766_FW_BASE_ADDR 0x00030000 +#define TG3_57766_FW_HANDSHAKE 0x0003fccc +#define TG3_SBROM_IN_SERVICE_LOOP 0x51 + #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5700 128 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5755 64 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5906 32 @@ -3009,17 +3015,18 @@ enum TG3_FLAGS { TG3_FLAG_JUMBO_CAPABLE, TG3_FLAG_CHIP_RESETTING, TG3_FLAG_INIT_COMPLETE, - TG3_FLAG_TSO_BUG, TG3_FLAG_MAX_RXPEND_64, - TG3_FLAG_TSO_CAPABLE, TG3_FLAG_PCI_EXPRESS, /* BCM5785 + pci_is_pcie() */ TG3_FLAG_ASF_NEW_HANDSHAKE, TG3_FLAG_HW_AUTONEG, TG3_FLAG_IS_NIC, TG3_FLAG_FLASH, + TG3_FLAG_FW_TSO, TG3_FLAG_HW_TSO_1, TG3_FLAG_HW_TSO_2, TG3_FLAG_HW_TSO_3, + TG3_FLAG_TSO_CAPABLE, + TG3_FLAG_TSO_BUG, TG3_FLAG_ICH_WORKAROUND, TG3_FLAG_1SHOT_MSI, TG3_FLAG_NO_FWARE_REPORTED, @@ -3064,6 +3071,13 @@ enum TG3_FLAGS { TG3_FLAG_NUMBER_OF_FLAGS, /* Last entry in enum TG3_FLAGS */ }; +struct tg3_firmware_hdr { + __be32 version; /* unused for fragments */ + __be32 base_addr; + __be32 len; +}; +#define TG3_FW_HDR_LEN (sizeof(struct tg3_firmware_hdr)) + struct tg3 { /* begin "general, frequently-used members" cacheline section */ |