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| author | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2024-04-02 08:17:13 -0400 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2024-04-02 08:17:13 -0400 |
| commit | 5add703f6acad1c63f8a532b6de56e50d548e904 (patch) | |
| tree | be39a82716119cd8b7cf7e2734baf8cd9a80ceb7 /drivers/pci/controller/cadence/pcie-cadence.h | |
| parent | 71cdfa8cad300caa7afcbba09776bbc8dcfa9e39 (diff) | |
| parent | 39cd87c4eb2b893354f3b850f916353f2658ae6f (diff) | |
Merge drm/drm-next into drm-intel-next
Catching up on 6.9-rc2
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/pci/controller/cadence/pcie-cadence.h')
| -rw-r--r-- | drivers/pci/controller/cadence/pcie-cadence.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index 03b96798f858..7a66a2f815dc 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -131,6 +131,12 @@ #define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 /* + * Endpoint PF Registers + */ +#define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn) (0x144 + (fn) * 0x1000) +#define CDNS_PCIE_ARI_CAP_NFN_MASK GENMASK(15, 8) + +/* * Root Port Registers (PCI configuration space for the root port function) */ #define CDNS_PCIE_RP_BASE 0x00200000 |