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authorRob Herring <robh@kernel.org>2020-10-26 13:16:52 -0500
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2020-11-18 16:01:53 +0000
commit9f9e59a4809563f24e3d1377aa804a4b7386a418 (patch)
tree6e5b5ac2e082be6a85adc75ec769c3974a3663a5 /drivers/pci/controller/dwc/pcie-designware.h
parentf8394f232b1eab649ce2df5c5f15b0e528c92091 (diff)
PCI: dwc: Support multiple ATU memory regions
The current ATU setup only supports a single memory resource which isn't sufficient if there are also prefetchable memory regions. In order to support multiple memory regions, we need to move away from fixed ATU slots and rework the assignment. As there's always an ATU entry for config space, let's assign index 0 to config space. Then we assign memory resources to index 1 and up. Finally, if we have an I/O region and slots remaining, we assign the I/O region last. If there aren't remaining slots, we keep the same config and I/O space sharing. Link: https://lore.kernel.org/r/20201026181652.418729-1-robh@kernel.org Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Vidya Sagar <vidyas@nvidia.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> Cc: Vidya Sagar <vidyas@nvidia.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-designware.h')
-rw-r--r--drivers/pci/controller/dwc/pcie-designware.h6
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 9d2f511f13fa..ed19c34dd0fe 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -80,9 +80,6 @@
#define PCIE_ATU_VIEWPORT 0x900
#define PCIE_ATU_REGION_INBOUND BIT(31)
#define PCIE_ATU_REGION_OUTBOUND 0
-#define PCIE_ATU_REGION_INDEX2 0x2
-#define PCIE_ATU_REGION_INDEX1 0x1
-#define PCIE_ATU_REGION_INDEX0 0x0
#define PCIE_ATU_CR1 0x904
#define PCIE_ATU_TYPE_MEM 0x0
#define PCIE_ATU_TYPE_IO 0x2
@@ -266,7 +263,6 @@ struct dw_pcie {
/* Used when iatu_unroll_enabled is true */
void __iomem *atu_base;
u32 num_viewport;
- u8 iatu_unroll_enabled;
struct pcie_port pp;
struct dw_pcie_ep ep;
const struct dw_pcie_ops *ops;
@@ -274,6 +270,8 @@ struct dw_pcie {
int num_lanes;
int link_gen;
u8 n_fts[2];
+ bool iatu_unroll_enabled: 1;
+ bool io_cfg_atu_shared: 1;
};
#define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)