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| author | Bjorn Helgaas <bhelgaas@google.com> | 2020-06-04 12:59:15 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2020-06-04 12:59:15 -0500 |
| commit | b9fcf4910b72dd4d94b36989df5d6bcf7795c18d (patch) | |
| tree | cf1d51fe10b942f98b72c3bc945dbc6e2a628f67 /drivers/pci/controller/dwc/pcie-designware.h | |
| parent | 712879510fa4930b65748046426ac4a730512bba (diff) | |
| parent | 8d7e33d6811fbd24d3a1476a1b481b704975352a (diff) | |
Merge branch 'remotes/lorenzo/pci/dwc'
- Simplify computation of msix_tbl (Jiri Slaby)
- Make hisi_pcie_platform_ops static (Zou Wei)
- Warn about resources above 4G (Alan Mikhak)
- Make intel_pcie_cpu_addr() static (Jason Yan)
- Use devm_platform_ioremap_resource_byname() to simplify code and
improve error checking (Wei Yongjun)
- Fix inner MSI IRQ domain registration so it doesn't confuse debugfs
(Marc Zyngier)
- Don't use FAST_LINK_MODE on meson (Marc Zyngier)
- Add Socionext UniPhier Pro5 PCIe endpoint controller driver and DT
description (Kunihiko Hayashi)
* remotes/lorenzo/pci/dwc:
PCI: uniphier: Add Socionext UniPhier Pro5 PCIe endpoint controller driver
dt-bindings: PCI: Add UniPhier PCIe endpoint controller description
PCI: dwc: Use private data pointer of "struct irq_domain" to get pcie_port
PCI: amlogic: meson: Don't use FAST_LINK_MODE to set up link
PCI: dwc: Fix inner MSI IRQ domain registration
PCI: dwc: pci-dra7xx: Use devm_platform_ioremap_resource_byname()
PCI: dwc: intel: Make intel_pcie_cpu_addr() static
PCI: dwc: Program outbound ATU upper limit register
PCI: dwc: Make hisi_pcie_platform_ops static
PCI: dwc: Clean up computing of msix_tbl
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-designware.h')
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-designware.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index d6e1f397e6b0..656e00f8fbeb 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -112,9 +112,10 @@ #define PCIE_ATU_UNR_REGION_CTRL2 0x04 #define PCIE_ATU_UNR_LOWER_BASE 0x08 #define PCIE_ATU_UNR_UPPER_BASE 0x0C -#define PCIE_ATU_UNR_LIMIT 0x10 +#define PCIE_ATU_UNR_LOWER_LIMIT 0x10 #define PCIE_ATU_UNR_LOWER_TARGET 0x14 #define PCIE_ATU_UNR_UPPER_TARGET 0x18 +#define PCIE_ATU_UNR_UPPER_LIMIT 0x20 /* * The default address offset between dbi_base and atu_base. Root controller |