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authorMichael J. Ruhl <michael.j.ruhl@intel.com>2022-02-09 11:28:01 -0500
committerBjorn Helgaas <bhelgaas@google.com>2022-02-25 11:03:30 -0600
commitfeaea1fe8b36b2e5b12b2f9e6e050db28dfee789 (patch)
tree38a42e3bf52076a438216dfbe50287fccb10a092 /drivers/pci/p2pdma.c
parente783362eb54cd99b2cac8b3a9aeac942e6f6ac07 (diff)
PCI/P2PDMA: Add Intel 3rd Gen Intel Xeon Scalable Processors to whitelist
In order to do P2P communication the bridge ID of the platform must be in the P2P device table. Update the P2P device table with a device ID for the 3rd Gen Intel Xeon Scalable Processors. Link: https://lore.kernel.org/r/20220209162801.7647-1-michael.j.ruhl@intel.com Signed-off-by: Michael J. Ruhl <michael.j.ruhl@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/pci/p2pdma.c')
-rw-r--r--drivers/pci/p2pdma.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/pci/p2pdma.c b/drivers/pci/p2pdma.c
index 1015274bd2fe..30b1df3c9d2f 100644
--- a/drivers/pci/p2pdma.c
+++ b/drivers/pci/p2pdma.c
@@ -321,6 +321,7 @@ static const struct pci_p2pdma_whitelist_entry {
{PCI_VENDOR_ID_INTEL, 0x2032, 0},
{PCI_VENDOR_ID_INTEL, 0x2033, 0},
{PCI_VENDOR_ID_INTEL, 0x2020, 0},
+ {PCI_VENDOR_ID_INTEL, 0x09a2, 0},
{}
};