diff options
| author | Haneen Mohammed <hamohammed.sa@gmail.com> | 2015-03-22 21:23:23 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2015-03-23 22:21:58 +0100 |
| commit | 0c76706967dd15b58dfc132d1dc46e13edb86424 (patch) | |
| tree | 705baa06117da9eae1cb5849b237a4c21c18dbba /drivers/staging/iio/accel/adis16201.h | |
| parent | 6cf23dfffd3c69fc5cf5e2ca6fee0ab7eb316812 (diff) | |
Staging: iio: use the BIT macro in .h files
This patch replace bit shifting on 1, 2, and 3 with the BIT(x) macro.
Issue addressed by checkpatch.pl with --strict flag.
This was done with the help of Coccninelle:
@r1@
constant int g;
@@
(
0<<g
|
1<<g
|
2<<g
|
3<<g
)
@script:python b@
g2 <<r1.g;
y;
@@
coccinelle.y = int(g2) + 1
@c@
constant int r1.g;
identifier b.y;
@@
(
-(1 << g)
+BIT(g)
|
-(0 << g)
+ 0
|
-(2 << g)
+BIT(y)
|
-(3 << g)
+(BIT(y)| BIT(g))
)
Signed-off-by: Haneen Mohammed <hamohammed.sa@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/iio/accel/adis16201.h')
| -rw-r--r-- | drivers/staging/iio/accel/adis16201.h | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/staging/iio/accel/adis16201.h b/drivers/staging/iio/accel/adis16201.h index 8747de5a9805..e6b8c9af6e22 100644 --- a/drivers/staging/iio/accel/adis16201.h +++ b/drivers/staging/iio/accel/adis16201.h @@ -34,24 +34,24 @@ #define ADIS16201_GLOB_CMD 0x3E /* Operation, system command register */ /* MSC_CTRL */ -#define ADIS16201_MSC_CTRL_SELF_TEST_EN (1 << 8) /* Self-test enable */ -#define ADIS16201_MSC_CTRL_DATA_RDY_EN (1 << 2) /* Data-ready enable: 1 = enabled, 0 = disabled */ -#define ADIS16201_MSC_CTRL_ACTIVE_HIGH (1 << 1) /* Data-ready polarity: 1 = active high, 0 = active low */ -#define ADIS16201_MSC_CTRL_DATA_RDY_DIO1 (1 << 0) /* Data-ready line selection: 1 = DIO1, 0 = DIO0 */ +#define ADIS16201_MSC_CTRL_SELF_TEST_EN BIT(8) /* Self-test enable */ +#define ADIS16201_MSC_CTRL_DATA_RDY_EN BIT(2) /* Data-ready enable: 1 = enabled, 0 = disabled */ +#define ADIS16201_MSC_CTRL_ACTIVE_HIGH BIT(1) /* Data-ready polarity: 1 = active high, 0 = active low */ +#define ADIS16201_MSC_CTRL_DATA_RDY_DIO1 BIT(0) /* Data-ready line selection: 1 = DIO1, 0 = DIO0 */ /* DIAG_STAT */ -#define ADIS16201_DIAG_STAT_ALARM2 (1<<9) /* Alarm 2 status: 1 = alarm active, 0 = alarm inactive */ -#define ADIS16201_DIAG_STAT_ALARM1 (1<<8) /* Alarm 1 status: 1 = alarm active, 0 = alarm inactive */ +#define ADIS16201_DIAG_STAT_ALARM2 BIT(9) /* Alarm 2 status: 1 = alarm active, 0 = alarm inactive */ +#define ADIS16201_DIAG_STAT_ALARM1 BIT(8) /* Alarm 1 status: 1 = alarm active, 0 = alarm inactive */ #define ADIS16201_DIAG_STAT_SPI_FAIL_BIT 3 /* SPI communications failure */ #define ADIS16201_DIAG_STAT_FLASH_UPT_BIT 2 /* Flash update failure */ #define ADIS16201_DIAG_STAT_POWER_HIGH_BIT 1 /* Power supply above 3.625 V */ #define ADIS16201_DIAG_STAT_POWER_LOW_BIT 0 /* Power supply below 3.15 V */ /* GLOB_CMD */ -#define ADIS16201_GLOB_CMD_SW_RESET (1<<7) -#define ADIS16201_GLOB_CMD_FACTORY_CAL (1<<1) +#define ADIS16201_GLOB_CMD_SW_RESET BIT(7) +#define ADIS16201_GLOB_CMD_FACTORY_CAL BIT(1) -#define ADIS16201_ERROR_ACTIVE (1<<14) +#define ADIS16201_ERROR_ACTIVE BIT(14) enum adis16201_scan { ADIS16201_SCAN_ACC_X, |