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authorLucas De Marchi <lucas.demarchi@profusion.mobi>2011-03-30 22:57:33 -0300
committerLucas De Marchi <lucas.demarchi@profusion.mobi>2011-03-31 11:26:23 -0300
commit25985edcedea6396277003854657b5f3cb31a628 (patch)
treef026e810210a2ee7290caeb737c23cb6472b7c38 /drivers/staging/vme/bridges
parent6aba74f2791287ec407e0f92487a725a25908067 (diff)
Fix common misspellings
Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
Diffstat (limited to 'drivers/staging/vme/bridges')
-rw-r--r--drivers/staging/vme/bridges/vme_ca91cx42.c6
-rw-r--r--drivers/staging/vme/bridges/vme_tsi148.c4
-rw-r--r--drivers/staging/vme/bridges/vme_tsi148.h8
3 files changed, 9 insertions, 9 deletions
diff --git a/drivers/staging/vme/bridges/vme_ca91cx42.c b/drivers/staging/vme/bridges/vme_ca91cx42.c
index d4a48c4e59c2..a4007287ef47 100644
--- a/drivers/staging/vme/bridges/vme_ca91cx42.c
+++ b/drivers/staging/vme/bridges/vme_ca91cx42.c
@@ -621,7 +621,7 @@ static int ca91cx42_master_set(struct vme_master_resource *image, int enabled,
/*
* Let's allocate the resource here rather than further up the stack as
- * it avoids pushing loads of bus dependant stuff up the stack
+ * it avoids pushing loads of bus dependent stuff up the stack
*/
retval = ca91cx42_alloc_resource(image, size);
if (retval) {
@@ -1052,7 +1052,7 @@ static int ca91cx42_dma_list_add(struct vme_dma_list *list,
pci_attr = dest->private;
}
- /* Check we can do fullfill required attributes */
+ /* Check we can do fulfill required attributes */
if ((vme_attr->aspace & ~(VME_A16 | VME_A24 | VME_A32 | VME_USER1 |
VME_USER2)) != 0) {
@@ -1069,7 +1069,7 @@ static int ca91cx42_dma_list_add(struct vme_dma_list *list,
goto err_cycle;
}
- /* Check to see if we can fullfill source and destination */
+ /* Check to see if we can fulfill source and destination */
if (!(((src->type == VME_DMA_PCI) && (dest->type == VME_DMA_VME)) ||
((src->type == VME_DMA_VME) && (dest->type == VME_DMA_PCI)))) {
diff --git a/drivers/staging/vme/bridges/vme_tsi148.c b/drivers/staging/vme/bridges/vme_tsi148.c
index b00a53e793e7..106aa9daff48 100644
--- a/drivers/staging/vme/bridges/vme_tsi148.c
+++ b/drivers/staging/vme/bridges/vme_tsi148.c
@@ -928,7 +928,7 @@ static int tsi148_master_set(struct vme_master_resource *image, int enabled,
spin_lock(&image->lock);
/* Let's allocate the resource here rather than further up the stack as
- * it avoids pushing loads of bus dependant stuff up the stack. If size
+ * it avoids pushing loads of bus dependent stuff up the stack. If size
* is zero, any existing resource will be freed.
*/
retval = tsi148_alloc_resource(image, size);
@@ -1320,7 +1320,7 @@ static ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf,
/*
* Writes are posted. We need to do a read on the VME bus to flush out
- * all of the writes before we check for errors. We can't guarentee
+ * all of the writes before we check for errors. We can't guarantee
* that reading the data we have just written is safe. It is believed
* that there isn't any read, write re-ordering, so we can read any
* location in VME space, so lets read the Device ID from the tsi148's
diff --git a/drivers/staging/vme/bridges/vme_tsi148.h b/drivers/staging/vme/bridges/vme_tsi148.h
index 9f97fa8084e8..a3ac2fe98816 100644
--- a/drivers/staging/vme/bridges/vme_tsi148.h
+++ b/drivers/staging/vme/bridges/vme_tsi148.h
@@ -212,7 +212,7 @@ static const int TSI148_LCSR_OT[8] = { TSI148_LCSR_OT0, TSI148_LCSR_OT1,
#define TSI148_LCSR_OFFSET_OTAT 0x1C
/*
- * VMEbus interupt ack
+ * VMEbus interrupt ack
* offset 200
*/
#define TSI148_LCSR_VIACK1 0x204
@@ -613,7 +613,7 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
/*
* PCI-X Status Register (CRG +$054)
*/
-#define TSI148_PCFS_PCIXSTAT_RSCEM (1<<29) /* Recieved Split Comp Error */
+#define TSI148_PCFS_PCIXSTAT_RSCEM (1<<29) /* Received Split Comp Error */
#define TSI148_PCFS_PCIXSTAT_DMCRS_M (7<<26) /* max Cumulative Read Size */
#define TSI148_PCFS_PCIXSTAT_DMOST_M (7<<23) /* max outstanding Split Trans
*/
@@ -982,8 +982,8 @@ static const int TSI148_GCSR_MBOX[4] = { TSI148_GCSR_MBOX0,
#define TSI148_LCSR_VICR_CNTS_IRQ1 (2<<22) /* IRQ1 to Cntr */
#define TSI148_LCSR_VICR_CNTS_IRQ2 (3<<22) /* IRQ2 to Cntr */
-#define TSI148_LCSR_VICR_EDGIS_M (3<<20) /* Edge interupt MASK */
-#define TSI148_LCSR_VICR_EDGIS_DIS (1<<20) /* Edge interupt Disable */
+#define TSI148_LCSR_VICR_EDGIS_M (3<<20) /* Edge interrupt MASK */
+#define TSI148_LCSR_VICR_EDGIS_DIS (1<<20) /* Edge interrupt Disable */
#define TSI148_LCSR_VICR_EDGIS_IRQ1 (2<<20) /* IRQ1 to Edge */
#define TSI148_LCSR_VICR_EDGIS_IRQ2 (3<<20) /* IRQ2 to Edge */