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authorAlex Frid <afrid@nvidia.com>2017-07-25 13:34:13 +0300
committerStephen Boyd <sboyd@codeaurora.org>2017-08-23 16:00:23 -0700
commit2f924ac33f6bd46dcf1d1374401515ada5a35f21 (patch)
treeeb073265e05a04aa1d2588bcc6e2d411f922bba2 /lib/Kconfig.ubsan
parentf7bdb8b78a3d4b2f0ebd76e606ac6ca2925d7b02 (diff)
clk: tegra: Fix T210 PLLRE registration
Switched Tegra210 PLLRE registration to common PLL ops instead of special PLLRE ops used on previous Tegra chips. The latter ops do not follow chip specific PLL frequency table, and do not apply chip specific rate calculation method. Removed unnecessary default rate setting that duplicates h/w reset state, and is overwritten by clock initialization, anyway. Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'lib/Kconfig.ubsan')
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