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authorChen-Yu Tsai <wens@csie.org>2017-07-24 21:58:58 +0800
committerUlf Hansson <ulf.hansson@linaro.org>2017-08-30 14:01:48 +0200
commit81e911d0dcdb35203785542e0417cd8feb45df65 (patch)
tree0d5ada4405b192bfa9e03017306f77ee9a81eae1 /lib/locking-selftest-wlock.h
parentdc8797e39fca777217fd4cfc9c74a5337a3daa76 (diff)
clk: sunxi-ng: a83t: Support new timing mode for mmc2 clock
The MMC2 clock supports a new timing mode. When the new mode is active, the output clock rate is halved. This patch sets the feature flag for the new timing mode, and adds a pre-divider based on the mode bit. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'lib/locking-selftest-wlock.h')
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