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authorGil Fine <gil.fine@linux.intel.com>2023-08-10 22:37:15 +0300
committerMika Westerberg <mika.westerberg@linux.intel.com>2023-10-20 18:18:01 +0300
commit81af2952e60603d12415e1a6fd200f8073a2ad8b (patch)
treece083f20defdfd871574df8094610906b7195cb6 /scripts
parentc4ff14436952c3d0dd05769d76cf48e73a253b48 (diff)
thunderbolt: Add support for asymmetric link
USB4 v2 spec defines a Gen 4 link that can operate as an aggregated symmetric (80/80G) or asymmetric (120/40G). When the link is asymmetric, the USB4 port on one side of the link operates with three TX lanes and one RX lane, while the USB4 port on the opposite side of the link operates with three RX lanes and one TX lane. Add support for the asymmetric link and provide functions that can be used to transition the link to asymmetric and back. Signed-off-by: Gil Fine <gil.fine@linux.intel.com> Co-developed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
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