diff options
| author | Borislav Petkov <bp@suse.de> | 2021-03-18 16:43:11 +0100 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2021-03-18 16:43:11 +0100 |
| commit | afb4a37778491eae010a43edebea32ff2d45f01c (patch) | |
| tree | c40bcc6143e5542134477dd96a108d24b1f9074f /tools/include/linux/coresight-pmu.h | |
| parent | 229164175ff0c61ff581e6bf37fbfcb608b6e9bb (diff) | |
| parent | 1e28eed17697bcf343c6743f0028cc3b5dd88bf0 (diff) | |
Merge tag 'v5.12-rc3' into x86/seves
Pick up dependent SEV-ES urgent changes which went into -rc3 to base new
work ontop.
Signed-off-by: Borislav Petkov <bp@suse.de>
Diffstat (limited to 'tools/include/linux/coresight-pmu.h')
| -rw-r--r-- | tools/include/linux/coresight-pmu.h | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/tools/include/linux/coresight-pmu.h b/tools/include/linux/coresight-pmu.h index b0e35eec6499..4ac5c081af93 100644 --- a/tools/include/linux/coresight-pmu.h +++ b/tools/include/linux/coresight-pmu.h @@ -10,17 +10,27 @@ #define CORESIGHT_ETM_PMU_NAME "cs_etm" #define CORESIGHT_ETM_PMU_SEED 0x10 -/* ETMv3.5/PTM's ETMCR config bit */ -#define ETM_OPT_CYCACC 12 -#define ETM_OPT_CTXTID 14 -#define ETM_OPT_TS 28 -#define ETM_OPT_RETSTK 29 +/* + * Below are the definition of bit offsets for perf option, and works as + * arbitrary values for all ETM versions. + * + * Most of them are orignally from ETMv3.5/PTM's ETMCR config, therefore, + * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and + * directly use below macros as config bits. + */ +#define ETM_OPT_CYCACC 12 +#define ETM_OPT_CTXTID 14 +#define ETM_OPT_CTXTID2 15 +#define ETM_OPT_TS 28 +#define ETM_OPT_RETSTK 29 /* ETMv4 CONFIGR programming bits for the ETM OPTs */ #define ETM4_CFG_BIT_CYCACC 4 #define ETM4_CFG_BIT_CTXTID 6 +#define ETM4_CFG_BIT_VMID 7 #define ETM4_CFG_BIT_TS 11 #define ETM4_CFG_BIT_RETSTK 12 +#define ETM4_CFG_BIT_VMID_OPT 15 static inline int coresight_get_trace_id(int cpu) { |