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-rw-r--r--Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml64
-rw-r--r--Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml55
-rw-r--r--drivers/clk/rockchip/Kconfig14
-rw-r--r--drivers/clk/rockchip/Makefile2
-rw-r--r--drivers/clk/rockchip/clk-pll.c10
-rw-r--r--drivers/clk/rockchip/clk-rk3188.c4
-rw-r--r--drivers/clk/rockchip/clk-rk3328.c2
-rw-r--r--drivers/clk/rockchip/clk-rk3528.c1116
-rw-r--r--drivers/clk/rockchip/clk-rk3562.c1101
-rw-r--r--drivers/clk/rockchip/clk-rk3568.c1
-rw-r--r--drivers/clk/rockchip/clk.h63
-rw-r--r--drivers/clk/rockchip/rst-rk3528.c306
-rw-r--r--drivers/clk/rockchip/rst-rk3562.c429
-rw-r--r--include/dt-bindings/clock/rk3188-cru-common.h2
-rw-r--r--include/dt-bindings/clock/rockchip,rk3528-cru.h453
-rw-r--r--include/dt-bindings/clock/rockchip,rk3562-cru.h379
-rw-r--r--include/dt-bindings/reset/rockchip,rk3528-cru.h241
-rw-r--r--include/dt-bindings/reset/rockchip,rk3562-cru.h358
18 files changed, 4593 insertions, 7 deletions
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml
new file mode 100644
index 000000000000..5a3ec902351c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3528-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RK3528 Clock and Reset Controller
+
+maintainers:
+ - Yao Zi <ziyao@disroot.org>
+
+description: |
+ The RK3528 clock controller generates the clock and also implements a reset
+ controller for SoC peripherals. For example, it provides SCLK_UART0 and
+ PCLK_UART0 as well as SRST_P_UART0 and SRST_S_UART0 for the first UART
+ module.
+ Each clock is assigned an identifier, consumer nodes can use it to specify
+ the clock. All available clock and reset IDs are defined in dt-binding
+ headers.
+
+properties:
+ compatible:
+ const: rockchip,rk3528-cru
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: External 24MHz oscillator clock
+ - description: >
+ 50MHz clock generated by PHY module, for generating GMAC0 clocks only.
+
+ clock-names:
+ items:
+ - const: xin24m
+ - const: gmac0
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@ff4a0000 {
+ compatible = "rockchip,rk3528-cru";
+ reg = <0xff4a0000 0x30000>;
+ clocks = <&xin24m>, <&gmac0_clk>;
+ clock-names = "xin24m", "gmac0";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml
new file mode 100644
index 000000000000..36a353f5c42a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3562-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip rk3562 Clock and Reset Control Module
+
+maintainers:
+ - Elaine Zhang <zhangqing@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description:
+ The RK3562 clock controller generates the clock and also implements a reset
+ controller for SoC peripherals. For example it provides SCLK_UART2 and
+ PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART
+ module.
+
+properties:
+ compatible:
+ const: rockchip,rk3562-cru
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: xin24m
+ - const: xin32k
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@ff100000 {
+ compatible = "rockchip,rk3562-cru";
+ reg = <0xff100000 0x40000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig
index 570ad90835d3..febb7944f34b 100644
--- a/drivers/clk/rockchip/Kconfig
+++ b/drivers/clk/rockchip/Kconfig
@@ -93,6 +93,20 @@ config CLK_RK3399
help
Build the driver for RK3399 Clock Driver.
+config CLK_RK3528
+ bool "Rockchip RK3528 clock controller support"
+ depends on ARM64 || COMPILE_TEST
+ default y
+ help
+ Build the driver for RK3528 Clock Controller.
+
+config CLK_RK3562
+ bool "Rockchip RK3562 clock controller support"
+ depends on ARM64 || COMPILE_TEST
+ default y
+ help
+ Build the driver for RK3562 Clock Controller.
+
config CLK_RK3568
bool "Rockchip RK3568 clock controller support"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 3fe7616f0ebe..e8ece20aebfd 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -28,6 +28,8 @@ obj-$(CONFIG_CLK_RK3308) += clk-rk3308.o
obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o
obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o
obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o
+obj-$(CONFIG_CLK_RK3528) += clk-rk3528.o rst-rk3528.o
+obj-$(CONFIG_CLK_RK3562) += clk-rk3562.o rst-rk3562.o
obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o
obj-$(CONFIG_CLK_RK3576) += clk-rk3576.o rst-rk3576.o
obj-$(CONFIG_CLK_RK3588) += clk-rk3588.o rst-rk3588.o
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index fe76756e592e..2c2abb3b4210 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -204,10 +204,12 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
rockchip_rk3036_pll_get_params(pll, &cur);
cur.rate = 0;
- cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
- if (cur_parent == PLL_MODE_NORM) {
- pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
- rate_change_remuxed = 1;
+ if (!(pll->flags & ROCKCHIP_PLL_FIXED_MODE)) {
+ cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
+ if (cur_parent == PLL_MODE_NORM) {
+ pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
+ rate_change_remuxed = 1;
+ }
}
/* update pll values */
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index 30e670c8afba..318c8ddc8a76 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -337,7 +337,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
GATE(0, "pclkin_cif0", "ext_cif0", 0,
RK2928_CLKGATE_CON(3), 3, GFLAGS),
- INVERTER(0, "pclk_cif0", "pclkin_cif0",
+ INVERTER(PCLK_CIF0, "pclk_cif0", "pclkin_cif0",
RK2928_CLKSEL_CON(30), 8, IFLAGS),
FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
@@ -595,7 +595,7 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
GATE(0, "pclkin_cif1", "ext_cif1", 0,
RK2928_CLKGATE_CON(3), 4, GFLAGS),
- INVERTER(0, "pclk_cif1", "pclkin_cif1",
+ INVERTER(PCLK_CIF1, "pclk_cif1", "pclkin_cif1",
RK2928_CLKSEL_CON(30), 12, IFLAGS),
COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
index 3bb87b27b662..cf60fcf2fa5c 100644
--- a/drivers/clk/rockchip/clk-rk3328.c
+++ b/drivers/clk/rockchip/clk-rk3328.c
@@ -201,7 +201,7 @@ PNAME(mux_aclk_peri_pre_p) = { "cpll_peri",
"gpll_peri",
"hdmiphy_peri" };
PNAME(mux_ref_usb3otg_src_p) = { "xin24m",
- "clk_usb3otg_ref" };
+ "clk_ref_usb3otg_src" };
PNAME(mux_xin24m_32k_p) = { "xin24m",
"clk_rtc32k" };
PNAME(mux_mac2io_src_p) = { "clk_mac2io_src",
diff --git a/drivers/clk/rockchip/clk-rk3528.c b/drivers/clk/rockchip/clk-rk3528.c
new file mode 100644
index 000000000000..b8b577b902a0
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3528.c
@@ -0,0 +1,1116 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
+ * Author: Joseph Chen <chenjh@rock-chips.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/rockchip,rk3528-cru.h>
+
+#include "clk.h"
+
+#define RK3528_GRF_SOC_STATUS0 0x1a0
+
+enum rk3528_plls {
+ apll, cpll, gpll, ppll, dpll,
+};
+
+static struct rockchip_pll_rate_table rk3528_pll_rates[] = {
+ RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), /* GPLL */
+ RK3036_PLL_RATE(1092000000, 2, 91, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1008000000, 1, 42, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), /* PPLL */
+ RK3036_PLL_RATE(996000000, 2, 83, 1, 1, 1, 0), /* CPLL */
+ RK3036_PLL_RATE(960000000, 1, 40, 1, 1, 1, 0),
+ RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
+ RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
+ RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0),
+ RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
+ RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
+ RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
+ RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
+ RK3036_PLL_RATE(96000000, 1, 24, 3, 2, 1, 0),
+ { /* sentinel */ },
+};
+
+#define RK3528_DIV_ACLK_M_CORE_MASK 0x1f
+#define RK3528_DIV_ACLK_M_CORE_SHIFT 11
+#define RK3528_DIV_PCLK_DBG_MASK 0x1f
+#define RK3528_DIV_PCLK_DBG_SHIFT 1
+
+#define RK3528_CLKSEL39(_aclk_m_core) \
+{ \
+ .reg = RK3528_CLKSEL_CON(39), \
+ .val = HIWORD_UPDATE(_aclk_m_core, RK3528_DIV_ACLK_M_CORE_MASK, \
+ RK3528_DIV_ACLK_M_CORE_SHIFT), \
+}
+
+#define RK3528_CLKSEL40(_pclk_dbg) \
+{ \
+ .reg = RK3528_CLKSEL_CON(40), \
+ .val = HIWORD_UPDATE(_pclk_dbg, RK3528_DIV_PCLK_DBG_MASK, \
+ RK3528_DIV_PCLK_DBG_SHIFT), \
+}
+
+#define RK3528_CPUCLK_RATE(_prate, _aclk_m_core, _pclk_dbg) \
+{ \
+ .prate = _prate, \
+ .divs = { \
+ RK3528_CLKSEL39(_aclk_m_core), \
+ RK3528_CLKSEL40(_pclk_dbg), \
+ }, \
+}
+
+static struct rockchip_cpuclk_rate_table rk3528_cpuclk_rates[] __initdata = {
+ RK3528_CPUCLK_RATE(1896000000, 1, 13),
+ RK3528_CPUCLK_RATE(1800000000, 1, 12),
+ RK3528_CPUCLK_RATE(1704000000, 1, 11),
+ RK3528_CPUCLK_RATE(1608000000, 1, 11),
+ RK3528_CPUCLK_RATE(1512000000, 1, 11),
+ RK3528_CPUCLK_RATE(1416000000, 1, 9),
+ RK3528_CPUCLK_RATE(1296000000, 1, 8),
+ RK3528_CPUCLK_RATE(1200000000, 1, 8),
+ RK3528_CPUCLK_RATE(1188000000, 1, 8),
+ RK3528_CPUCLK_RATE(1092000000, 1, 7),
+ RK3528_CPUCLK_RATE(1008000000, 1, 6),
+ RK3528_CPUCLK_RATE(1000000000, 1, 6),
+ RK3528_CPUCLK_RATE(996000000, 1, 6),
+ RK3528_CPUCLK_RATE(960000000, 1, 6),
+ RK3528_CPUCLK_RATE(912000000, 1, 6),
+ RK3528_CPUCLK_RATE(816000000, 1, 5),
+ RK3528_CPUCLK_RATE(600000000, 1, 3),
+ RK3528_CPUCLK_RATE(594000000, 1, 3),
+ RK3528_CPUCLK_RATE(408000000, 1, 2),
+ RK3528_CPUCLK_RATE(312000000, 1, 2),
+ RK3528_CPUCLK_RATE(216000000, 1, 1),
+ RK3528_CPUCLK_RATE(96000000, 1, 0),
+};
+
+static const struct rockchip_cpuclk_reg_data rk3528_cpuclk_data = {
+ .core_reg[0] = RK3528_CLKSEL_CON(39),
+ .div_core_shift[0] = 5,
+ .div_core_mask[0] = 0x1f,
+ .num_cores = 1,
+ .mux_core_alt = 1,
+ .mux_core_main = 0,
+ .mux_core_shift = 10,
+ .mux_core_mask = 0x1,
+};
+
+PNAME(mux_pll_p) = { "xin24m" };
+PNAME(mux_armclk) = { "apll", "gpll" };
+PNAME(mux_24m_32k_p) = { "xin24m", "clk_32k" };
+PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
+PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
+PNAME(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src",
+ "xin24m" };
+PNAME(mux_150m_100m_24m_p) = { "clk_150m_src", "clk_100m_src",
+ "xin24m" };
+PNAME(mux_200m_100m_24m_p) = { "clk_200m_src", "clk_100m_src",
+ "xin24m" };
+PNAME(mux_200m_100m_50m_24m_p) = { "clk_200m_src", "clk_100m_src",
+ "clk_50m_src", "xin24m" };
+PNAME(mux_300m_200m_100m_24m_p) = { "clk_300m_src", "clk_200m_src",
+ "clk_100m_src", "xin24m" };
+PNAME(mux_339m_200m_100m_24m_p) = { "clk_339m_src", "clk_200m_src",
+ "clk_100m_src", "xin24m" };
+PNAME(mux_500m_200m_100m_24m_p) = { "clk_500m_src", "clk_200m_src",
+ "clk_100m_src", "xin24m" };
+PNAME(mux_500m_300m_100m_24m_p) = { "clk_500m_src", "clk_300m_src",
+ "clk_100m_src", "xin24m" };
+PNAME(mux_600m_300m_200m_24m_p) = { "clk_600m_src", "clk_300m_src",
+ "clk_200m_src", "xin24m" };
+PNAME(aclk_gpu_p) = { "aclk_gpu_root",
+ "clk_gpu_pvtpll_src" };
+PNAME(aclk_rkvdec_pvtmux_root_p) = { "aclk_rkvdec_root",
+ "clk_rkvdec_pvtpll_src" };
+PNAME(clk_i2c2_p) = { "clk_200m_src", "clk_100m_src",
+ "xin24m", "clk_32k" };
+PNAME(clk_ref_pcie_inner_phy_p) = { "clk_ppll_100m_src", "xin24m" };
+PNAME(dclk_vop0_p) = { "dclk_vop_src0",
+ "clk_hdmiphy_pixel_io" };
+PNAME(mclk_i2s0_2ch_sai_src_p) = { "clk_i2s0_2ch_src",
+ "clk_i2s0_2ch_frac", "xin12m" };
+PNAME(mclk_i2s1_8ch_sai_src_p) = { "clk_i2s1_8ch_src",
+ "clk_i2s1_8ch_frac", "xin12m" };
+PNAME(mclk_i2s2_2ch_sai_src_p) = { "clk_i2s2_2ch_src",
+ "clk_i2s2_2ch_frac", "xin12m" };
+PNAME(mclk_i2s3_8ch_sai_src_p) = { "clk_i2s3_8ch_src",
+ "clk_i2s3_8ch_frac", "xin12m" };
+PNAME(mclk_sai_i2s0_p) = { "mclk_i2s0_2ch_sai_src",
+ "i2s0_mclkin" };
+PNAME(mclk_sai_i2s1_p) = { "mclk_i2s1_8ch_sai_src",
+ "i2s1_mclkin" };
+PNAME(mclk_spdif_src_p) = { "clk_spdif_src", "clk_spdif_frac",
+ "xin12m" };
+PNAME(sclk_uart0_src_p) = { "clk_uart0_src", "clk_uart0_frac",
+ "xin24m" };
+PNAME(sclk_uart1_src_p) = { "clk_uart1_src", "clk_uart1_frac",
+ "xin24m" };
+PNAME(sclk_uart2_src_p) = { "clk_uart2_src", "clk_uart2_frac",
+ "xin24m" };
+PNAME(sclk_uart3_src_p) = { "clk_uart3_src", "clk_uart3_frac",
+ "xin24m" };
+PNAME(sclk_uart4_src_p) = { "clk_uart4_src", "clk_uart4_frac",
+ "xin24m" };
+PNAME(sclk_uart5_src_p) = { "clk_uart5_src", "clk_uart5_frac",
+ "xin24m" };
+PNAME(sclk_uart6_src_p) = { "clk_uart6_src", "clk_uart6_frac",
+ "xin24m" };
+PNAME(sclk_uart7_src_p) = { "clk_uart7_src", "clk_uart7_frac",
+ "xin24m" };
+PNAME(clk_32k_p) = { "xin_osc0_div", "clk_pvtm_32k" };
+
+static struct rockchip_pll_clock rk3528_pll_clks[] __initdata = {
+ [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
+ CLK_IS_CRITICAL, RK3528_PLL_CON(0),
+ RK3528_MODE_CON, 0, 0, 0, rk3528_pll_rates),
+
+ [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
+ CLK_IS_CRITICAL, RK3528_PLL_CON(8),
+ RK3528_MODE_CON, 2, 0, 0, rk3528_pll_rates),
+
+ [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
+ CLK_IS_CRITICAL, RK3528_PLL_CON(24),
+ RK3528_MODE_CON, 4, 0, 0, rk3528_pll_rates),
+
+ [ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p,
+ CLK_IS_CRITICAL, RK3528_PCIE_PLL_CON(32),
+ RK3528_MODE_CON, 6, 0, ROCKCHIP_PLL_FIXED_MODE, rk3528_pll_rates),
+
+ [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
+ CLK_IGNORE_UNUSED, RK3528_DDRPHY_PLL_CON(16),
+ RK3528_DDRPHY_MODE_CON, 0, 0, 0, rk3528_pll_rates),
+};
+
+#define MFLAGS CLK_MUX_HIWORD_MASK
+#define DFLAGS CLK_DIVIDER_HIWORD_MASK
+#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
+
+static struct rockchip_clk_branch rk3528_uart0_fracmux __initdata =
+ MUX(CLK_UART0, "clk_uart0", sclk_uart0_src_p, CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(6), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3528_uart1_fracmux __initdata =
+ MUX(CLK_UART1, "clk_uart1", sclk_uart1_src_p, CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(8), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3528_uart2_fracmux __initdata =
+ MUX(CLK_UART2, "clk_uart2", sclk_uart2_src_p, CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(10), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3528_uart3_fracmux __initdata =
+ MUX(CLK_UART3, "clk_uart3", sclk_uart3_src_p, CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(12), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3528_uart4_fracmux __initdata =
+ MUX(CLK_UART4, "clk_uart4", sclk_uart4_src_p, CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(14), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3528_uart5_fracmux __initdata =
+ MUX(CLK_UART5, "clk_uart5", sclk_uart5_src_p, CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(16), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3528_uart6_fracmux __initdata =
+ MUX(CLK_UART6, "clk_uart6", sclk_uart6_src_p, CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(18), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3528_uart7_fracmux __initdata =
+ MUX(CLK_UART7, "clk_uart7", sclk_uart7_src_p, CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(20), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch mclk_i2s0_2ch_sai_src_fracmux __initdata =
+ MUX(MCLK_I2S0_2CH_SAI_SRC_PRE, "mclk_i2s0_2ch_sai_src_pre", mclk_i2s0_2ch_sai_src_p, CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(22), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch mclk_i2s1_8ch_sai_src_fracmux __initdata =
+ MUX(MCLK_I2S1_8CH_SAI_SRC_PRE, "mclk_i2s1_8ch_sai_src_pre", mclk_i2s1_8ch_sai_src_p, CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(26), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch mclk_i2s2_2ch_sai_src_fracmux __initdata =
+ MUX(MCLK_I2S2_2CH_SAI_SRC_PRE, "mclk_i2s2_2ch_sai_src_pre", mclk_i2s2_2ch_sai_src_p, CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(28), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch mclk_i2s3_8ch_sai_src_fracmux __initdata =
+ MUX(MCLK_I2S3_8CH_SAI_SRC_PRE, "mclk_i2s3_8ch_sai_src_pre", mclk_i2s3_8ch_sai_src_p, CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(24), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch mclk_spdif_src_fracmux __initdata =
+ MUX(MCLK_SDPDIF_SRC_PRE, "mclk_spdif_src_pre", mclk_spdif_src_p, CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(32), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3528_clk_branches[] __initdata = {
+ /* top */
+ FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
+
+ COMPOSITE(CLK_MATRIX_250M_SRC, "clk_250m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(1), 15, 1, MFLAGS, 10, 5, DFLAGS,
+ RK3528_CLKGATE_CON(0), 5, GFLAGS),
+ COMPOSITE(CLK_MATRIX_500M_SRC, "clk_500m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS,
+ RK3528_CLKGATE_CON(0), 10, GFLAGS),
+ COMPOSITE_NOMUX(CLK_MATRIX_50M_SRC, "clk_50m_src", "cpll", CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(0), 2, 5, DFLAGS,
+ RK3528_CLKGATE_CON(0), 1, GFLAGS),
+ COMPOSITE_NOMUX(CLK_MATRIX_100M_SRC, "clk_100m_src", "cpll", CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(0), 7, 5, DFLAGS,
+ RK3528_CLKGATE_CON(0), 2, GFLAGS),
+ COMPOSITE_NOMUX(CLK_MATRIX_150M_SRC, "clk_150m_src", "gpll", CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(1), 0, 5, DFLAGS,
+ RK3528_CLKGATE_CON(0), 3, GFLAGS),
+ COMPOSITE_NOMUX(CLK_MATRIX_200M_SRC, "clk_200m_src", "gpll", CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(1), 5, 5, DFLAGS,
+ RK3528_CLKGATE_CON(0), 4, GFLAGS),
+ COMPOSITE_NOMUX(CLK_MATRIX_300M_SRC, "clk_300m_src", "gpll", CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(2), 0, 5, DFLAGS,
+ RK3528_CLKGATE_CON(0), 6, GFLAGS),
+ COMPOSITE_NOMUX_HALFDIV(CLK_MATRIX_339M_SRC, "clk_339m_src", "gpll", CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(2), 5, 5, DFLAGS,
+ RK3528_CLKGATE_CON(0), 7, GFLAGS),
+ COMPOSITE_NOMUX(CLK_MATRIX_400M_SRC, "clk_400m_src", "gpll", CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(2), 10, 5, DFLAGS,
+ RK3528_CLKGATE_CON(0), 8, GFLAGS),
+ COMPOSITE_NOMUX(CLK_MATRIX_600M_SRC, "clk_600m_src", "gpll", CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(4), 0, 5, DFLAGS,
+ RK3528_CLKGATE_CON(0), 11, GFLAGS),
+ COMPOSITE(DCLK_VOP_SRC0, "dclk_vop_src0", mux_gpll_cpll_p, 0,
+ RK3528_CLKSEL_CON(32), 10, 1, MFLAGS, 2, 8, DFLAGS,
+ RK3528_CLKGATE_CON(3), 7, GFLAGS),
+ COMPOSITE(DCLK_VOP_SRC1, "dclk_vop_src1", mux_gpll_cpll_p, 0,
+ RK3528_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 8, DFLAGS,
+ RK3528_CLKGATE_CON(3), 8, GFLAGS),
+ COMPOSITE_NOMUX(CLK_HSM, "clk_hsm", "xin24m", 0,
+ RK3528_CLKSEL_CON(36), 5, 5, DFLAGS,
+ RK3528_CLKGATE_CON(3), 13, GFLAGS),
+
+ COMPOSITE_NOMUX(CLK_UART0_SRC, "clk_uart0_src", "gpll", 0,
+ RK3528_CLKSEL_CON(4), 5, 5, DFLAGS,
+ RK3528_CLKGATE_CON(0), 12, GFLAGS),
+ COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(5), 0,
+ RK3528_CLKGATE_CON(0), 13, GFLAGS,
+ &rk3528_uart0_fracmux),
+ GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0,
+ RK3528_CLKGATE_CON(0), 14, GFLAGS),
+
+ COMPOSITE_NOMUX(CLK_UART1_SRC, "clk_uart1_src", "gpll", 0,
+ RK3528_CLKSEL_CON(6), 2, 5, DFLAGS,
+ RK3528_CLKGATE_CON(0), 15, GFLAGS),
+ COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(7), 0,
+ RK3528_CLKGATE_CON(1), 0, GFLAGS,
+ &rk3528_uart1_fracmux),
+ GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0,
+ RK3528_CLKGATE_CON(1), 1, GFLAGS),
+
+ COMPOSITE_NOMUX(CLK_UART2_SRC, "clk_uart2_src", "gpll", 0,
+ RK3528_CLKSEL_CON(8), 2, 5, DFLAGS,
+ RK3528_CLKGATE_CON(1), 2, GFLAGS),
+ COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(9), 0,
+ RK3528_CLKGATE_CON(1), 3, GFLAGS,
+ &rk3528_uart2_fracmux),
+ GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0,
+ RK3528_CLKGATE_CON(1), 4, GFLAGS),
+
+ COMPOSITE_NOMUX(CLK_UART3_SRC, "clk_uart3_src", "gpll", 0,
+ RK3528_CLKSEL_CON(10), 2, 5, DFLAGS,
+ RK3528_CLKGATE_CON(1), 5, GFLAGS),
+ COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(11), 0,
+ RK3528_CLKGATE_CON(1), 6, GFLAGS,
+ &rk3528_uart3_fracmux),
+ GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0,
+ RK3528_CLKGATE_CON(1), 7, GFLAGS),
+
+ COMPOSITE_NOMUX(CLK_UART4_SRC, "clk_uart4_src", "gpll", 0,
+ RK3528_CLKSEL_CON(12), 2, 5, DFLAGS,
+ RK3528_CLKGATE_CON(1), 8, GFLAGS),
+ COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(13), 0,
+ RK3528_CLKGATE_CON(1), 9, GFLAGS,
+ &rk3528_uart4_fracmux),
+ GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0,
+ RK3528_CLKGATE_CON(1), 10, GFLAGS),
+
+ COMPOSITE_NOMUX(CLK_UART5_SRC, "clk_uart5_src", "gpll", 0,
+ RK3528_CLKSEL_CON(14), 2, 5, DFLAGS,
+ RK3528_CLKGATE_CON(1), 11, GFLAGS),
+ COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(15), 0,
+ RK3528_CLKGATE_CON(1), 12, GFLAGS,
+ &rk3528_uart5_fracmux),
+ GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
+ RK3528_CLKGATE_CON(1), 13, GFLAGS),
+
+ COMPOSITE_NOMUX(CLK_UART6_SRC, "clk_uart6_src", "gpll", 0,
+ RK3528_CLKSEL_CON(16), 2, 5, DFLAGS,
+ RK3528_CLKGATE_CON(1), 14, GFLAGS),
+ COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(17), 0,
+ RK3528_CLKGATE_CON(1), 15, GFLAGS,
+ &rk3528_uart6_fracmux),
+ GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0,
+ RK3528_CLKGATE_CON(2), 0, GFLAGS),
+
+ COMPOSITE_NOMUX(CLK_UART7_SRC, "clk_uart7_src", "gpll", 0,
+ RK3528_CLKSEL_CON(18), 2, 5, DFLAGS,
+ RK3528_CLKGATE_CON(2), 1, GFLAGS),
+ COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(19), 0,
+ RK3528_CLKGATE_CON(2), 2, GFLAGS,
+ &rk3528_uart7_fracmux),
+ GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0,
+ RK3528_CLKGATE_CON(2), 3, GFLAGS),
+
+ COMPOSITE_NOMUX(CLK_I2S0_2CH_SRC, "clk_i2s0_2ch_src", "gpll", 0,
+ RK3528_CLKSEL_CON(20), 8, 5, DFLAGS,
+ RK3528_CLKGATE_CON(2), 5, GFLAGS),
+ COMPOSITE_FRACMUX(CLK_I2S0_2CH_FRAC, "clk_i2s0_2ch_frac", "clk_i2s0_2ch_src", CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(21), 0,
+ RK3528_CLKGATE_CON(2), 6, GFLAGS,
+ &mclk_i2s0_2ch_sai_src_fracmux),
+ GATE(MCLK_I2S0_2CH_SAI_SRC, "mclk_i2s0_2ch_sai_src", "mclk_i2s0_2ch_sai_src_pre", 0,
+ RK3528_CLKGATE_CON(2), 7, GFLAGS),
+
+ COMPOSITE_NOMUX(CLK_I2S1_8CH_SRC, "clk_i2s1_8ch_src", "gpll", 0,
+ RK3528_CLKSEL_CON(24), 3, 5, DFLAGS,
+ RK3528_CLKGATE_CON(2), 11, GFLAGS),
+ COMPOSITE_FRACMUX(CLK_I2S1_8CH_FRAC, "clk_i2s1_8ch_frac", "clk_i2s1_8ch_src", CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(25), 0,
+ RK3528_CLKGATE_CON(2), 12, GFLAGS,
+ &mclk_i2s1_8ch_sai_src_fracmux),
+ GATE(MCLK_I2S1_8CH_SAI_SRC, "mclk_i2s1_8ch_sai_src", "mclk_i2s1_8ch_sai_src_pre", 0,
+ RK3528_CLKGATE_CON(2), 13, GFLAGS),
+
+ COMPOSITE_NOMUX(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", "gpll", 0,
+ RK3528_CLKSEL_CON(26), 3, 5, DFLAGS,
+ RK3528_CLKGATE_CON(2), 14, GFLAGS),
+ COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(27), 0,
+ RK3528_CLKGATE_CON(2), 15, GFLAGS,
+ &mclk_i2s2_2ch_sai_src_fracmux),
+ GATE(MCLK_I2S2_2CH_SAI_SRC, "mclk_i2s2_2ch_sai_src", "mclk_i2s2_2ch_sai_src_pre", 0,
+ RK3528_CLKGATE_CON(3), 0, GFLAGS),
+
+ COMPOSITE_NOMUX(CLK_I2S3_8CH_SRC, "clk_i2s3_8ch_src", "gpll", 0,
+ RK3528_CLKSEL_CON(22), 3, 5, DFLAGS,
+ RK3528_CLKGATE_CON(2), 8, GFLAGS),
+ COMPOSITE_FRACMUX(CLK_I2S3_8CH_FRAC, "clk_i2s3_8ch_frac", "clk_i2s3_8ch_src", CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(23), 0,
+ RK3528_CLKGATE_CON(2), 9, GFLAGS,
+ &mclk_i2s3_8ch_sai_src_fracmux),
+ GATE(MCLK_I2S3_8CH_SAI_SRC, "mclk_i2s3_8ch_sai_src", "mclk_i2s3_8ch_sai_src_pre", 0,
+ RK3528_CLKGATE_CON(2), 10, GFLAGS),
+
+ COMPOSITE_NOMUX(CLK_SPDIF_SRC, "clk_spdif_src", "gpll", 0,
+ RK3528_CLKSEL_CON(30), 2, 5, DFLAGS,
+ RK3528_CLKGATE_CON(3), 4, GFLAGS),
+ COMPOSITE_FRACMUX(CLK_SPDIF_FRAC, "clk_spdif_frac", "clk_spdif_src", CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(31), 0,
+ RK3528_CLKGATE_CON(3), 5, GFLAGS,
+ &mclk_spdif_src_fracmux),
+ GATE(MCLK_SPDIF_SRC, "mclk_spdif_src", "mclk_spdif_src_pre", 0,
+ RK3528_CLKGATE_CON(3), 6, GFLAGS),
+
+ /* bus */
+ COMPOSITE_NODIV(ACLK_BUS_M_ROOT, "aclk_bus_m_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(43), 12, 2, MFLAGS,
+ RK3528_CLKGATE_CON(8), 7, GFLAGS),
+ GATE(ACLK_GIC, "aclk_gic", "aclk_bus_m_root", CLK_IS_CRITICAL,
+ RK3528_CLKGATE_CON(9), 1, GFLAGS),
+
+ COMPOSITE_NODIV(ACLK_BUS_ROOT, "aclk_bus_root", mux_200m_100m_24m_p, CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(43), 6, 2, MFLAGS,
+ RK3528_CLKGATE_CON(8), 4, GFLAGS),
+ GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", 0,
+ RK3528_CLKGATE_CON(9), 2, GFLAGS),
+ GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_root", 0,
+ RK3528_CLKGATE_CON(9), 4, GFLAGS),
+ GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_root", 0,
+ RK3528_CLKGATE_CON(11), 11, GFLAGS),
+ COMPOSITE(ACLK_BUS_VOPGL_ROOT, "aclk_bus_vopgl_root", mux_gpll_cpll_p, CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(43), 3, 1, MFLAGS, 0, 3, DFLAGS,
+ RK3528_CLKGATE_CON(8), 0, GFLAGS),
+ COMPOSITE_NODIV(ACLK_BUS_H_ROOT, "aclk_bus_h_root", mux_500m_200m_100m_24m_p, CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(43), 4, 2, MFLAGS,
+ RK3528_CLKGATE_CON(8), 2, GFLAGS),
+ GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_bus_h_root", 0,
+ RK3528_CLKGATE_CON(10), 14, GFLAGS),
+
+ COMPOSITE_NODIV(HCLK_BUS_ROOT, "hclk_bus_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(43), 8, 2, MFLAGS,
+ RK3528_CLKGATE_CON(8), 5, GFLAGS),
+
+ COMPOSITE_NODIV(PCLK_BUS_ROOT, "pclk_bus_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(43), 10, 2, MFLAGS,
+ RK3528_CLKGATE_CON(8), 6, GFLAGS),
+ GATE(PCLK_DFT2APB, "pclk_dft2apb", "pclk_bus_root", 0,
+ RK3528_CLKGATE_CON(8), 13, GFLAGS),
+ GATE(PCLK_BUS_GRF, "pclk_bus_grf", "pclk_bus_root", CLK_IS_CRITICAL,
+ RK3528_CLKGATE_CON(8), 15, GFLAGS),
+ GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_root", 0,
+ RK3528_CLKGATE_CON(9), 5, GFLAGS),
+ GATE(PCLK_JDBCK_DAP, "pclk_jdbck_dap", "pclk_bus_root", 0,
+ RK3528_CLKGATE_CON(9), 12, GFLAGS),
+ GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus_root", 0,
+ RK3528_CLKGATE_CON(9), 15, GFLAGS),
+ GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_root", 0,
+ RK3528_CLKGATE_CON(10), 7, GFLAGS),
+ GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_root", 0,
+ RK3528_CLKGATE_CON(11), 4, GFLAGS),
+ GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_root", 0,
+ RK3528_CLKGATE_CON(11), 7, GFLAGS),
+ GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_bus_root", 0,
+ RK3528_CLKGATE_CON(10), 13, GFLAGS),
+ GATE(PCLK_SCR, "pclk_scr", "pclk_bus_root", 0,
+ RK3528_CLKGATE_CON(11), 10, GFLAGS),
+ GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus_root", CLK_IGNORE_UNUSED,
+ RK3528_CLKGATE_CON(11), 12, GFLAGS),
+
+ COMPOSITE_NODIV(CLK_PWM0, "clk_pwm0", mux_100m_50m_24m_p, 0,
+ RK3528_CLKSEL_CON(44), 6, 2, MFLAGS,
+ RK3528_CLKGATE_CON(11), 5, GFLAGS),
+ COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_50m_24m_p, 0,
+ RK3528_CLKSEL_CON(44), 8, 2, MFLAGS,
+ RK3528_CLKGATE_CON(11), 8, GFLAGS),
+
+ GATE(CLK_CAPTURE_PWM1, "clk_capture_pwm1", "xin24m", 0,
+ RK3528_CLKGATE_CON(11), 9, GFLAGS),
+ GATE(CLK_CAPTURE_PWM0, "clk_capture_pwm0", "xin24m", 0,
+ RK3528_CLKGATE_CON(11), 6, GFLAGS),
+ GATE(CLK_JDBCK_DAP, "clk_jdbck_dap", "xin24m", 0,
+ RK3528_CLKGATE_CON(9), 13, GFLAGS),
+ GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0,
+ RK3528_CLKGATE_CON(10), 0, GFLAGS),
+
+ GATE(CLK_TIMER_ROOT, "clk_timer_root", "xin24m", 0,
+ RK3528_CLKGATE_CON(8), 9, GFLAGS),
+ GATE(CLK_TIMER0, "clk_timer0", "clk_timer_root", 0,
+ RK3528_CLKGATE_CON(9), 6, GFLAGS),
+ GATE(CLK_TIMER1, "clk_timer1", "clk_timer_root", 0,
+ RK3528_CLKGATE_CON(9), 7, GFLAGS),
+ GATE(CLK_TIMER2, "clk_timer2", "clk_timer_root", 0,
+ RK3528_CLKGATE_CON(9), 8, GFLAGS),
+ GATE(CLK_TIMER3, "clk_timer3", "clk_timer_root", 0,
+ RK3528_CLKGATE_CON(9), 9, GFLAGS),
+ GATE(CLK_TIMER4, "clk_timer4", "clk_timer_root", 0,
+ RK3528_CLKGATE_CON(9), 10, GFLAGS),
+ GATE(CLK_TIMER5, "clk_timer5", "clk_timer_root", 0,
+ RK3528_CLKGATE_CON(9), 11, GFLAGS),
+
+ /* pmu */
+ GATE(HCLK_PMU_ROOT, "hclk_pmu_root", "clk_100m_src", CLK_IGNORE_UNUSED,
+ RK3528_PMU_CLKGATE_CON(0), 1, GFLAGS),
+ GATE(PCLK_PMU_ROOT, "pclk_pmu_root", "clk_100m_src", CLK_IGNORE_UNUSED,
+ RK3528_PMU_CLKGATE_CON(0), 0, GFLAGS),
+
+ GATE(FCLK_MCU, "fclk_mcu", "hclk_pmu_root", 0,
+ RK3528_PMU_CLKGATE_CON(0), 7, GFLAGS),
+ GATE(HCLK_PMU_SRAM, "hclk_pmu_sram", "hclk_pmu_root", CLK_IS_CRITICAL,
+ RK3528_PMU_CLKGATE_CON(5), 4, GFLAGS),
+
+ GATE(PCLK_I2C2, "pclk_i2c2", "pclk_pmu_root", 0,
+ RK3528_PMU_CLKGATE_CON(0), 2, GFLAGS),
+ GATE(PCLK_PMU_HP_TIMER, "pclk_pmu_hp_timer", "pclk_pmu_root", 0,
+ RK3528_PMU_CLKGATE_CON(1), 2, GFLAGS),
+ GATE(PCLK_PMU_IOC, "pclk_pmu_ioc", "pclk_pmu_root", CLK_IS_CRITICAL,
+ RK3528_PMU_CLKGATE_CON(1), 5, GFLAGS),
+ GATE(PCLK_PMU_CRU, "pclk_pmu_cru", "pclk_pmu_root", CLK_IS_CRITICAL,
+ RK3528_PMU_CLKGATE_CON(1), 6, GFLAGS),
+ GATE(PCLK_PMU_GRF, "pclk_pmu_grf", "pclk_pmu_root", CLK_IS_CRITICAL,
+ RK3528_PMU_CLKGATE_CON(1), 7, GFLAGS),
+ GATE(PCLK_PMU_WDT, "pclk_pmu_wdt", "pclk_pmu_root", 0,
+ RK3528_PMU_CLKGATE_CON(1), 10, GFLAGS),
+ GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_root", CLK_IS_CRITICAL,
+ RK3528_PMU_CLKGATE_CON(0), 13, GFLAGS),
+ GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu_root", 0,
+ RK3528_PMU_CLKGATE_CON(0), 14, GFLAGS),
+ GATE(PCLK_OSCCHK, "pclk_oscchk", "pclk_pmu_root", 0,
+ RK3528_PMU_CLKGATE_CON(0), 9, GFLAGS),
+ GATE(PCLK_PMU_MAILBOX, "pclk_pmu_mailbox", "pclk_pmu_root", 0,
+ RK3528_PMU_CLKGATE_CON(1), 12, GFLAGS),
+ GATE(PCLK_SCRKEYGEN, "pclk_scrkeygen", "pclk_pmu_root", 0,
+ RK3528_PMU_CLKGATE_CON(1), 15, GFLAGS),
+ GATE(PCLK_PVTM_PMU, "pclk_pvtm_pmu", "pclk_pmu_root", 0,
+ RK3528_PMU_CLKGATE_CON(5), 1, GFLAGS),
+
+ COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", clk_i2c2_p, 0,
+ RK3528_PMU_CLKSEL_CON(0), 0, 2, MFLAGS,
+ RK3528_PMU_CLKGATE_CON(0), 3, GFLAGS),
+
+ GATE(CLK_REFOUT, "clk_refout", "xin24m", 0,
+ RK3528_PMU_CLKGATE_CON(2), 4, GFLAGS),
+ COMPOSITE_NOMUX(CLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,
+ RK3528_PMU_CLKSEL_CON(5), 0, 5, DFLAGS,
+ RK3528_PMU_CLKGATE_CON(5), 0, GFLAGS),
+
+ COMPOSITE_FRAC(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", 0,
+ RK3528_PMU_CLKSEL_CON(1), 0,
+ RK3528_PMU_CLKGATE_CON(1), 0, GFLAGS),
+ /* clk_32k: internal! No path from external osc 32k */
+ MUX(CLK_DEEPSLOW, "clk_32k", clk_32k_p, CLK_IS_CRITICAL,
+ RK3528_PMU_CLKSEL_CON(2), 0, 1, MFLAGS),
+ GATE(RTC_CLK_MCU, "rtc_clk_mcu", "clk_32k", 0,
+ RK3528_PMU_CLKGATE_CON(0), 8, GFLAGS),
+ GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "xin24m", CLK_IGNORE_UNUSED,
+ RK3528_PMU_CLKGATE_CON(1), 1, GFLAGS),
+
+ COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_24m_32k_p, 0,
+ RK3528_PMU_CLKSEL_CON(0), 2, 1, MFLAGS,
+ RK3528_PMU_CLKGATE_CON(0), 15, GFLAGS),
+ COMPOSITE_NODIV(TCLK_PMU_WDT, "tclk_pmu_wdt", mux_24m_32k_p, 0,
+ RK3528_PMU_CLKSEL_CON(2), 1, 1, MFLAGS,
+ RK3528_PMU_CLKGATE_CON(1), 11, GFLAGS),
+
+ /* core */
+ COMPOSITE_NOMUX(ACLK_M_CORE_BIU, "aclk_m_core", "armclk", CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(39), 11, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
+ RK3528_CLKGATE_CON(5), 12, GFLAGS),
+ COMPOSITE_NOMUX(PCLK_DBG, "pclk_dbg", "armclk", CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(40), 1, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
+ RK3528_CLKGATE_CON(5), 13, GFLAGS),
+ GATE(PCLK_CPU_ROOT, "pclk_cpu_root", "pclk_dbg", CLK_IS_CRITICAL,
+ RK3528_CLKGATE_CON(6), 1, GFLAGS),
+ GATE(PCLK_CORE_GRF, "pclk_core_grf", "pclk_cpu_root", CLK_IS_CRITICAL,
+ RK3528_CLKGATE_CON(6), 2, GFLAGS),
+
+ /* ddr */
+ GATE(CLK_DDRC_SRC, "clk_ddrc_src", "dpll", CLK_IS_CRITICAL,
+ RK3528_DDRPHY_CLKGATE_CON(0), 0, GFLAGS),
+ GATE(CLK_DDR_PHY, "clk_ddr_phy", "dpll", CLK_IS_CRITICAL,
+ RK3528_DDRPHY_CLKGATE_CON(0), 1, GFLAGS),
+
+ COMPOSITE_NODIV(PCLK_DDR_ROOT, "pclk_ddr_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(90), 0, 2, MFLAGS,
+ RK3528_CLKGATE_CON(45), 0, GFLAGS),
+ GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_ddr_root", CLK_IGNORE_UNUSED,
+ RK3528_CLKGATE_CON(45), 3, GFLAGS),
+ GATE(PCLK_DDR_HWLP, "pclk_ddr_hwlp", "pclk_ddr_root", CLK_IGNORE_UNUSED,
+ RK3528_CLKGATE_CON(45), 8, GFLAGS),
+ GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", CLK_IGNORE_UNUSED,
+ RK3528_CLKGATE_CON(45), 4, GFLAGS),
+
+ GATE(PCLK_DDRC, "pclk_ddrc", "pclk_ddr_root", CLK_IS_CRITICAL,
+ RK3528_CLKGATE_CON(45), 2, GFLAGS),
+ GATE(PCLK_DDR_GRF, "pclk_ddr_grf", "pclk_ddr_root", CLK_IS_CRITICAL,
+ RK3528_CLKGATE_CON(45), 6, GFLAGS),
+ GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_ddr_root", CLK_IS_CRITICAL,
+ RK3528_CLKGATE_CON(45), 9, GFLAGS),
+
+ GATE(ACLK_DDR_UPCTL, "aclk_ddr_upctl", "clk_ddrc_src", CLK_IS_CRITICAL,
+ RK3528_CLKGATE_CON(45), 11, GFLAGS),
+ GATE(CLK_DDR_UPCTL, "clk_ddr_upctl", "clk_ddrc_src", CLK_IS_CRITICAL,
+ RK3528_CLKGATE_CON(45), 12, GFLAGS),
+ GATE(CLK_DDRMON, "clk_ddrmon", "clk_ddrc_src", CLK_IS_CRITICAL,
+ RK3528_CLKGATE_CON(45), 13, GFLAGS),
+ GATE(ACLK_DDR_SCRAMBLE, "aclk_ddr_scramble", "clk_ddrc_src", CLK_IS_CRITICAL,
+ RK3528_CLKGATE_CON(45), 14, GFLAGS),
+ GATE(ACLK_SPLIT, "aclk_split", "clk_ddrc_src", CLK_IS_CRITICAL,
+ RK3528_CLKGATE_CON(45), 15, GFLAGS),
+
+ /* gpu */
+ COMPOSITE_NODIV(ACLK_GPU_ROOT, "aclk_gpu_root", mux_500m_300m_100m_24m_p, CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(76), 0, 2, MFLAGS,
+ RK3528_CLKGATE_CON(34), 0, GFLAGS),
+ COMPOSITE_NODIV(ACLK_GPU, "aclk_gpu", aclk_gpu_p, CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(76), 6, 1, MFLAGS,
+ RK3528_CLKGATE_CON(34), 7, GFLAGS),
+ GATE(ACLK_GPU_MALI, "aclk_gpu_mali", "aclk_gpu", 0,
+ RK3528_CLKGATE_CON(34), 8, GFLAGS),
+ COMPOSITE_NODIV(PCLK_GPU_ROOT, "pclk_gpu_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(76), 4, 2, MFLAGS,
+ RK3528_CLKGATE_CON(34), 2, GFLAGS),
+
+ /* rkvdec */
+ COMPOSITE_NODIV(ACLK_RKVDEC_ROOT_NDFT, "aclk_rkvdec_root", mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(88), 6, 2, MFLAGS,
+ RK3528_CLKGATE_CON(44), 3, GFLAGS),
+ COMPOSITE_NODIV(HCLK_RKVDEC_ROOT, "hclk_rkvdec_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(88), 4, 2, MFLAGS,
+ RK3528_CLKGATE_CON(44), 2, GFLAGS),
+ GATE(PCLK_DDRPHY_CRU, "pclk_ddrphy_cru", "hclk_rkvdec_root", CLK_IS_CRITICAL,
+ RK3528_CLKGATE_CON(44), 4, GFLAGS),
+ GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_root", 0,
+ RK3528_CLKGATE_CON(44), 9, GFLAGS),
+ COMPOSITE_NODIV(CLK_HEVC_CA_RKVDEC, "clk_hevc_ca_rkvdec", mux_600m_300m_200m_24m_p, 0,
+ RK3528_CLKSEL_CON(88), 11, 2, MFLAGS,
+ RK3528_CLKGATE_CON(44), 11, GFLAGS),
+ MUX(ACLK_RKVDEC_PVTMUX_ROOT, "aclk_rkvdec_pvtmux_root", aclk_rkvdec_pvtmux_root_p, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(88), 13, 1, MFLAGS),
+ GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pvtmux_root", 0,
+ RK3528_CLKGATE_CON(44), 8, GFLAGS),
+
+ /* rkvenc */
+ COMPOSITE_NODIV(ACLK_RKVENC_ROOT, "aclk_rkvenc_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(79), 2, 2, MFLAGS,
+ RK3528_CLKGATE_CON(36), 1, GFLAGS),
+ GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_root", 0,
+ RK3528_CLKGATE_CON(36), 7, GFLAGS),
+
+ COMPOSITE_NODIV(PCLK_RKVENC_ROOT, "pclk_rkvenc_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(79), 4, 2, MFLAGS,
+ RK3528_CLKGATE_CON(36), 2, GFLAGS),
+ GATE(PCLK_RKVENC_IOC, "pclk_rkvenc_ioc", "pclk_rkvenc_root", CLK_IS_CRITICAL,
+ RK3528_CLKGATE_CON(37), 10, GFLAGS),
+ GATE(PCLK_RKVENC_GRF, "pclk_rkvenc_grf", "pclk_rkvenc_root", CLK_IS_CRITICAL,
+ RK3528_CLKGATE_CON(38), 6, GFLAGS),
+ GATE(PCLK_I2C1, "pclk_i2c1", "pclk_rkvenc_root", 0,
+ RK3528_CLKGATE_CON(36), 11, GFLAGS),
+ GATE(PCLK_I2C0, "pclk_i2c0", "pclk_rkvenc_root", 0,
+ RK3528_CLKGATE_CON(36), 13, GFLAGS),
+ GATE(PCLK_SPI0, "pclk_spi0", "pclk_rkvenc_root", 0,
+ RK3528_CLKGATE_CON(37), 2, GFLAGS),
+ GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_rkvenc_root", 0,
+ RK3528_CLKGATE_CON(37), 8, GFLAGS),
+ GATE(PCLK_UART1, "pclk_uart1", "pclk_rkvenc_root", 0,
+ RK3528_CLKGATE_CON(38), 2, GFLAGS),
+ GATE(PCLK_UART3, "pclk_uart3", "pclk_rkvenc_root", 0,
+ RK3528_CLKGATE_CON(38), 4, GFLAGS),
+ GATE(PCLK_CAN0, "pclk_can0", "pclk_rkvenc_root", 0,
+ RK3528_CLKGATE_CON(38), 7, GFLAGS),
+ GATE(PCLK_CAN1, "pclk_can1", "pclk_rkvenc_root", 0,
+ RK3528_CLKGATE_CON(38), 9, GFLAGS),
+
+ COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mux_150m_100m_24m_p, 0,
+ RK3528_CLKSEL_CON(80), 12, 2, MFLAGS,
+ RK3528_CLKGATE_CON(38), 1, GFLAGS),
+ COMPOSITE(CLK_CAN0, "clk_can0", mux_gpll_cpll_p, 0,
+ RK3528_CLKSEL_CON(81), 6, 1, MFLAGS, 0, 6, DFLAGS,
+ RK3528_CLKGATE_CON(38), 8, GFLAGS),
+ COMPOSITE(CLK_CAN1, "clk_can1", mux_gpll_cpll_p, 0,
+ RK3528_CLKSEL_CON(81), 13, 1, MFLAGS, 7, 6, DFLAGS,
+ RK3528_CLKGATE_CON(38), 10, GFLAGS),
+
+ COMPOSITE_NODIV(HCLK_RKVENC_ROOT, "hclk_rkvenc_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(79), 0, 2, MFLAGS,
+ RK3528_CLKGATE_CON(36), 0, GFLAGS),
+ GATE(HCLK_SAI_I2S1, "hclk_sai_i2s1", "hclk_rkvenc_root", 0,
+ RK3528_CLKGATE_CON(36), 9, GFLAGS),
+ GATE(HCLK_SPDIF, "hclk_spdif", "hclk_rkvenc_root", 0,
+ RK3528_CLKGATE_CON(37), 14, GFLAGS),
+ GATE(HCLK_PDM, "hclk_pdm", "hclk_rkvenc_root", 0,
+ RK3528_CLKGATE_CON(38), 0, GFLAGS),
+ GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_root", 0,
+ RK3528_CLKGATE_CON(36), 6, GFLAGS),
+
+ COMPOSITE_NODIV(CLK_CORE_RKVENC, "clk_core_rkvenc", mux_300m_200m_100m_24m_p, 0,
+ RK3528_CLKSEL_CON(79), 6, 2, MFLAGS,
+ RK3528_CLKGATE_CON(36), 8, GFLAGS),
+ COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", mux_200m_100m_50m_24m_p, 0,
+ RK3528_CLKSEL_CON(79), 11, 2, MFLAGS,
+ RK3528_CLKGATE_CON(36), 14, GFLAGS),
+ COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_50m_24m_p, 0,
+ RK3528_CLKSEL_CON(79), 9, 2, MFLAGS,
+ RK3528_CLKGATE_CON(36), 12, GFLAGS),
+
+ COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0,
+ RK3528_CLKSEL_CON(79), 13, 2, MFLAGS,
+ RK3528_CLKGATE_CON(37), 3, GFLAGS),
+ COMPOSITE_NODIV(MCLK_SAI_I2S1, "mclk_sai_i2s1", mclk_sai_i2s1_p, CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(79), 8, 1, MFLAGS,
+ RK3528_CLKGATE_CON(36), 10, GFLAGS),
+ GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0,
+ RK3528_CLKGATE_CON(37), 9, GFLAGS),
+
+ /* vo */
+ COMPOSITE_NODIV(HCLK_VO_ROOT, "hclk_vo_root", mux_150m_100m_24m_p, CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(83), 2, 2, MFLAGS,
+ RK3528_CLKGATE_CON(39), 1, GFLAGS),
+ GATE(HCLK_VOP, "hclk_vop", "hclk_vo_root", 0,
+ RK3528_CLKGATE_CON(40), 2, GFLAGS),
+ GATE(HCLK_USBHOST, "hclk_usbhost", "hclk_vo_root", 0,
+ RK3528_CLKGATE_CON(43), 3, GFLAGS),
+ GATE(HCLK_JPEG_DECODER, "hclk_jpeg_decoder", "hclk_vo_root", 0,
+ RK3528_CLKGATE_CON(41), 7, GFLAGS),
+ GATE(HCLK_VDPP, "hclk_vdpp", "hclk_vo_root", 0,
+ RK3528_CLKGATE_CON(39), 10, GFLAGS),
+ GATE(HCLK_CVBS, "hclk_cvbs", "hclk_vo_root", 0,
+ RK3528_CLKGATE_CON(41), 3, GFLAGS),
+ GATE(HCLK_USBHOST_ARB, "hclk_usbhost_arb", "hclk_vo_root", 0,
+ RK3528_CLKGATE_CON(43), 4, GFLAGS),
+ GATE(HCLK_SAI_I2S3, "hclk_sai_i2s3", "hclk_vo_root", 0,
+ RK3528_CLKGATE_CON(42), 1, GFLAGS),
+ GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo_root", 0,
+ RK3528_CLKGATE_CON(41), 1, GFLAGS),
+ GATE(HCLK_RGA2E, "hclk_rga2e", "hclk_vo_root", 0,
+ RK3528_CLKGATE_CON(39), 7, GFLAGS),
+ GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_vo_root", 0,
+ RK3528_CLKGATE_CON(42), 9, GFLAGS),
+ GATE(HCLK_HDCP_KEY, "hclk_hdcp_key", "hclk_vo_root", 0,
+ RK3528_CLKGATE_CON(40), 15, GFLAGS),
+
+ COMPOSITE_NODIV(ACLK_VO_L_ROOT, "aclk_vo_l_root", mux_150m_100m_24m_p, CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(84), 1, 2, MFLAGS,
+ RK3528_CLKGATE_CON(41), 8, GFLAGS),
+ GATE(ACLK_MAC_VO, "aclk_gmac0", "aclk_vo_l_root", 0,
+ RK3528_CLKGATE_CON(41), 10, GFLAGS),
+
+ COMPOSITE_NODIV(PCLK_VO_ROOT, "pclk_vo_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(83), 4, 2, MFLAGS,
+ RK3528_CLKGATE_CON(39), 2, GFLAGS),
+ GATE(PCLK_MAC_VO, "pclk_gmac0", "pclk_vo_root", 0,
+ RK3528_CLKGATE_CON(41), 11, GFLAGS),
+ GATE(PCLK_VCDCPHY, "pclk_vcdcphy", "pclk_vo_root", 0,
+ RK3528_CLKGATE_CON(42), 4, GFLAGS),
+ GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_vo_root", 0,
+ RK3528_CLKGATE_CON(42), 5, GFLAGS),
+ GATE(PCLK_VO_IOC, "pclk_vo_ioc", "pclk_vo_root", CLK_IS_CRITICAL,
+ RK3528_CLKGATE_CON(42), 7, GFLAGS),
+ GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_vo_root", 0,
+ RK3528_CLKGATE_CON(42), 11, GFLAGS),
+ GATE(PCLK_UART4, "pclk_uart4", "pclk_vo_root", 0,
+ RK3528_CLKGATE_CON(43), 7, GFLAGS),
+ GATE(PCLK_I2C4, "pclk_i2c4", "pclk_vo_root", 0,
+ RK3528_CLKGATE_CON(43), 9, GFLAGS),
+ GATE(PCLK_I2C7, "pclk_i2c7", "pclk_vo_root", 0,
+ RK3528_CLKGATE_CON(43), 11, GFLAGS),
+
+ GATE(PCLK_USBPHY, "pclk_usbphy", "pclk_vo_root", 0,
+ RK3528_CLKGATE_CON(43), 13, GFLAGS),
+
+ GATE(PCLK_VO_GRF, "pclk_vo_grf", "pclk_vo_root", CLK_IS_CRITICAL,
+ RK3528_CLKGATE_CON(39), 13, GFLAGS),
+ GATE(PCLK_CRU, "pclk_cru", "pclk_vo_root", CLK_IS_CRITICAL,
+ RK3528_CLKGATE_CON(39), 15, GFLAGS),
+ GATE(PCLK_HDMI, "pclk_hdmi", "pclk_vo_root", 0,
+ RK3528_CLKGATE_CON(40), 6, GFLAGS),
+ GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_vo_root", 0,
+ RK3528_CLKGATE_CON(40), 14, GFLAGS),
+ GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo_root", 0,
+ RK3528_CLKGATE_CON(41), 2, GFLAGS),
+
+ COMPOSITE_NODIV(CLK_CORE_VDPP, "clk_core_vdpp", mux_339m_200m_100m_24m_p, 0,
+ RK3528_CLKSEL_CON(83), 10, 2, MFLAGS,
+ RK3528_CLKGATE_CON(39), 12, GFLAGS),
+ COMPOSITE_NODIV(CLK_CORE_RGA2E, "clk_core_rga2e", mux_339m_200m_100m_24m_p, 0,
+ RK3528_CLKSEL_CON(83), 8, 2, MFLAGS,
+ RK3528_CLKGATE_CON(39), 9, GFLAGS),
+ COMPOSITE_NODIV(ACLK_JPEG_ROOT, "aclk_jpeg_root", mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(84), 9, 2, MFLAGS,
+ RK3528_CLKGATE_CON(41), 15, GFLAGS),
+ GATE(ACLK_JPEG_DECODER, "aclk_jpeg_decoder", "aclk_jpeg_root", 0,
+ RK3528_CLKGATE_CON(41), 6, GFLAGS),
+
+ COMPOSITE_NODIV(ACLK_VO_ROOT, "aclk_vo_root", mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(83), 0, 2, MFLAGS,
+ RK3528_CLKGATE_CON(39), 0, GFLAGS),
+ GATE(ACLK_RGA2E, "aclk_rga2e", "aclk_vo_root", 0,
+ RK3528_CLKGATE_CON(39), 8, GFLAGS),
+ GATE(ACLK_VDPP, "aclk_vdpp", "aclk_vo_root", 0,
+ RK3528_CLKGATE_CON(39), 11, GFLAGS),
+ GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo_root", 0,
+ RK3528_CLKGATE_CON(41), 0, GFLAGS),
+
+ COMPOSITE(CCLK_SRC_SDMMC0, "cclk_src_sdmmc0", mux_gpll_cpll_xin24m_p, 0,
+ RK3528_CLKSEL_CON(85), 6, 2, MFLAGS, 0, 6, DFLAGS,
+ RK3528_CLKGATE_CON(42), 8, GFLAGS),
+
+ COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", mux_gpll_cpll_p, CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(83), 15, 1, MFLAGS, 12, 3, DFLAGS,
+ RK3528_CLKGATE_CON(40), 0, GFLAGS),
+ GATE(ACLK_VOP, "aclk_vop", "aclk_vop_root", 0,
+ RK3528_CLKGATE_CON(40), 5, GFLAGS),
+
+ COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_50m_24m_p, 0,
+ RK3528_CLKSEL_CON(85), 13, 2, MFLAGS,
+ RK3528_CLKGATE_CON(43), 10, GFLAGS),
+ COMPOSITE_NODIV(CLK_I2C7, "clk_i2c7", mux_200m_100m_50m_24m_p, 0,
+ RK3528_CLKSEL_CON(86), 0, 2, MFLAGS,
+ RK3528_CLKGATE_CON(43), 12, GFLAGS),
+ GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0,
+ RK3528_CLKGATE_CON(42), 6, GFLAGS),
+
+ GATE(CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 0,
+ RK3528_CLKGATE_CON(43), 2, GFLAGS),
+ GATE(CLK_MACPHY, "clk_macphy", "xin24m", 0,
+ RK3528_CLKGATE_CON(42), 3, GFLAGS),
+ GATE(CLK_REF_USBPHY, "clk_ref_usbphy", "xin24m", 0,
+ RK3528_CLKGATE_CON(43), 14, GFLAGS),
+ GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0,
+ RK3528_CLKGATE_CON(42), 12, GFLAGS),
+ FACTOR(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "clk_sbpi_otpc_ns",
+ 0, 1, 2),
+
+ GATE(MCLK_SAI_I2S3, "mclk_sai_i2s3", "mclk_i2s3_8ch_sai_src", 0,
+ RK3528_CLKGATE_CON(42), 2, GFLAGS),
+ COMPOSITE_NODIV(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+ RK3528_CLKSEL_CON(84), 0, 1, MFLAGS,
+ RK3528_CLKGATE_CON(40), 3, GFLAGS),
+ GATE(DCLK_VOP1, "dclk_vop1", "dclk_vop_src1", CLK_SET_RATE_PARENT,
+ RK3528_CLKGATE_CON(40), 4, GFLAGS),
+ FACTOR_GATE(DCLK_CVBS, "dclk_cvbs", "dclk_vop1", 0, 1, 4,
+ RK3528_CLKGATE_CON(41), 4, GFLAGS),
+ GATE(DCLK_4X_CVBS, "dclk_4x_cvbs", "dclk_vop1", 0,
+ RK3528_CLKGATE_CON(41), 5, GFLAGS),
+
+ FACTOR_GATE(CLK_SFR_HDMI, "clk_sfr_hdmi", "dclk_vop_src1", 0, 1, 4,
+ RK3528_CLKGATE_CON(40), 7, GFLAGS),
+
+ GATE(CLK_SPDIF_HDMI, "clk_spdif_hdmi", "mclk_spdif_src", 0,
+ RK3528_CLKGATE_CON(40), 10, GFLAGS),
+ GATE(MCLK_SPDIF, "mclk_spdif", "mclk_spdif_src", 0,
+ RK3528_CLKGATE_CON(37), 15, GFLAGS),
+ GATE(CLK_CEC_HDMI, "clk_cec_hdmi", "clk_32k", 0,
+ RK3528_CLKGATE_CON(40), 8, GFLAGS),
+
+ /* vpu */
+ GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0,
+ RK3528_CLKGATE_CON(26), 5, GFLAGS),
+ GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0,
+ RK3528_CLKGATE_CON(27), 1, GFLAGS),
+ GATE(CLK_SUSPEND_USB3OTG, "clk_suspend_usb3otg", "xin24m", 0,
+ RK3528_CLKGATE_CON(33), 4, GFLAGS),
+ GATE(CLK_PCIE_AUX, "clk_pcie_aux", "xin24m", 0,
+ RK3528_CLKGATE_CON(30), 2, GFLAGS),
+ GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0,
+ RK3528_CLKGATE_CON(26), 3, GFLAGS),
+ GATE(CLK_REF_USB3OTG, "clk_ref_usb3otg", "xin24m", 0,
+ RK3528_CLKGATE_CON(33), 2, GFLAGS),
+ COMPOSITE(CCLK_SRC_SDIO0, "cclk_src_sdio0", mux_gpll_cpll_xin24m_p, 0,
+ RK3528_CLKSEL_CON(72), 6, 2, MFLAGS, 0, 6, DFLAGS,
+ RK3528_CLKGATE_CON(32), 1, GFLAGS),
+
+ COMPOSITE_NODIV(PCLK_VPU_ROOT, "pclk_vpu_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(61), 4, 2, MFLAGS,
+ RK3528_CLKGATE_CON(25), 5, GFLAGS),
+ GATE(PCLK_VPU_GRF, "pclk_vpu_grf", "pclk_vpu_root", CLK_IS_CRITICAL,
+ RK3528_CLKGATE_CON(25), 12, GFLAGS),
+ GATE(PCLK_CRU_PCIE, "pclk_cru_pcie", "pclk_vpu_root", CLK_IS_CRITICAL,
+ RK3528_CLKGATE_CON(25), 11, GFLAGS),
+ GATE(PCLK_UART6, "pclk_uart6", "pclk_vpu_root", 0,
+ RK3528_CLKGATE_CON(27), 11, GFLAGS),
+ GATE(PCLK_CAN2, "pclk_can2", "pclk_vpu_root", 0,
+ RK3528_CLKGATE_CON(32), 7, GFLAGS),
+ GATE(PCLK_SPI1, "pclk_spi1", "pclk_vpu_root", 0,
+ RK3528_CLKGATE_CON(27), 4, GFLAGS),
+ GATE(PCLK_CAN3, "pclk_can3", "pclk_vpu_root", 0,
+ RK3528_CLKGATE_CON(32), 9, GFLAGS),
+ GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_vpu_root", 0,
+ RK3528_CLKGATE_CON(27), 0, GFLAGS),
+ GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_vpu_root", 0,
+ RK3528_CLKGATE_CON(26), 4, GFLAGS),
+ GATE(PCLK_SARADC, "pclk_saradc", "pclk_vpu_root", 0,
+ RK3528_CLKGATE_CON(32), 11, GFLAGS),
+ GATE(PCLK_ACODEC, "pclk_acodec", "pclk_vpu_root", 0,
+ RK3528_CLKGATE_CON(26), 13, GFLAGS),
+ GATE(PCLK_UART7, "pclk_uart7", "pclk_vpu_root", 0,
+ RK3528_CLKGATE_CON(27), 13, GFLAGS),
+ GATE(PCLK_UART5, "pclk_uart5", "pclk_vpu_root", 0,
+ RK3528_CLKGATE_CON(27), 9, GFLAGS),
+ GATE(PCLK_TSADC, "pclk_tsadc", "pclk_vpu_root", 0,
+ RK3528_CLKGATE_CON(32), 14, GFLAGS),
+ GATE(PCLK_PCIE, "pclk_pcie", "pclk_vpu_root", 0,
+ RK3528_CLKGATE_CON(30), 1, GFLAGS),
+ GATE(PCLK_UART2, "pclk_uart2", "pclk_vpu_root", 0,
+ RK3528_CLKGATE_CON(27), 7, GFLAGS),
+ GATE(PCLK_VPU_IOC, "pclk_vpu_ioc", "pclk_vpu_root", CLK_IS_CRITICAL,
+ RK3528_CLKGATE_CON(26), 8, GFLAGS),
+ GATE(PCLK_PIPE_GRF, "pclk_pipe_grf", "pclk_vpu_root", CLK_IS_CRITICAL,
+ RK3528_CLKGATE_CON(30), 7, GFLAGS),
+ GATE(PCLK_I2C5, "pclk_i2c5", "pclk_vpu_root", 0,
+ RK3528_CLKGATE_CON(28), 1, GFLAGS),
+ GATE(PCLK_PCIE_PHY, "pclk_pcie_phy", "pclk_vpu_root", 0,
+ RK3528_CLKGATE_CON(30), 6, GFLAGS),
+ GATE(PCLK_I2C3, "pclk_i2c3", "pclk_vpu_root", 0,
+ RK3528_CLKGATE_CON(27), 15, GFLAGS),
+ GATE(PCLK_MAC_VPU, "pclk_gmac1", "pclk_vpu_root", CLK_IS_CRITICAL,
+ RK3528_CLKGATE_CON(28), 6, GFLAGS),
+ GATE(PCLK_I2C6, "pclk_i2c6", "pclk_vpu_root", 0,
+ RK3528_CLKGATE_CON(28), 3, GFLAGS),
+
+ COMPOSITE_NODIV(ACLK_VPU_L_ROOT, "aclk_vpu_l_root", mux_200m_100m_24m_p, CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(60), 0, 2, MFLAGS,
+ RK3528_CLKGATE_CON(25), 0, GFLAGS),
+ GATE(ACLK_EMMC, "aclk_emmc", "aclk_vpu_l_root", 0,
+ RK3528_CLKGATE_CON(26), 1, GFLAGS),
+ GATE(ACLK_MAC_VPU, "aclk_gmac1", "aclk_vpu_l_root", 0,
+ RK3528_CLKGATE_CON(28), 5, GFLAGS),
+ GATE(ACLK_PCIE, "aclk_pcie", "aclk_vpu_l_root", 0,
+ RK3528_CLKGATE_CON(30), 3, GFLAGS),
+
+ GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_vpu_l_root", 0,
+ RK3528_CLKGATE_CON(33), 1, GFLAGS),
+
+ COMPOSITE_NODIV(HCLK_VPU_ROOT, "hclk_vpu_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(61), 2, 2, MFLAGS,
+ RK3528_CLKGATE_CON(25), 4, GFLAGS),
+ GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_root", 0,
+ RK3528_CLKGATE_CON(25), 10, GFLAGS),
+ GATE(HCLK_SFC, "hclk_sfc", "hclk_vpu_root", 0,
+ RK3528_CLKGATE_CON(25), 13, GFLAGS),
+ GATE(HCLK_EMMC, "hclk_emmc", "hclk_vpu_root", 0,
+ RK3528_CLKGATE_CON(26), 0, GFLAGS),
+ GATE(HCLK_SAI_I2S0, "hclk_sai_i2s0", "hclk_vpu_root", 0,
+ RK3528_CLKGATE_CON(26), 9, GFLAGS),
+ GATE(HCLK_SAI_I2S2, "hclk_sai_i2s2", "hclk_vpu_root", 0,
+ RK3528_CLKGATE_CON(26), 11, GFLAGS),
+
+ GATE(HCLK_PCIE_SLV, "hclk_pcie_slv", "hclk_vpu_root", 0,
+ RK3528_CLKGATE_CON(30), 4, GFLAGS),
+ GATE(HCLK_PCIE_DBI, "hclk_pcie_dbi", "hclk_vpu_root", 0,
+ RK3528_CLKGATE_CON(30), 5, GFLAGS),
+ GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_vpu_root", 0,
+ RK3528_CLKGATE_CON(32), 2, GFLAGS),
+ GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_vpu_root", 0,
+ RK3528_CLKGATE_CON(32), 4, GFLAGS),
+
+ COMPOSITE_NOMUX(CLK_GMAC1_VPU_25M, "clk_gmac1_25m", "ppll", 0,
+ RK3528_CLKSEL_CON(60), 2, 8, DFLAGS,
+ RK3528_CLKGATE_CON(25), 1, GFLAGS),
+ COMPOSITE_NOMUX(CLK_PPLL_125M_MATRIX, "clk_ppll_125m_src", "ppll", 0,
+ RK3528_CLKSEL_CON(60), 10, 5, DFLAGS,
+ RK3528_CLKGATE_CON(25), 2, GFLAGS),
+
+ COMPOSITE(CLK_CAN3, "clk_can3", mux_gpll_cpll_p, 0,
+ RK3528_CLKSEL_CON(73), 13, 1, MFLAGS, 7, 6, DFLAGS,
+ RK3528_CLKGATE_CON(32), 10, GFLAGS),
+ COMPOSITE_NODIV(CLK_I2C6, "clk_i2c6", mux_200m_100m_50m_24m_p, 0,
+ RK3528_CLKSEL_CON(64), 0, 2, MFLAGS,
+ RK3528_CLKGATE_CON(28), 4, GFLAGS),
+
+ COMPOSITE(SCLK_SFC, "sclk_sfc", mux_gpll_cpll_xin24m_p, 0,
+ RK3528_CLKSEL_CON(61), 12, 2, MFLAGS, 6, 6, DFLAGS,
+ RK3528_CLKGATE_CON(25), 14, GFLAGS),
+ COMPOSITE(CCLK_SRC_EMMC, "cclk_src_emmc", mux_gpll_cpll_xin24m_p, 0,
+ RK3528_CLKSEL_CON(62), 6, 2, MFLAGS, 0, 6, DFLAGS,
+ RK3528_CLKGATE_CON(25), 15, GFLAGS),
+
+ COMPOSITE_NODIV(ACLK_VPU_ROOT, "aclk_vpu_root",
+ mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL,
+ RK3528_CLKSEL_CON(61), 0, 2, MFLAGS,
+ RK3528_CLKGATE_CON(25), 3, GFLAGS),
+ GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_root", 0,
+ RK3528_CLKGATE_CON(25), 9, GFLAGS),
+
+ COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0,
+ RK3528_CLKSEL_CON(63), 10, 2, MFLAGS,
+ RK3528_CLKGATE_CON(27), 5, GFLAGS),
+ COMPOSITE(CCLK_SRC_SDIO1, "cclk_src_sdio1", mux_gpll_cpll_xin24m_p, 0,
+ RK3528_CLKSEL_CON(72), 14, 2, MFLAGS, 8, 6, DFLAGS,
+ RK3528_CLKGATE_CON(32), 3, GFLAGS),
+ COMPOSITE(CLK_CAN2, "clk_can2", mux_gpll_cpll_p, 0,
+ RK3528_CLKSEL_CON(73), 6, 1, MFLAGS, 0, 6, DFLAGS,
+ RK3528_CLKGATE_CON(32), 8, GFLAGS),
+ COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0,
+ RK3528_CLKSEL_CON(74), 3, 5, DFLAGS,
+ RK3528_CLKGATE_CON(32), 15, GFLAGS),
+ COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
+ RK3528_CLKSEL_CON(74), 0, 3, DFLAGS,
+ RK3528_CLKGATE_CON(32), 12, GFLAGS),
+ COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m", 0,
+ RK3528_CLKSEL_CON(74), 8, 5, DFLAGS,
+ RK3528_CLKGATE_CON(33), 0, GFLAGS),
+ COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", mux_200m_100m_50m_24m_p, 0,
+ RK3528_CLKSEL_CON(62), 8, 2, MFLAGS,
+ RK3528_CLKGATE_CON(26), 2, GFLAGS),
+ COMPOSITE_NOMUX(MCLK_ACODEC_TX, "mclk_acodec_tx", "mclk_i2s2_2ch_sai_src", 0,
+ RK3528_CLKSEL_CON(63), 0, 8, DFLAGS,
+ RK3528_CLKGATE_CON(26), 14, GFLAGS),
+ COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_50m_24m_p, 0,
+ RK3528_CLKSEL_CON(63), 12, 2, MFLAGS,
+ RK3528_CLKGATE_CON(28), 0, GFLAGS),
+ COMPOSITE_NODIV(CLK_I2C5, "clk_i2c5", mux_200m_100m_50m_24m_p, 0,
+ RK3528_CLKSEL_CON(63), 14, 2, MFLAGS,
+ RK3528_CLKGATE_CON(28), 2, GFLAGS),
+ COMPOSITE_NODIV(MCLK_SAI_I2S0, "mclk_sai_i2s0", mclk_sai_i2s0_p, CLK_SET_RATE_PARENT,
+ RK3528_CLKSEL_CON(62), 10, 1, MFLAGS,
+ RK3528_CLKGATE_CON(26), 10, GFLAGS),
+ GATE(MCLK_SAI_I2S2, "mclk_sai_i2s2", "mclk_i2s2_2ch_sai_src", 0,
+ RK3528_CLKGATE_CON(26), 12, GFLAGS),
+
+ /* pcie */
+ COMPOSITE_NOMUX(CLK_PPLL_100M_MATRIX, "clk_ppll_100m_src", "ppll", CLK_IS_CRITICAL,
+ RK3528_PCIE_CLKSEL_CON(1), 2, 5, DFLAGS,
+ RK3528_PCIE_CLKGATE_CON(0), 1, GFLAGS),
+ COMPOSITE_NOMUX(CLK_PPLL_50M_MATRIX, "clk_ppll_50m_src", "ppll", CLK_IS_CRITICAL,
+ RK3528_PCIE_CLKSEL_CON(1), 7, 5, DFLAGS,
+ RK3528_PCIE_CLKGATE_CON(0), 2, GFLAGS),
+ MUX(CLK_REF_PCIE_INNER_PHY, "clk_ref_pcie_inner_phy", clk_ref_pcie_inner_phy_p, 0,
+ RK3528_PCIE_CLKSEL_CON(1), 13, 1, MFLAGS),
+ FACTOR(CLK_REF_PCIE_100M_PHY, "clk_ref_pcie_100m_phy", "clk_ppll_100m_src",
+ 0, 1, 1),
+
+ /* gmac */
+ DIV(CLK_GMAC0_SRC, "clk_gmac0_src", "gmac0", 0,
+ RK3528_CLKSEL_CON(84), 3, 6, DFLAGS),
+ GATE(CLK_GMAC0_TX, "clk_gmac0_tx", "clk_gmac0_src", 0,
+ RK3528_CLKGATE_CON(41), 13, GFLAGS),
+ GATE(CLK_GMAC0_RX, "clk_gmac0_rx", "clk_gmac0_src", 0,
+ RK3528_CLKGATE_CON(41), 14, GFLAGS),
+ GATE(CLK_GMAC0_RMII_50M, "clk_gmac0_rmii_50m", "gmac0", 0,
+ RK3528_CLKGATE_CON(41), 12, GFLAGS),
+
+ FACTOR(CLK_GMAC1_RMII_VPU, "clk_gmac1_50m", "clk_ppll_50m_src",
+ 0, 1, 1),
+ FACTOR(CLK_GMAC1_SRC_VPU, "clk_gmac1_125m", "clk_ppll_125m_src",
+ 0, 1, 1),
+};
+
+static int __init clk_rk3528_probe(struct platform_device *pdev)
+{
+ struct rockchip_clk_provider *ctx;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ unsigned long nr_branches = ARRAY_SIZE(rk3528_clk_branches);
+ unsigned long nr_clks;
+ void __iomem *reg_base;
+
+ nr_clks = rockchip_clk_find_max_clk_id(rk3528_clk_branches,
+ nr_branches) + 1;
+
+ reg_base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(reg_base))
+ return dev_err_probe(dev, PTR_ERR(reg_base),
+ "could not map cru region");
+
+ ctx = rockchip_clk_init(np, reg_base, nr_clks);
+ if (IS_ERR(ctx))
+ return dev_err_probe(dev, PTR_ERR(ctx),
+ "rockchip clk init failed");
+
+ rockchip_clk_register_plls(ctx, rk3528_pll_clks,
+ ARRAY_SIZE(rk3528_pll_clks),
+ RK3528_GRF_SOC_STATUS0);
+ rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
+ mux_armclk, ARRAY_SIZE(mux_armclk),
+ &rk3528_cpuclk_data, rk3528_cpuclk_rates,
+ ARRAY_SIZE(rk3528_cpuclk_rates));
+ rockchip_clk_register_branches(ctx, rk3528_clk_branches, nr_branches);
+
+ rk3528_rst_init(np, reg_base);
+
+ rockchip_register_restart_notifier(ctx, RK3528_GLB_SRST_FST, NULL);
+
+ rockchip_clk_of_add_provider(np, ctx);
+
+ return 0;
+}
+
+static const struct of_device_id clk_rk3528_match_table[] = {
+ { .compatible = "rockchip,rk3528-cru" },
+ { /* end */ }
+};
+
+static struct platform_driver clk_rk3528_driver = {
+ .driver = {
+ .name = "clk-rk3528",
+ .of_match_table = clk_rk3528_match_table,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver_probe(clk_rk3528_driver, clk_rk3528_probe);
diff --git a/drivers/clk/rockchip/clk-rk3562.c b/drivers/clk/rockchip/clk-rk3562.c
new file mode 100644
index 000000000000..b8858e5d5530
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rk3562.c
@@ -0,0 +1,1101 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ * Author: Finley Xiao <finley.xiao@rock-chips.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/syscore_ops.h>
+#include <dt-bindings/clock/rockchip,rk3562-cru.h>
+#include "clk.h"
+
+#define RK3562_GRF_SOC_STATUS0 0x430
+#define ROCKCHIP_PLL_ALLOW_POWER_DOWN BIT(2)
+
+enum rk3562_plls {
+ apll, gpll, vpll, hpll, cpll, dpll,
+};
+
+static struct rockchip_pll_rate_table rk3562_pll_rates[] = {
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+ RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0),
+ RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0),
+ RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0),
+ RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0),
+ RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0),
+ RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0),
+ RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
+ RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
+ RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
+ RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
+ RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
+ RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
+ RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
+ RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
+ RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
+ RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
+ RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
+ RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
+ RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0),
+ RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0),
+ RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
+ RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
+ RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
+ { /* sentinel */ },
+};
+
+PNAME(mux_pll_p) = { "xin24m" };
+PNAME(gpll_cpll_p) = { "gpll", "cpll" };
+PNAME(gpll_cpll_hpll_p) = { "gpll", "cpll", "hpll" };
+PNAME(gpll_cpll_pvtpll_dmyapll_p) = { "gpll", "cpll", "log_pvtpll", "dummy_apll" };
+PNAME(gpll_cpll_hpll_xin24m_p) = { "gpll", "cpll", "hpll", "xin24m" };
+PNAME(gpll_cpll_vpll_dmyhpll_p) = { "gpll", "cpll", "vpll", "dummy_hpll" };
+PNAME(gpll_dmyhpll_vpll_apll_p) = { "gpll", "dummy_hpll", "vpll", "apll" };
+PNAME(gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
+PNAME(gpll_cpll_xin24m_dmyapll_p) = { "gpll", "cpll", "xin24m", "dummy_apll" };
+PNAME(gpll_cpll_xin24m_dmyhpll_p) = { "gpll", "cpll", "xin24m", "dummy_hpll" };
+PNAME(vpll_dmyhpll_gpll_cpll_p) = { "vpll", "dummy_hpll", "gpll", "cpll" };
+PNAME(mux_xin24m_32k_p) = { "xin24m", "clk_rtc_32k" };
+PNAME(mux_50m_xin24m_p) = { "clk_matrix_50m_src", "xin24m" };
+PNAME(mux_100m_50m_xin24m_p) = { "clk_matrix_100m_src", "clk_matrix_50m_src", "xin24m" };
+PNAME(mux_125m_xin24m_p) = { "clk_matrix_125m_src", "xin24m" };
+PNAME(mux_200m_xin24m_32k_p) = { "clk_200m_pmu", "xin24m", "clk_rtc_32k" };
+PNAME(mux_200m_100m_p) = { "clk_matrix_200m_src", "clk_matrix_100m_src" };
+PNAME(mux_200m_100m_50m_xin24m_p) = { "clk_matrix_200m_src", "clk_matrix_100m_src", "clk_matrix_50m_src", "xin24m" };
+PNAME(clk_sai0_p) = { "clk_sai0_src", "clk_sai0_frac", "xin_osc0_half", "mclk_sai0_from_io" };
+PNAME(mclk_sai0_out2io_p) = { "mclk_sai0", "xin_osc0_half" };
+PNAME(clk_sai1_p) = { "clk_sai1_src", "clk_sai1_frac", "xin_osc0_half", "mclk_sai1_from_io" };
+PNAME(mclk_sai1_out2io_p) = { "mclk_sai1", "xin_osc0_half" };
+PNAME(clk_sai2_p) = { "clk_sai2_src", "clk_sai2_frac", "xin_osc0_half", "mclk_sai2_from_io" };
+PNAME(mclk_sai2_out2io_p) = { "mclk_sai2", "xin_osc0_half" };
+PNAME(clk_spdif_p) = { "clk_spdif_src", "clk_spdif_frac", "xin_osc0_half" };
+PNAME(clk_uart1_p) = { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
+PNAME(clk_uart2_p) = { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
+PNAME(clk_uart3_p) = { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
+PNAME(clk_uart4_p) = { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
+PNAME(clk_uart5_p) = { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
+PNAME(clk_uart6_p) = { "clk_uart6_src", "clk_uart6_frac", "xin24m" };
+PNAME(clk_uart7_p) = { "clk_uart7_src", "clk_uart7_frac", "xin24m" };
+PNAME(clk_uart8_p) = { "clk_uart8_src", "clk_uart8_frac", "xin24m" };
+PNAME(clk_uart9_p) = { "clk_uart9_src", "clk_uart9_frac", "xin24m" };
+PNAME(clk_rtc32k_pmu_p) = { "clk_rtc32k_frac", "xin32k", "clk_32k_pvtm" };
+PNAME(clk_pmu1_uart0_p) = { "clk_pmu1_uart0_src", "clk_pmu1_uart0_frac", "xin24m" };
+PNAME(clk_pipephy_ref_p) = { "clk_pipephy_div", "clk_pipephy_xin24m" };
+PNAME(clk_usbphy_ref_p) = { "clk_usb2phy_xin24m", "clk_24m_sscsrc" };
+PNAME(clk_mipidsi_ref_p) = { "clk_mipidsiphy_xin24m", "clk_24m_sscsrc" };
+
+static struct rockchip_pll_clock rk3562_pll_clks[] __initdata = {
+ [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
+ 0, RK3562_PLL_CON(0),
+ RK3562_MODE_CON, 0, 0,
+ ROCKCHIP_PLL_ALLOW_POWER_DOWN, rk3562_pll_rates),
+ [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
+ 0, RK3562_PLL_CON(24),
+ RK3562_MODE_CON, 2, 3, 0, rk3562_pll_rates),
+ [vpll] = PLL(pll_rk3328, PLL_VPLL, "vpll", mux_pll_p,
+ 0, RK3562_PLL_CON(32),
+ RK3562_MODE_CON, 6, 4,
+ ROCKCHIP_PLL_ALLOW_POWER_DOWN, rk3562_pll_rates),
+ [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p,
+ 0, RK3562_PLL_CON(40),
+ RK3562_MODE_CON, 8, 5,
+ ROCKCHIP_PLL_ALLOW_POWER_DOWN, rk3562_pll_rates),
+ [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
+ 0, RK3562_PMU1_PLL_CON(0),
+ RK3562_PMU1_MODE_CON, 0, 2, 0, rk3562_pll_rates),
+ [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
+ CLK_IS_CRITICAL, RK3562_SUBDDR_PLL_CON(0),
+ RK3562_SUBDDR_MODE_CON, 0, 1, 0, NULL),
+};
+
+#define MFLAGS CLK_MUX_HIWORD_MASK
+#define DFLAGS CLK_DIVIDER_HIWORD_MASK
+#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
+
+static struct rockchip_clk_branch rk3562_clk_sai0_fracmux __initdata =
+ MUX(CLK_SAI0, "clk_sai0", clk_sai0_p, CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(3), 6, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3562_clk_sai1_fracmux __initdata =
+ MUX(CLK_SAI1, "clk_sai1", clk_sai1_p, CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(5), 6, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3562_clk_sai2_fracmux __initdata =
+ MUX(CLK_SAI2, "clk_sai2", clk_sai2_p, CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(8), 6, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3562_clk_spdif_fracmux __initdata =
+ MUX(CLK_SPDIF, "clk_spdif", clk_spdif_p, CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(15), 6, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3562_clk_uart1_fracmux __initdata =
+ MUX(CLK_UART1, "clk_uart1", clk_uart1_p, CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(21), 14, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3562_clk_uart2_fracmux __initdata =
+ MUX(CLK_UART2, "clk_uart2", clk_uart2_p, CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(23), 14, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3562_clk_uart3_fracmux __initdata =
+ MUX(CLK_UART3, "clk_uart3", clk_uart3_p, CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(25), 14, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3562_clk_uart4_fracmux __initdata =
+ MUX(CLK_UART4, "clk_uart4", clk_uart4_p, CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(27), 14, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3562_clk_uart5_fracmux __initdata =
+ MUX(CLK_UART5, "clk_uart5", clk_uart5_p, CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(29), 14, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3562_clk_uart6_fracmux __initdata =
+ MUX(CLK_UART6, "clk_uart6", clk_uart6_p, CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(31), 14, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3562_clk_uart7_fracmux __initdata =
+ MUX(CLK_UART7, "clk_uart7", clk_uart7_p, CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(33), 14, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3562_clk_uart8_fracmux __initdata =
+ MUX(CLK_UART8, "clk_uart8", clk_uart8_p, CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(35), 14, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3562_clk_uart9_fracmux __initdata =
+ MUX(CLK_UART9, "clk_uart9", clk_uart9_p, CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(37), 14, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3562_rtc32k_pmu_fracmux __initdata =
+ MUX(CLK_RTC_32K, "clk_rtc_32k", clk_rtc32k_pmu_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+ RK3562_PMU0_CLKSEL_CON(1), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3562_clk_pmu1_uart0_fracmux __initdata =
+ MUX(CLK_PMU1_UART0, "clk_pmu1_uart0", clk_pmu1_uart0_p, CLK_SET_RATE_PARENT,
+ RK3562_PMU1_CLKSEL_CON(2), 6, 2, MFLAGS);
+
+static struct rockchip_clk_branch rk3562_clk_branches[] __initdata = {
+ /*
+ * CRU Clock-Architecture
+ */
+ /* PD_TOP */
+ COMPOSITE(CLK_MATRIX_50M_SRC, "clk_matrix_50m_src", gpll_cpll_p, 0,
+ RK3562_CLKSEL_CON(0), 7, 1, MFLAGS, 0, 5, DFLAGS,
+ RK3562_CLKGATE_CON(0), 0, GFLAGS),
+ COMPOSITE(CLK_MATRIX_100M_SRC, "clk_matrix_100m_src", gpll_cpll_p, CLK_IS_CRITICAL,
+ RK3562_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 4, DFLAGS,
+ RK3562_CLKGATE_CON(0), 1, GFLAGS),
+ COMPOSITE(CLK_MATRIX_125M_SRC, "clk_matrix_125m_src", gpll_cpll_p, 0,
+ RK3562_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 4, DFLAGS,
+ RK3562_CLKGATE_CON(0), 2, GFLAGS),
+ COMPOSITE(CLK_MATRIX_200M_SRC, "clk_matrix_200m_src", gpll_cpll_p, CLK_IS_CRITICAL,
+ RK3562_CLKSEL_CON(2), 7, 1, MFLAGS, 0, 4, DFLAGS,
+ RK3562_CLKGATE_CON(0), 4, GFLAGS),
+ COMPOSITE(CLK_MATRIX_300M_SRC, "clk_matrix_300m_src", gpll_cpll_p, CLK_IS_CRITICAL,
+ RK3562_CLKSEL_CON(3), 7, 1, MFLAGS, 0, 4, DFLAGS,
+ RK3562_CLKGATE_CON(0), 6, GFLAGS),
+ COMPOSITE(ACLK_TOP, "aclk_top", gpll_cpll_p, CLK_IS_CRITICAL,
+ RK3562_CLKSEL_CON(5), 7, 1, MFLAGS, 0, 4, DFLAGS,
+ RK3562_CLKGATE_CON(1), 0, GFLAGS),
+ COMPOSITE(ACLK_TOP_VIO, "aclk_top_vio", gpll_cpll_p, 0,
+ RK3562_CLKSEL_CON(5), 15, 1, MFLAGS, 8, 4, DFLAGS,
+ RK3562_CLKGATE_CON(1), 1, GFLAGS),
+ COMPOSITE(CLK_24M_SSCSRC, "clk_24m_sscsrc", vpll_dmyhpll_gpll_cpll_p, 0,
+ RK3562_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS,
+ RK3562_CLKGATE_CON(1), 9, GFLAGS),
+ COMPOSITE(CLK_CAM0_OUT2IO, "clk_cam0_out2io", gpll_cpll_xin24m_dmyapll_p, 0,
+ RK3562_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 6, DFLAGS,
+ RK3562_CLKGATE_CON(1), 12, GFLAGS),
+ COMPOSITE(CLK_CAM1_OUT2IO, "clk_cam1_out2io", gpll_cpll_xin24m_dmyapll_p, 0,
+ RK3562_CLKSEL_CON(8), 14, 2, MFLAGS, 8, 6, DFLAGS,
+ RK3562_CLKGATE_CON(1), 13, GFLAGS),
+ COMPOSITE(CLK_CAM2_OUT2IO, "clk_cam2_out2io", gpll_cpll_xin24m_dmyapll_p, 0,
+ RK3562_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 6, DFLAGS,
+ RK3562_CLKGATE_CON(1), 14, GFLAGS),
+ COMPOSITE(CLK_CAM3_OUT2IO, "clk_cam3_out2io", gpll_cpll_xin24m_dmyapll_p, 0,
+ RK3562_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 6, DFLAGS,
+ RK3562_CLKGATE_CON(1), 15, GFLAGS),
+ FACTOR(0, "xin_osc0_half", "xin24m", 0, 1, 2),
+
+ /* PD_BUS */
+ COMPOSITE(ACLK_BUS, "aclk_bus", gpll_cpll_p, CLK_IS_CRITICAL,
+ RK3562_CLKSEL_CON(40), 7, 1, MFLAGS, 0, 5, DFLAGS,
+ RK3562_CLKGATE_CON(18), 0, GFLAGS),
+ COMPOSITE(HCLK_BUS, "hclk_bus", gpll_cpll_p, CLK_IS_CRITICAL,
+ RK3562_CLKSEL_CON(40), 15, 1, MFLAGS, 8, 6, DFLAGS,
+ RK3562_CLKGATE_CON(18), 1, GFLAGS),
+ COMPOSITE(PCLK_BUS, "pclk_bus", gpll_cpll_p, CLK_IS_CRITICAL,
+ RK3562_CLKSEL_CON(41), 7, 1, MFLAGS, 0, 5, DFLAGS,
+ RK3562_CLKGATE_CON(18), 2, GFLAGS),
+ GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0,
+ RK3562_CLKGATE_CON(19), 0, GFLAGS),
+ GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0,
+ RK3562_CLKGATE_CON(19), 1, GFLAGS),
+ GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0,
+ RK3562_CLKGATE_CON(19), 2, GFLAGS),
+ GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus", 0,
+ RK3562_CLKGATE_CON(19), 3, GFLAGS),
+ GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus", 0,
+ RK3562_CLKGATE_CON(19), 4, GFLAGS),
+ COMPOSITE_NODIV(CLK_I2C, "clk_i2c", mux_200m_100m_50m_xin24m_p, 0,
+ RK3562_CLKSEL_CON(41), 8, 2, MFLAGS,
+ RK3562_CLKGATE_CON(19), 5, GFLAGS),
+ GATE(CLK_I2C1, "clk_i2c1", "clk_i2c", 0,
+ RK3562_CLKGATE_CON(19), 6, GFLAGS),
+ GATE(CLK_I2C2, "clk_i2c2", "clk_i2c", 0,
+ RK3562_CLKGATE_CON(19), 7, GFLAGS),
+ GATE(CLK_I2C3, "clk_i2c3", "clk_i2c", 0,
+ RK3562_CLKGATE_CON(19), 8, GFLAGS),
+ GATE(CLK_I2C4, "clk_i2c4", "clk_i2c", 0,
+ RK3562_CLKGATE_CON(19), 9, GFLAGS),
+ GATE(CLK_I2C5, "clk_i2c5", "clk_i2c", 0,
+ RK3562_CLKGATE_CON(19), 10, GFLAGS),
+ COMPOSITE_NODIV(DCLK_BUS_GPIO, "dclk_bus_gpio", mux_xin24m_32k_p, 0,
+ RK3562_CLKSEL_CON(41), 15, 1, MFLAGS,
+ RK3562_CLKGATE_CON(20), 4, GFLAGS),
+ GATE(DCLK_BUS_GPIO3, "dclk_bus_gpio3", "dclk_bus_gpio", 0,
+ RK3562_CLKGATE_CON(20), 5, GFLAGS),
+ GATE(DCLK_BUS_GPIO4, "dclk_bus_gpio4", "dclk_bus_gpio", 0,
+ RK3562_CLKGATE_CON(20), 6, GFLAGS),
+ GATE(PCLK_TIMER, "pclk_timer", "pclk_bus", 0,
+ RK3562_CLKGATE_CON(21), 0, GFLAGS),
+ GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0,
+ RK3562_CLKGATE_CON(21), 1, GFLAGS),
+ GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0,
+ RK3562_CLKGATE_CON(21), 2, GFLAGS),
+ GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0,
+ RK3562_CLKGATE_CON(21), 3, GFLAGS),
+ GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0,
+ RK3562_CLKGATE_CON(21), 4, GFLAGS),
+ GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0,
+ RK3562_CLKGATE_CON(21), 5, GFLAGS),
+ GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0,
+ RK3562_CLKGATE_CON(21), 6, GFLAGS),
+ GATE(PCLK_STIMER, "pclk_stimer", "pclk_bus", CLK_IGNORE_UNUSED,
+ RK3562_CLKGATE_CON(21), 7, GFLAGS),
+ GATE(CLK_STIMER0, "clk_stimer0", "xin24m", CLK_IGNORE_UNUSED,
+ RK3562_CLKGATE_CON(21), 8, GFLAGS),
+ GATE(CLK_STIMER1, "clk_stimer1", "xin24m", CLK_IGNORE_UNUSED,
+ RK3562_CLKGATE_CON(21), 9, GFLAGS),
+ GATE(PCLK_WDTNS, "pclk_wdtns", "pclk_bus", 0,
+ RK3562_CLKGATE_CON(22), 0, GFLAGS),
+ GATE(CLK_WDTNS, "clk_wdtns", "xin24m", 0,
+ RK3562_CLKGATE_CON(22), 1, GFLAGS),
+ GATE(PCLK_GRF, "pclk_grf", "pclk_bus", CLK_IGNORE_UNUSED,
+ RK3562_CLKGATE_CON(22), 2, GFLAGS),
+ GATE(PCLK_SGRF, "pclk_sgrf", "pclk_bus", CLK_IGNORE_UNUSED,
+ RK3562_CLKGATE_CON(22), 3, GFLAGS),
+ GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0,
+ RK3562_CLKGATE_CON(22), 4, GFLAGS),
+ GATE(PCLK_INTC, "pclk_intc", "pclk_bus", 0,
+ RK3562_CLKGATE_CON(22), 5, GFLAGS),
+ GATE(ACLK_BUS_GIC400, "aclk_bus_gic400", "aclk_bus", CLK_IGNORE_UNUSED,
+ RK3562_CLKGATE_CON(22), 6, GFLAGS),
+ GATE(ACLK_BUS_SPINLOCK, "aclk_bus_spinlock", "aclk_bus", 0,
+ RK3562_CLKGATE_CON(23), 0, GFLAGS),
+ GATE(ACLK_DCF, "aclk_dcf", "aclk_bus", CLK_IGNORE_UNUSED,
+ RK3562_CLKGATE_CON(23), 1, GFLAGS),
+ GATE(PCLK_DCF, "pclk_dcf", "pclk_bus", CLK_IGNORE_UNUSED,
+ RK3562_CLKGATE_CON(23), 2, GFLAGS),
+ GATE(FCLK_BUS_CM0_CORE, "fclk_bus_cm0_core", "hclk_bus", 0,
+ RK3562_CLKGATE_CON(23), 3, GFLAGS),
+ GATE(CLK_BUS_CM0_RTC, "clk_bus_cm0_rtc", "clk_rtc_32k", 0,
+ RK3562_CLKGATE_CON(23), 4, GFLAGS),
+ GATE(HCLK_ICACHE, "hclk_icache", "hclk_bus", CLK_IGNORE_UNUSED,
+ RK3562_CLKGATE_CON(23), 8, GFLAGS),
+ GATE(HCLK_DCACHE, "hclk_dcache", "hclk_bus", CLK_IGNORE_UNUSED,
+ RK3562_CLKGATE_CON(23), 9, GFLAGS),
+ GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0,
+ RK3562_CLKGATE_CON(24), 0, GFLAGS),
+ COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0,
+ RK3562_CLKSEL_CON(43), 0, 11, DFLAGS,
+ RK3562_CLKGATE_CON(24), 1, GFLAGS),
+ COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m", 0,
+ RK3562_CLKSEL_CON(43), 11, 5, DFLAGS,
+ RK3562_CLKGATE_CON(24), 3, GFLAGS),
+ GATE(PCLK_DFT2APB, "pclk_dft2apb", "pclk_bus", CLK_IGNORE_UNUSED,
+ RK3562_CLKGATE_CON(24), 4, GFLAGS),
+ COMPOSITE_NOMUX(CLK_SARADC_VCCIO156, "clk_saradc_vccio156", "xin24m", 0,
+ RK3562_CLKSEL_CON(44), 0, 12, DFLAGS,
+ RK3562_CLKGATE_CON(24), 9, GFLAGS),
+ GATE(PCLK_GMAC, "pclk_gmac", "pclk_bus", 0,
+ RK3562_CLKGATE_CON(25), 0, GFLAGS),
+ GATE(ACLK_GMAC, "aclk_gmac", "aclk_bus", 0,
+ RK3562_CLKGATE_CON(25), 1, GFLAGS),
+ COMPOSITE_NODIV(CLK_GMAC_125M_CRU_I, "clk_gmac_125m_cru_i", mux_125m_xin24m_p, 0,
+ RK3562_CLKSEL_CON(45), 8, 1, MFLAGS,
+ RK3562_CLKGATE_CON(25), 2, GFLAGS),
+ COMPOSITE_NODIV(CLK_GMAC_50M_CRU_I, "clk_gmac_50m_cru_i", mux_50m_xin24m_p, 0,
+ RK3562_CLKSEL_CON(45), 7, 1, MFLAGS,
+ RK3562_CLKGATE_CON(25), 3, GFLAGS),
+ COMPOSITE(CLK_GMAC_ETH_OUT2IO, "clk_gmac_eth_out2io", gpll_cpll_p, 0,
+ RK3562_CLKSEL_CON(46), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RK3562_CLKGATE_CON(25), 4, GFLAGS),
+ GATE(PCLK_APB2ASB_VCCIO156, "pclk_apb2asb_vccio156", "pclk_bus", CLK_IS_CRITICAL,
+ RK3562_CLKGATE_CON(25), 5, GFLAGS),
+ GATE(PCLK_TO_VCCIO156, "pclk_to_vccio156", "pclk_bus", CLK_IS_CRITICAL,
+ RK3562_CLKGATE_CON(25), 6, GFLAGS),
+ GATE(PCLK_DSIPHY, "pclk_dsiphy", "pclk_bus", 0,
+ RK3562_CLKGATE_CON(25), 8, GFLAGS),
+ GATE(PCLK_DSITX, "pclk_dsitx", "pclk_bus", 0,
+ RK3562_CLKGATE_CON(25), 9, GFLAGS),
+ GATE(PCLK_CPU_EMA_DET, "pclk_cpu_ema_det", "pclk_bus", CLK_IGNORE_UNUSED,
+ RK3562_CLKGATE_CON(25), 10, GFLAGS),
+ GATE(PCLK_HASH, "pclk_hash", "pclk_bus", 0,
+ RK3562_CLKGATE_CON(25), 11, GFLAGS),
+ GATE(PCLK_TOPCRU, "pclk_topcru", "pclk_bus", CLK_IGNORE_UNUSED,
+ RK3562_CLKGATE_CON(25), 15, GFLAGS),
+ GATE(PCLK_ASB2APB_VCCIO156, "pclk_asb2apb_vccio156", "pclk_to_vccio156", CLK_IS_CRITICAL,
+ RK3562_CLKGATE_CON(26), 0, GFLAGS),
+ GATE(PCLK_IOC_VCCIO156, "pclk_ioc_vccio156", "pclk_to_vccio156", CLK_IS_CRITICAL,
+ RK3562_CLKGATE_CON(26), 1, GFLAGS),
+ GATE(PCLK_GPIO3_VCCIO156, "pclk_gpio3_vccio156", "pclk_to_vccio156", 0,
+ RK3562_CLKGATE_CON(26), 2, GFLAGS),
+ GATE(PCLK_GPIO4_VCCIO156, "pclk_gpio4_vccio156", "pclk_to_vccio156", 0,
+ RK3562_CLKGATE_CON(26), 3, GFLAGS),
+ GATE(PCLK_SARADC_VCCIO156, "pclk_saradc_vccio156", "pclk_to_vccio156", 0,
+ RK3562_CLKGATE_CON(26), 4, GFLAGS),
+ GATE(PCLK_MAC100, "pclk_mac100", "pclk_bus", 0,
+ RK3562_CLKGATE_CON(27), 0, GFLAGS),
+ GATE(ACLK_MAC100, "aclk_mac100", "aclk_bus", 0,
+ RK3562_CLKGATE_CON(27), 1, GFLAGS),
+ COMPOSITE_NODIV(CLK_MAC100_50M_MATRIX, "clk_mac100_50m_matrix", mux_50m_xin24m_p, 0,
+ RK3562_CLKSEL_CON(47), 7, 1, MFLAGS,
+ RK3562_CLKGATE_CON(27), 2, GFLAGS),
+
+ /* PD_CORE */
+ COMPOSITE_NOMUX(0, "aclk_core_pre", "scmi_clk_cpu", CLK_IGNORE_UNUSED,
+ RK3562_CLKSEL_CON(11), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
+ RK3562_CLKGATE_CON(4), 3, GFLAGS),
+ COMPOSITE_NOMUX(0, "pclk_dbg_pre", "scmi_clk_cpu", CLK_IGNORE_UNUSED,
+ RK3562_CLKSEL_CON(12), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
+ RK3562_CLKGATE_CON(4), 5, GFLAGS),
+ COMPOSITE_NOMUX(HCLK_CORE, "hclk_core", "gpll", CLK_IS_CRITICAL,
+ RK3562_CLKSEL_CON(13), 0, 6, DFLAGS,
+ RK3562_CLKGATE_CON(5), 2, GFLAGS),
+ GATE(0, "pclk_dbg_daplite", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
+ RK3562_CLKGATE_CON(4), 10, GFLAGS),
+
+ /* PD_DDR */
+ FACTOR_GATE(0, "clk_gpll_mux_to_ddr", "gpll", 0, 1, 4,
+ RK3328_CLKGATE_CON(1), 6, GFLAGS),
+ COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "clk_gpll_mux_to_ddr", CLK_IS_CRITICAL,
+ RK3562_DDR_CLKSEL_CON(1), 8, 5, DFLAGS,
+ RK3562_DDR_CLKGATE_CON(0), 3, GFLAGS),
+ COMPOSITE_NOMUX(CLK_MSCH_BRG_BIU, "clk_msch_brg_biu", "clk_gpll_mux_to_ddr", CLK_IS_CRITICAL,
+ RK3562_DDR_CLKSEL_CON(1), 0, 4, DFLAGS,
+ RK3562_DDR_CLKGATE_CON(0), 4, GFLAGS),
+ GATE(PCLK_DDR_HWLP, "pclk_ddr_hwlp", "pclk_ddr", CLK_IGNORE_UNUSED,
+ RK3562_DDR_CLKGATE_CON(0), 6, GFLAGS),
+ GATE(PCLK_DDR_UPCTL, "pclk_ddr_upctl", "pclk_ddr", CLK_IGNORE_UNUSED,
+ RK3562_DDR_CLKGATE_CON(0), 7, GFLAGS),
+ GATE(PCLK_DDR_PHY, "pclk_ddr_phy", "pclk_ddr", CLK_IGNORE_UNUSED,
+ RK3562_DDR_CLKGATE_CON(0), 8, GFLAGS),
+ GATE(PCLK_DDR_DFICTL, "pclk_ddr_dfictl", "pclk_ddr", CLK_IGNORE_UNUSED,
+ RK3562_DDR_CLKGATE_CON(0), 9, GFLAGS),
+ GATE(PCLK_DDR_DMA2DDR, "pclk_ddr_dma2ddr", "pclk_ddr", CLK_IGNORE_UNUSED,
+ RK3562_DDR_CLKGATE_CON(0), 10, GFLAGS),
+ GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED,
+ RK3562_DDR_CLKGATE_CON(1), 0, GFLAGS),
+ GATE(TMCLK_DDR_MON, "tmclk_ddr_mon", "xin24m", CLK_IGNORE_UNUSED,
+ RK3562_DDR_CLKGATE_CON(1), 1, GFLAGS),
+ GATE(PCLK_DDR_GRF, "pclk_ddr_grf", "pclk_ddr", CLK_IGNORE_UNUSED,
+ RK3562_DDR_CLKGATE_CON(1), 2, GFLAGS),
+ GATE(PCLK_DDR_CRU, "pclk_ddr_cru", "pclk_ddr", CLK_IGNORE_UNUSED,
+ RK3562_DDR_CLKGATE_CON(1), 3, GFLAGS),
+ GATE(PCLK_SUBDDR_CRU, "pclk_subddr_cru", "pclk_ddr", CLK_IGNORE_UNUSED,
+ RK3562_DDR_CLKGATE_CON(1), 4, GFLAGS),
+
+ /* PD_GPU */
+ COMPOSITE(CLK_GPU_PRE, "clk_gpu_pre", gpll_cpll_p, 0,
+ RK3562_CLKSEL_CON(18), 7, 1, MFLAGS, 0, 4, DFLAGS,
+ RK3562_CLKGATE_CON(8), 0, GFLAGS),
+ COMPOSITE_NOMUX(ACLK_GPU_PRE, "aclk_gpu_pre", "clk_gpu_pre", 0,
+ RK3562_CLKSEL_CON(19), 0, 4, DFLAGS,
+ RK3562_CLKGATE_CON(8), 2, GFLAGS),
+ GATE(CLK_GPU, "clk_gpu", "clk_gpu_pre", 0,
+ RK3562_CLKGATE_CON(8), 4, GFLAGS),
+ COMPOSITE_NODIV(CLK_GPU_BRG, "clk_gpu_brg", mux_200m_100m_p, 0,
+ RK3562_CLKSEL_CON(19), 15, 1, MFLAGS,
+ RK3562_CLKGATE_CON(8), 8, GFLAGS),
+
+ /* PD_NPU */
+ COMPOSITE(CLK_NPU_PRE, "clk_npu_pre", gpll_cpll_p, 0,
+ RK3562_CLKSEL_CON(15), 7, 1, MFLAGS, 0, 4, DFLAGS,
+ RK3562_CLKGATE_CON(6), 0, GFLAGS),
+ COMPOSITE_NOMUX(HCLK_NPU_PRE, "hclk_npu_pre", "clk_npu_pre", 0,
+ RK3562_CLKSEL_CON(16), 0, 4, DFLAGS,
+ RK3562_CLKGATE_CON(6), 1, GFLAGS),
+ GATE(ACLK_RKNN, "aclk_rknn", "clk_npu_pre", 0,
+ RK3562_CLKGATE_CON(6), 4, GFLAGS),
+ GATE(HCLK_RKNN, "hclk_rknn", "hclk_npu_pre", 0,
+ RK3562_CLKGATE_CON(6), 5, GFLAGS),
+
+ /* PD_PERI */
+ COMPOSITE(ACLK_PERI, "aclk_peri", gpll_cpll_p, CLK_IS_CRITICAL,
+ RK3562_PERI_CLKSEL_CON(0), 7, 1, MFLAGS, 0, 5, DFLAGS,
+ RK3562_PERI_CLKGATE_CON(1), 0, GFLAGS),
+ COMPOSITE(HCLK_PERI, "hclk_peri", gpll_cpll_p, CLK_IS_CRITICAL,
+ RK3562_PERI_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 6, DFLAGS,
+ RK3562_PERI_CLKGATE_CON(1), 1, GFLAGS),
+ COMPOSITE(PCLK_PERI, "pclk_peri", gpll_cpll_p, CLK_IS_CRITICAL,
+ RK3562_PERI_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 5, DFLAGS,
+ RK3562_PERI_CLKGATE_CON(1), 2, GFLAGS),
+ GATE(PCLK_PERICRU, "pclk_pericru", "pclk_peri", CLK_IGNORE_UNUSED,
+ RK3562_PERI_CLKGATE_CON(1), 6, GFLAGS),
+ GATE(HCLK_SAI0, "hclk_sai0", "hclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(2), 0, GFLAGS),
+ COMPOSITE(CLK_SAI0_SRC, "clk_sai0_src", gpll_cpll_hpll_p, 0,
+ RK3562_PERI_CLKSEL_CON(1), 14, 2, MFLAGS, 8, 6, DFLAGS,
+ RK3562_PERI_CLKGATE_CON(2), 1, GFLAGS),
+ COMPOSITE_FRACMUX(CLK_SAI0_FRAC, "clk_sai0_frac", "clk_sai0_src", CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(2), 0,
+ RK3562_PERI_CLKGATE_CON(2), 2, GFLAGS,
+ &rk3562_clk_sai0_fracmux),
+ GATE(MCLK_SAI0, "mclk_sai0", "clk_sai0", 0,
+ RK3562_PERI_CLKGATE_CON(2), 3, GFLAGS),
+ COMPOSITE_NODIV(MCLK_SAI0_OUT2IO, "mclk_sai0_out2io", mclk_sai0_out2io_p, CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(3), 5, 1, MFLAGS,
+ RK3562_PERI_CLKGATE_CON(2), 4, GFLAGS),
+ GATE(HCLK_SAI1, "hclk_sai1", "hclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(2), 5, GFLAGS),
+ COMPOSITE(CLK_SAI1_SRC, "clk_sai1_src", gpll_cpll_hpll_p, 0,
+ RK3562_PERI_CLKSEL_CON(3), 14, 2, MFLAGS, 8, 6, DFLAGS,
+ RK3562_PERI_CLKGATE_CON(2), 6, GFLAGS),
+ COMPOSITE_FRACMUX(CLK_SAI1_FRAC, "clk_sai1_frac", "clk_sai1_src", CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(4), 0,
+ RK3562_PERI_CLKGATE_CON(2), 7, GFLAGS,
+ &rk3562_clk_sai1_fracmux),
+ GATE(MCLK_SAI1, "mclk_sai1", "clk_sai1", 0,
+ RK3562_PERI_CLKGATE_CON(2), 8, GFLAGS),
+ COMPOSITE_NODIV(MCLK_SAI1_OUT2IO, "mclk_sai1_out2io", mclk_sai1_out2io_p, CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(5), 5, 1, MFLAGS,
+ RK3562_PERI_CLKGATE_CON(2), 9, GFLAGS),
+ GATE(HCLK_SAI2, "hclk_sai2", "hclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(2), 10, GFLAGS),
+ COMPOSITE(CLK_SAI2_SRC, "clk_sai2_src", gpll_cpll_hpll_p, 0,
+ RK3562_PERI_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,
+ RK3562_PERI_CLKGATE_CON(2), 11, GFLAGS),
+ COMPOSITE_FRACMUX(CLK_SAI2_FRAC, "clk_sai2_frac", "clk_sai2_src", CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(7), 0,
+ RK3562_PERI_CLKGATE_CON(2), 12, GFLAGS,
+ &rk3562_clk_sai2_fracmux),
+ GATE(MCLK_SAI2, "mclk_sai2", "clk_sai2", 0,
+ RK3562_PERI_CLKGATE_CON(2), 13, GFLAGS),
+ COMPOSITE_NODIV(MCLK_SAI2_OUT2IO, "mclk_sai2_out2io", mclk_sai2_out2io_p, CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(8), 5, 1, MFLAGS,
+ RK3562_PERI_CLKGATE_CON(2), 14, GFLAGS),
+ GATE(HCLK_DSM, "hclk_dsm", "hclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(3), 1, GFLAGS),
+ GATE(CLK_DSM, "clk_dsm", "mclk_sai1", 0,
+ RK3562_PERI_CLKGATE_CON(3), 2, GFLAGS),
+ GATE(HCLK_PDM, "hclk_pdm", "hclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(3), 4, GFLAGS),
+ COMPOSITE(MCLK_PDM, "mclk_pdm", gpll_cpll_hpll_xin24m_p, 0,
+ RK3562_PERI_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3562_PERI_CLKGATE_CON(3), 5, GFLAGS),
+ GATE(HCLK_SPDIF, "hclk_spdif", "hclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(3), 8, GFLAGS),
+ COMPOSITE(CLK_SPDIF_SRC, "clk_spdif_src", gpll_cpll_hpll_p, 0,
+ RK3562_PERI_CLKSEL_CON(13), 14, 2, MFLAGS, 8, 6, DFLAGS,
+ RK3562_PERI_CLKGATE_CON(3), 9, GFLAGS),
+ COMPOSITE_FRACMUX(CLK_SPDIF_FRAC, "clk_spdif_frac", "clk_spdif_src", CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(14), 0,
+ RK3562_PERI_CLKGATE_CON(3), 10, GFLAGS,
+ &rk3562_clk_spdif_fracmux),
+ GATE(MCLK_SPDIF, "mclk_spdif", "clk_spdif", 0,
+ RK3562_PERI_CLKGATE_CON(3), 11, GFLAGS),
+ GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(4), 0, GFLAGS),
+ COMPOSITE(CCLK_SDMMC0, "cclk_sdmmc0", gpll_cpll_xin24m_dmyhpll_p, 0,
+ RK3562_PERI_CLKSEL_CON(16), 14, 2, MFLAGS, 0, 8, DFLAGS,
+ RK3562_PERI_CLKGATE_CON(4), 1, GFLAGS),
+ MMC(SCLK_SDMMC0_DRV, "sdmmc0_drv", "cclk_sdmmc0", RK3562_SDMMC0_CON0, 1),
+ MMC(SCLK_SDMMC0_SAMPLE, "sdmmc0_sample", "cclk_sdmmc0", RK3562_SDMMC0_CON1, 1),
+ GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(4), 2, GFLAGS),
+ COMPOSITE(CCLK_SDMMC1, "cclk_sdmmc1", gpll_cpll_xin24m_dmyhpll_p, 0,
+ RK3562_PERI_CLKSEL_CON(17), 14, 2, MFLAGS, 0, 8, DFLAGS,
+ RK3562_PERI_CLKGATE_CON(4), 3, GFLAGS),
+ MMC(SCLK_SDMMC1_DRV, "sdmmc1_drv", "cclk_sdmmc1", RK3562_SDMMC1_CON0, 1),
+ MMC(SCLK_SDMMC1_SAMPLE, "sdmmc1_sample", "cclk_sdmmc1", RK3562_SDMMC1_CON1, 1),
+ GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(4), 8, GFLAGS),
+ GATE(ACLK_EMMC, "aclk_emmc", "aclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(4), 9, GFLAGS),
+ COMPOSITE(CCLK_EMMC, "cclk_emmc", gpll_cpll_xin24m_dmyhpll_p, 0,
+ RK3562_PERI_CLKSEL_CON(18), 14, 2, MFLAGS, 0, 8, DFLAGS,
+ RK3562_PERI_CLKGATE_CON(4), 10, GFLAGS),
+ COMPOSITE(BCLK_EMMC, "bclk_emmc", gpll_cpll_p, 0,
+ RK3562_PERI_CLKSEL_CON(19), 15, 1, MFLAGS, 8, 7, DFLAGS,
+ RK3562_PERI_CLKGATE_CON(4), 11, GFLAGS),
+ GATE(TMCLK_EMMC, "tmclk_emmc", "xin24m", 0,
+ RK3562_PERI_CLKGATE_CON(4), 12, GFLAGS),
+ COMPOSITE(SCLK_SFC, "sclk_sfc", gpll_cpll_xin24m_p, 0,
+ RK3562_PERI_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS,
+ RK3562_PERI_CLKGATE_CON(4), 13, GFLAGS),
+ GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(4), 14, GFLAGS),
+ GATE(HCLK_USB2HOST, "hclk_usb2host", "hclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(5), 0, GFLAGS),
+ GATE(HCLK_USB2HOST_ARB, "hclk_usb2host_arb", "hclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(5), 1, GFLAGS),
+ GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(6), 0, GFLAGS),
+ COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_xin24m_p, 0,
+ RK3562_PERI_CLKSEL_CON(20), 12, 2, MFLAGS,
+ RK3562_PERI_CLKGATE_CON(6), 1, GFLAGS),
+ GATE(SCLK_IN_SPI1, "sclk_in_spi1", "sclk_in_spi1_io", 0,
+ RK3562_PERI_CLKGATE_CON(6), 2, GFLAGS),
+ GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(6), 3, GFLAGS),
+ COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", mux_200m_100m_50m_xin24m_p, 0,
+ RK3562_PERI_CLKSEL_CON(20), 14, 2, MFLAGS,
+ RK3562_PERI_CLKGATE_CON(6), 4, GFLAGS),
+ GATE(SCLK_IN_SPI2, "sclk_in_spi2", "sclk_in_spi2_io", 0,
+ RK3562_PERI_CLKGATE_CON(6), 5, GFLAGS),
+ GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(7), 0, GFLAGS),
+ GATE(PCLK_UART2, "pclk_uart2", "pclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(7), 1, GFLAGS),
+ GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(7), 2, GFLAGS),
+ GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(7), 3, GFLAGS),
+ GATE(PCLK_UART5, "pclk_uart5", "pclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(7), 4, GFLAGS),
+ GATE(PCLK_UART6, "pclk_uart6", "pclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(7), 5, GFLAGS),
+ GATE(PCLK_UART7, "pclk_uart7", "pclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(7), 6, GFLAGS),
+ GATE(PCLK_UART8, "pclk_uart8", "pclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(7), 7, GFLAGS),
+ GATE(PCLK_UART9, "pclk_uart9", "pclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(7), 8, GFLAGS),
+ COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_p, 0,
+ RK3562_PERI_CLKSEL_CON(21), 8, 1, MFLAGS, 0, 7, DFLAGS,
+ RK3562_PERI_CLKGATE_CON(7), 9, GFLAGS),
+ COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(22), 0,
+ RK3562_PERI_CLKGATE_CON(7), 10, GFLAGS,
+ &rk3562_clk_uart1_fracmux),
+ GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0,
+ RK3562_PERI_CLKGATE_CON(7), 11, GFLAGS),
+ COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_p, 0,
+ RK3562_PERI_CLKSEL_CON(23), 8, 1, MFLAGS, 0, 7, DFLAGS,
+ RK3562_PERI_CLKGATE_CON(7), 12, GFLAGS),
+ COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(24), 0,
+ RK3562_PERI_CLKGATE_CON(7), 13, GFLAGS,
+ &rk3562_clk_uart2_fracmux),
+ GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0,
+ RK3562_PERI_CLKGATE_CON(7), 14, GFLAGS),
+ COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_p, 0,
+ RK3562_PERI_CLKSEL_CON(25), 8, 1, MFLAGS, 0, 7, DFLAGS,
+ RK3562_PERI_CLKGATE_CON(7), 15, GFLAGS),
+ COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(26), 0,
+ RK3562_PERI_CLKGATE_CON(8), 0, GFLAGS,
+ &rk3562_clk_uart3_fracmux),
+ GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0,
+ RK3562_PERI_CLKGATE_CON(8), 1, GFLAGS),
+ COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_p, 0,
+ RK3562_PERI_CLKSEL_CON(27), 8, 1, MFLAGS, 0, 7, DFLAGS,
+ RK3562_PERI_CLKGATE_CON(8), 2, GFLAGS),
+ COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(28), 0,
+ RK3562_PERI_CLKGATE_CON(8), 3, GFLAGS,
+ &rk3562_clk_uart4_fracmux),
+ GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0,
+ RK3562_PERI_CLKGATE_CON(8), 4, GFLAGS),
+ COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_p, 0,
+ RK3562_PERI_CLKSEL_CON(29), 8, 1, MFLAGS, 0, 7, DFLAGS,
+ RK3562_PERI_CLKGATE_CON(8), 5, GFLAGS),
+ COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(30), 0,
+ RK3562_PERI_CLKGATE_CON(8), 6, GFLAGS,
+ &rk3562_clk_uart5_fracmux),
+ GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
+ RK3562_PERI_CLKGATE_CON(8), 7, GFLAGS),
+ COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_p, 0,
+ RK3562_PERI_CLKSEL_CON(31), 8, 1, MFLAGS, 0, 7, DFLAGS,
+ RK3562_PERI_CLKGATE_CON(8), 8, GFLAGS),
+ COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(32), 0,
+ RK3562_PERI_CLKGATE_CON(8), 9, GFLAGS,
+ &rk3562_clk_uart6_fracmux),
+ GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0,
+ RK3562_PERI_CLKGATE_CON(8), 10, GFLAGS),
+ COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_p, 0,
+ RK3562_PERI_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 7, DFLAGS,
+ RK3562_PERI_CLKGATE_CON(8), 11, GFLAGS),
+ COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(34), 0,
+ RK3562_PERI_CLKGATE_CON(8), 12, GFLAGS,
+ &rk3562_clk_uart7_fracmux),
+ GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0,
+ RK3562_PERI_CLKGATE_CON(8), 13, GFLAGS),
+ COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_p, 0,
+ RK3562_PERI_CLKSEL_CON(35), 8, 1, MFLAGS, 0, 7, DFLAGS,
+ RK3562_PERI_CLKGATE_CON(8), 14, GFLAGS),
+ COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(36), 0,
+ RK3562_PERI_CLKGATE_CON(8), 15, GFLAGS,
+ &rk3562_clk_uart8_fracmux),
+ GATE(SCLK_UART8, "sclk_uart8", "clk_uart8", 0,
+ RK3562_PERI_CLKGATE_CON(9), 0, GFLAGS),
+ COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_p, 0,
+ RK3562_PERI_CLKSEL_CON(37), 8, 1, MFLAGS, 0, 7, DFLAGS,
+ RK3562_PERI_CLKGATE_CON(9), 1, GFLAGS),
+ COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT,
+ RK3562_PERI_CLKSEL_CON(38), 0,
+ RK3562_PERI_CLKGATE_CON(9), 2, GFLAGS,
+ &rk3562_clk_uart9_fracmux),
+ GATE(SCLK_UART9, "sclk_uart9", "clk_uart9", 0,
+ RK3562_PERI_CLKGATE_CON(9), 3, GFLAGS),
+ GATE(PCLK_PWM1_PERI, "pclk_pwm1_peri", "pclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(10), 0, GFLAGS),
+ COMPOSITE_NODIV(CLK_PWM1_PERI, "clk_pwm1_peri", mux_100m_50m_xin24m_p, 0,
+ RK3562_PERI_CLKSEL_CON(40), 0, 2, MFLAGS,
+ RK3562_PERI_CLKGATE_CON(10), 1, GFLAGS),
+ GATE(CLK_CAPTURE_PWM1_PERI, "clk_capture_pwm1_peri", "xin24m", 0,
+ RK3562_PERI_CLKGATE_CON(10), 2, GFLAGS),
+ GATE(PCLK_PWM2_PERI, "pclk_pwm2_peri", "pclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(10), 3, GFLAGS),
+ COMPOSITE_NODIV(CLK_PWM2_PERI, "clk_pwm2_peri", mux_100m_50m_xin24m_p, 0,
+ RK3562_PERI_CLKSEL_CON(40), 6, 2, MFLAGS,
+ RK3562_PERI_CLKGATE_CON(10), 4, GFLAGS),
+ GATE(CLK_CAPTURE_PWM2_PERI, "clk_capture_pwm2_peri", "xin24m", 0,
+ RK3562_PERI_CLKGATE_CON(10), 5, GFLAGS),
+ GATE(PCLK_PWM3_PERI, "pclk_pwm3_peri", "pclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(10), 6, GFLAGS),
+ COMPOSITE_NODIV(CLK_PWM3_PERI, "clk_pwm3_peri", mux_100m_50m_xin24m_p, 0,
+ RK3562_PERI_CLKSEL_CON(40), 8, 2, MFLAGS,
+ RK3562_PERI_CLKGATE_CON(10), 7, GFLAGS),
+ GATE(CLK_CAPTURE_PWM3_PERI, "clk_capture_pwm3_peri", "xin24m", 0,
+ RK3562_PERI_CLKGATE_CON(10), 8, GFLAGS),
+ GATE(PCLK_CAN0, "pclk_can0", "pclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(11), 0, GFLAGS),
+ COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0,
+ RK3562_PERI_CLKSEL_CON(41), 7, 1, MFLAGS, 0, 5, DFLAGS,
+ RK3562_PERI_CLKGATE_CON(11), 1, GFLAGS),
+ GATE(PCLK_CAN1, "pclk_can1", "pclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(11), 2, GFLAGS),
+ COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0,
+ RK3562_PERI_CLKSEL_CON(41), 15, 1, MFLAGS, 8, 5, DFLAGS,
+ RK3562_PERI_CLKGATE_CON(11), 3, GFLAGS),
+ GATE(PCLK_PERI_WDT, "pclk_peri_wdt", "pclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(13), 0, GFLAGS),
+ COMPOSITE_NODIV(TCLK_PERI_WDT, "tclk_peri_wdt", mux_xin24m_32k_p, 0,
+ RK3562_PERI_CLKSEL_CON(43), 15, 1, MFLAGS,
+ RK3562_PERI_CLKGATE_CON(13), 1, GFLAGS),
+ GATE(ACLK_SYSMEM, "aclk_sysmem", "aclk_peri", CLK_IGNORE_UNUSED,
+ RK3562_PERI_CLKGATE_CON(13), 2, GFLAGS),
+ GATE(HCLK_BOOTROM, "hclk_bootrom", "hclk_peri", CLK_IGNORE_UNUSED,
+ RK3562_PERI_CLKGATE_CON(13), 3, GFLAGS),
+ GATE(PCLK_PERI_GRF, "pclk_peri_grf", "pclk_peri", CLK_IGNORE_UNUSED,
+ RK3562_PERI_CLKGATE_CON(13), 4, GFLAGS),
+ GATE(ACLK_DMAC, "aclk_dmac", "aclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(13), 5, GFLAGS),
+ GATE(ACLK_RKDMAC, "aclk_rkdmac", "aclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(13), 6, GFLAGS),
+ GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(14), 0, GFLAGS),
+ GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0,
+ RK3562_PERI_CLKGATE_CON(14), 1, GFLAGS),
+ COMPOSITE_NOMUX(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "xin24m", 0,
+ RK3562_PERI_CLKSEL_CON(44), 0, 8, DFLAGS,
+ RK3562_PERI_CLKGATE_CON(14), 2, GFLAGS),
+ GATE(PCLK_OTPC_S, "pclk_otpc_s", "pclk_peri", CLK_IGNORE_UNUSED,
+ RK3562_PERI_CLKGATE_CON(14), 3, GFLAGS),
+ GATE(CLK_SBPI_OTPC_S, "clk_sbpi_otpc_s", "xin24m", CLK_IGNORE_UNUSED,
+ RK3562_PERI_CLKGATE_CON(14), 4, GFLAGS),
+ COMPOSITE_NOMUX(CLK_USER_OTPC_S, "clk_user_otpc_s", "xin24m", CLK_IGNORE_UNUSED,
+ RK3562_PERI_CLKSEL_CON(44), 8, 8, DFLAGS,
+ RK3562_PERI_CLKGATE_CON(14), 5, GFLAGS),
+ GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0,
+ RK3562_PERI_CLKGATE_CON(14), 6, GFLAGS),
+ GATE(PCLK_OTPPHY, "pclk_otpphy", "pclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(14), 7, GFLAGS),
+ GATE(PCLK_USB2PHY, "pclk_usb2phy", "pclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(15), 0, GFLAGS),
+ GATE(PCLK_PIPEPHY, "pclk_pipephy", "pclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(15), 7, GFLAGS),
+ GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(16), 4, GFLAGS),
+ COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
+ RK3562_PERI_CLKSEL_CON(46), 0, 12, DFLAGS,
+ RK3562_PERI_CLKGATE_CON(16), 5, GFLAGS),
+ GATE(PCLK_IOC_VCCIO234, "pclk_ioc_vccio234", "pclk_peri", CLK_IS_CRITICAL,
+ RK3562_PERI_CLKGATE_CON(16), 12, GFLAGS),
+ GATE(PCLK_PERI_GPIO1, "pclk_peri_gpio1", "pclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(17), 0, GFLAGS),
+ GATE(PCLK_PERI_GPIO2, "pclk_peri_gpio2", "pclk_peri", 0,
+ RK3562_PERI_CLKGATE_CON(17), 1, GFLAGS),
+ COMPOSITE_NODIV(DCLK_PERI_GPIO, "dclk_peri_gpio", mux_xin24m_32k_p, 0,
+ RK3562_PERI_CLKSEL_CON(47), 8, 1, MFLAGS,
+ RK3562_PERI_CLKGATE_CON(17), 4, GFLAGS),
+ GATE(DCLK_PERI_GPIO1, "dclk_peri_gpio1", "dclk_peri_gpio", 0,
+ RK3562_PERI_CLKGATE_CON(17), 2, GFLAGS),
+ GATE(DCLK_PERI_GPIO2, "dclk_peri_gpio2", "dclk_peri_gpio", 0,
+ RK3562_PERI_CLKGATE_CON(17), 3, GFLAGS),
+
+ /* PD_PHP */
+ COMPOSITE(ACLK_PHP, "aclk_php", gpll_cpll_p, 0,
+ RK3562_CLKSEL_CON(36), 7, 1, MFLAGS, 0, 4, DFLAGS,
+ RK3562_CLKGATE_CON(16), 0, GFLAGS),
+ COMPOSITE_NOMUX(PCLK_PHP, "pclk_php", "aclk_php", 0,
+ RK3562_CLKSEL_CON(36), 8, 4, DFLAGS,
+ RK3562_CLKGATE_CON(16), 1, GFLAGS),
+ GATE(ACLK_PCIE20_MST, "aclk_pcie20_mst", "aclk_php", 0,
+ RK3562_CLKGATE_CON(16), 4, GFLAGS),
+ GATE(ACLK_PCIE20_SLV, "aclk_pcie20_slv", "aclk_php", 0,
+ RK3562_CLKGATE_CON(16), 5, GFLAGS),
+ GATE(ACLK_PCIE20_DBI, "aclk_pcie20_dbi", "aclk_php", 0,
+ RK3562_CLKGATE_CON(16), 6, GFLAGS),
+ GATE(PCLK_PCIE20, "pclk_pcie20", "pclk_php", 0,
+ RK3562_CLKGATE_CON(16), 7, GFLAGS),
+ GATE(CLK_PCIE20_AUX, "clk_pcie20_aux", "xin24m", 0,
+ RK3562_CLKGATE_CON(16), 8, GFLAGS),
+ GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_php", 0,
+ RK3562_CLKGATE_CON(16), 10, GFLAGS),
+ COMPOSITE_NODIV(CLK_USB3OTG_SUSPEND, "clk_usb3otg_suspend", mux_xin24m_32k_p, 0,
+ RK3562_CLKSEL_CON(36), 15, 1, MFLAGS,
+ RK3562_CLKGATE_CON(16), 11, GFLAGS),
+ GATE(CLK_USB3OTG_REF, "clk_usb3otg_ref", "xin24m", 0,
+ RK3562_CLKGATE_CON(16), 12, GFLAGS),
+ GATE(CLK_PIPEPHY_REF_FUNC, "clk_pipephy_ref_func", "pclk_pcie20", 0,
+ RK3562_CLKGATE_CON(17), 3, GFLAGS),
+
+ /* PD_PMU1 */
+ COMPOSITE_NOMUX(CLK_200M_PMU, "clk_200m_pmu", "cpll", CLK_IS_CRITICAL,
+ RK3562_PMU1_CLKSEL_CON(0), 0, 5, DFLAGS,
+ RK3562_PMU1_CLKGATE_CON(0), 1, GFLAGS),
+ /* PD_PMU0 */
+ COMPOSITE_FRACMUX(CLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", CLK_IS_CRITICAL,
+ RK3562_PMU0_CLKSEL_CON(0), 0,
+ RK3562_PMU0_CLKGATE_CON(0), 15, GFLAGS,
+ &rk3562_rtc32k_pmu_fracmux),
+ COMPOSITE_NOMUX(BUSCLK_PDPMU0, "busclk_pdpmu0", "clk_200m_pmu", CLK_IS_CRITICAL,
+ RK3562_PMU0_CLKSEL_CON(1), 3, 2, DFLAGS,
+ RK3562_PMU0_CLKGATE_CON(0), 14, GFLAGS),
+ GATE(PCLK_PMU0_CRU, "pclk_pmu0_cru", "busclk_pdpmu0", CLK_IGNORE_UNUSED,
+ RK3562_PMU0_CLKGATE_CON(0), 0, GFLAGS),
+ GATE(PCLK_PMU0_PMU, "pclk_pmu0_pmu", "busclk_pdpmu0", CLK_IGNORE_UNUSED,
+ RK3562_PMU0_CLKGATE_CON(0), 1, GFLAGS),
+ GATE(CLK_PMU0_PMU, "clk_pmu0_pmu", "xin24m", CLK_IGNORE_UNUSED,
+ RK3562_PMU0_CLKGATE_CON(0), 2, GFLAGS),
+ GATE(PCLK_PMU0_HP_TIMER, "pclk_pmu0_hp_timer", "busclk_pdpmu0", CLK_IGNORE_UNUSED,
+ RK3562_PMU0_CLKGATE_CON(0), 3, GFLAGS),
+ GATE(CLK_PMU0_HP_TIMER, "clk_pmu0_hp_timer", "xin24m", CLK_IGNORE_UNUSED,
+ RK3562_PMU0_CLKGATE_CON(0), 4, GFLAGS),
+ GATE(CLK_PMU0_32K_HP_TIMER, "clk_pmu0_32k_hp_timer", "clk_rtc_32k", CLK_IGNORE_UNUSED,
+ RK3562_PMU0_CLKGATE_CON(0), 5, GFLAGS),
+ GATE(PCLK_PMU0_PVTM, "pclk_pmu0_pvtm", "busclk_pdpmu0", 0,
+ RK3562_PMU0_CLKGATE_CON(0), 6, GFLAGS),
+ GATE(CLK_PMU0_PVTM, "clk_pmu0_pvtm", "xin24m", 0,
+ RK3562_PMU0_CLKGATE_CON(0), 7, GFLAGS),
+ GATE(PCLK_IOC_PMUIO, "pclk_ioc_pmuio", "busclk_pdpmu0", CLK_IS_CRITICAL,
+ RK3562_PMU0_CLKGATE_CON(0), 8, GFLAGS),
+ GATE(PCLK_PMU0_GPIO0, "pclk_pmu0_gpio0", "busclk_pdpmu0", 0,
+ RK3562_PMU0_CLKGATE_CON(0), 9, GFLAGS),
+ GATE(DBCLK_PMU0_GPIO0, "dbclk_pmu0_gpio0", "xin24m", 0,
+ RK3562_PMU0_CLKGATE_CON(0), 10, GFLAGS),
+ GATE(PCLK_PMU0_GRF, "pclk_pmu0_grf", "busclk_pdpmu0", CLK_IGNORE_UNUSED,
+ RK3562_PMU0_CLKGATE_CON(0), 11, GFLAGS),
+ GATE(PCLK_PMU0_SGRF, "pclk_pmu0_sgrf", "busclk_pdpmu0", CLK_IGNORE_UNUSED,
+ RK3562_PMU0_CLKGATE_CON(0), 12, GFLAGS),
+ GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "xin24m", CLK_IGNORE_UNUSED,
+ RK3562_PMU0_CLKGATE_CON(1), 0, GFLAGS),
+ GATE(PCLK_PMU0_SCRKEYGEN, "pclk_pmu0_scrkeygen", "busclk_pdpmu0", CLK_IGNORE_UNUSED,
+ RK3562_PMU0_CLKGATE_CON(1), 1, GFLAGS),
+ COMPOSITE_NOMUX(CLK_PIPEPHY_DIV, "clk_pipephy_div", "cpll", 0,
+ RK3562_PMU0_CLKSEL_CON(2), 0, 6, DFLAGS,
+ RK3562_PMU0_CLKGATE_CON(2), 0, GFLAGS),
+ GATE(CLK_PIPEPHY_XIN24M, "clk_pipephy_xin24m", "xin24m", 0,
+ RK3562_PMU0_CLKGATE_CON(2), 1, GFLAGS),
+ COMPOSITE_NODIV(CLK_PIPEPHY_REF, "clk_pipephy_ref", clk_pipephy_ref_p, 0,
+ RK3562_PMU0_CLKSEL_CON(2), 7, 1, MFLAGS,
+ RK3562_PMU0_CLKGATE_CON(2), 2, GFLAGS),
+ GATE(CLK_USB2PHY_XIN24M, "clk_usb2phy_xin24m", "xin24m", 0,
+ RK3562_PMU0_CLKGATE_CON(2), 4, GFLAGS),
+ COMPOSITE_NODIV(CLK_USB2PHY_REF, "clk_usb2phy_ref", clk_usbphy_ref_p, 0,
+ RK3562_PMU0_CLKSEL_CON(2), 8, 1, MFLAGS,
+ RK3562_PMU0_CLKGATE_CON(2), 5, GFLAGS),
+ GATE(CLK_MIPIDSIPHY_XIN24M, "clk_mipidsiphy_xin24m", "xin24m", 0,
+ RK3562_PMU0_CLKGATE_CON(2), 6, GFLAGS),
+ COMPOSITE_NODIV(CLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", clk_mipidsi_ref_p, 0,
+ RK3562_PMU0_CLKSEL_CON(2), 15, 1, MFLAGS,
+ RK3562_PMU0_CLKGATE_CON(2), 7, GFLAGS),
+ GATE(PCLK_PMU0_I2C0, "pclk_pmu0_i2c0", "busclk_pdpmu0", 0,
+ RK3562_PMU0_CLKGATE_CON(2), 8, GFLAGS),
+ COMPOSITE(CLK_PMU0_I2C0, "clk_pmu0_i2c0", mux_200m_xin24m_32k_p, 0,
+ RK3562_PMU0_CLKSEL_CON(3), 14, 2, MFLAGS, 8, 5, DFLAGS,
+ RK3562_PMU0_CLKGATE_CON(2), 9, GFLAGS),
+ /* PD_PMU1 */
+ GATE(PCLK_PMU1_CRU, "pclk_pmu1_cru", "busclk_pdpmu0", CLK_IGNORE_UNUSED,
+ RK3562_PMU1_CLKGATE_CON(0), 0, GFLAGS),
+ GATE(HCLK_PMU1_MEM, "hclk_pmu1_mem", "busclk_pdpmu0", CLK_IGNORE_UNUSED,
+ RK3562_PMU1_CLKGATE_CON(0), 2, GFLAGS),
+ GATE(PCLK_PMU1_UART0, "pclk_pmu1_uart0", "busclk_pdpmu0", 0,
+ RK3562_PMU1_CLKGATE_CON(0), 7, GFLAGS),
+ COMPOSITE_NOMUX(CLK_PMU1_UART0_SRC, "clk_pmu1_uart0_src", "cpll", 0,
+ RK3562_PMU1_CLKSEL_CON(2), 0, 4, DFLAGS,
+ RK3562_PMU1_CLKGATE_CON(0), 8, GFLAGS),
+ COMPOSITE_FRACMUX(CLK_PMU1_UART0_FRAC, "clk_pmu1_uart0_frac", "clk_pmu1_uart0_src", CLK_SET_RATE_PARENT,
+ RK3562_PMU1_CLKSEL_CON(3), 0,
+ RK3562_PMU1_CLKGATE_CON(0), 9, GFLAGS,
+ &rk3562_clk_pmu1_uart0_fracmux),
+ GATE(SCLK_PMU1_UART0, "sclk_pmu1_uart0", "clk_pmu1_uart0", 0,
+ RK3562_PMU1_CLKGATE_CON(0), 10, GFLAGS),
+ GATE(PCLK_PMU1_SPI0, "pclk_pmu1_spi0", "busclk_pdpmu0", 0,
+ RK3562_PMU1_CLKGATE_CON(1), 0, GFLAGS),
+ COMPOSITE(CLK_PMU1_SPI0, "clk_pmu1_spi0", mux_200m_xin24m_32k_p, 0,
+ RK3562_PMU1_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 2, DFLAGS,
+ RK3562_PMU1_CLKGATE_CON(1), 1, GFLAGS),
+ GATE(SCLK_IN_PMU1_SPI0, "sclk_in_pmu1_spi0", "sclk_in_pmu1_spi0_io", 0,
+ RK3562_PMU1_CLKGATE_CON(1), 2, GFLAGS),
+ GATE(PCLK_PMU1_PWM0, "pclk_pmu1_pwm0", "busclk_pdpmu0", 0,
+ RK3562_PMU1_CLKGATE_CON(1), 3, GFLAGS),
+ COMPOSITE(CLK_PMU1_PWM0, "clk_pmu1_pwm0", mux_200m_xin24m_32k_p, 0,
+ RK3562_PMU1_CLKSEL_CON(4), 14, 2, MFLAGS, 8, 2, DFLAGS,
+ RK3562_PMU1_CLKGATE_CON(1), 4, GFLAGS),
+ GATE(CLK_CAPTURE_PMU1_PWM0, "clk_capture_pmu1_pwm0", "xin24m", 0,
+ RK3562_PMU1_CLKGATE_CON(1), 5, GFLAGS),
+ GATE(CLK_PMU1_WIFI, "clk_pmu1_wifi", "xin24m", 0,
+ RK3562_PMU1_CLKGATE_CON(1), 6, GFLAGS),
+ GATE(FCLK_PMU1_CM0_CORE, "fclk_pmu1_cm0_core", "busclk_pdpmu0", 0,
+ RK3562_PMU1_CLKGATE_CON(2), 0, GFLAGS),
+ GATE(CLK_PMU1_CM0_RTC, "clk_pmu1_cm0_rtc", "clk_rtc_32k", 0,
+ RK3562_PMU1_CLKGATE_CON(2), 1, GFLAGS),
+ GATE(PCLK_PMU1_WDTNS, "pclk_pmu1_wdtns", "busclk_pdpmu0", 0,
+ RK3562_PMU1_CLKGATE_CON(2), 3, GFLAGS),
+ GATE(CLK_PMU1_WDTNS, "clk_pmu1_wdtns", "xin24m", 0,
+ RK3562_PMU1_CLKGATE_CON(2), 4, GFLAGS),
+ GATE(PCLK_PMU1_MAILBOX, "pclk_pmu1_mailbox", "busclk_pdpmu0", 0,
+ RK3562_PMU1_CLKGATE_CON(3), 8, GFLAGS),
+
+ /* PD_RGA */
+ COMPOSITE(ACLK_RGA_PRE, "aclk_rga_pre", gpll_cpll_pvtpll_dmyapll_p, 0,
+ RK3562_CLKSEL_CON(32), 6, 2, MFLAGS, 0, 4, DFLAGS,
+ RK3562_CLKGATE_CON(14), 0, GFLAGS),
+ COMPOSITE_NOMUX(HCLK_RGA_PRE, "hclk_rga_pre", "aclk_rga_jdec", 0,
+ RK3562_CLKSEL_CON(32), 8, 3, DFLAGS,
+ RK3562_CLKGATE_CON(14), 1, GFLAGS),
+ GATE(ACLK_RGA, "aclk_rga", "aclk_rga_jdec", 0,
+ RK3562_CLKGATE_CON(14), 6, GFLAGS),
+ GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0,
+ RK3562_CLKGATE_CON(14), 7, GFLAGS),
+ COMPOSITE(CLK_RGA_CORE, "clk_rga_core", gpll_cpll_pvtpll_dmyapll_p, 0,
+ RK3562_CLKSEL_CON(33), 6, 2, MFLAGS, 0, 4, DFLAGS,
+ RK3562_CLKGATE_CON(14), 8, GFLAGS),
+ GATE(ACLK_JDEC, "aclk_jdec", "aclk_rga_jdec", 0,
+ RK3562_CLKGATE_CON(14), 9, GFLAGS),
+ GATE(HCLK_JDEC, "hclk_jdec", "hclk_rga_pre", 0,
+ RK3562_CLKGATE_CON(14), 10, GFLAGS),
+
+ /* PD_VDPU */
+ COMPOSITE(ACLK_VDPU_PRE, "aclk_vdpu_pre", gpll_cpll_pvtpll_dmyapll_p, 0,
+ RK3562_CLKSEL_CON(22), 6, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3562_CLKGATE_CON(10), 0, GFLAGS),
+ COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", gpll_cpll_pvtpll_dmyapll_p, 0,
+ RK3562_CLKSEL_CON(23), 14, 2, MFLAGS, 8, 5, DFLAGS,
+ RK3562_CLKGATE_CON(10), 3, GFLAGS),
+ COMPOSITE_NOMUX(HCLK_VDPU_PRE, "hclk_vdpu_pre", "aclk_vdpu", 0,
+ RK3562_CLKSEL_CON(24), 0, 4, DFLAGS,
+ RK3562_CLKGATE_CON(10), 4, GFLAGS),
+ GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_vdpu", 0,
+ RK3562_CLKGATE_CON(10), 7, GFLAGS),
+ GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_vdpu_pre", 0,
+ RK3562_CLKGATE_CON(10), 8, GFLAGS),
+
+ /* PD_VEPU */
+ COMPOSITE(CLK_RKVENC_CORE, "clk_rkvenc_core", gpll_cpll_pvtpll_dmyapll_p, 0,
+ RK3562_CLKSEL_CON(20), 6, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3562_CLKGATE_CON(9), 0, GFLAGS),
+ COMPOSITE(ACLK_VEPU_PRE, "aclk_vepu_pre", gpll_cpll_pvtpll_dmyapll_p, 0,
+ RK3562_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS,
+ RK3562_CLKGATE_CON(9), 1, GFLAGS),
+ COMPOSITE_NOMUX(HCLK_VEPU_PRE, "hclk_vepu_pre", "aclk_vepu", 0,
+ RK3562_CLKSEL_CON(21), 0, 4, DFLAGS,
+ RK3562_CLKGATE_CON(9), 2, GFLAGS),
+ GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_vepu", 0,
+ RK3562_CLKGATE_CON(9), 5, GFLAGS),
+ GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_vepu", 0,
+ RK3562_CLKGATE_CON(9), 6, GFLAGS),
+
+ /* PD_VI */
+ COMPOSITE(ACLK_VI, "aclk_vi", gpll_cpll_pvtpll_dmyapll_p, 0,
+ RK3562_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 4, DFLAGS,
+ RK3562_CLKGATE_CON(11), 0, GFLAGS),
+ COMPOSITE_NOMUX(HCLK_VI, "hclk_vi", "aclk_vi_isp", 0,
+ RK3562_CLKSEL_CON(26), 0, 4, DFLAGS,
+ RK3562_CLKGATE_CON(11), 1, GFLAGS),
+ COMPOSITE_NOMUX(PCLK_VI, "pclk_vi", "aclk_vi_isp", 0,
+ RK3562_CLKSEL_CON(26), 8, 4, DFLAGS,
+ RK3562_CLKGATE_CON(11), 2, GFLAGS),
+ GATE(ACLK_ISP, "aclk_isp", "aclk_vi_isp", 0,
+ RK3562_CLKGATE_CON(11), 6, GFLAGS),
+ GATE(HCLK_ISP, "hclk_isp", "hclk_vi", 0,
+ RK3562_CLKGATE_CON(11), 7, GFLAGS),
+ COMPOSITE(CLK_ISP, "clk_isp", gpll_cpll_pvtpll_dmyapll_p, 0,
+ RK3562_CLKSEL_CON(27), 6, 2, MFLAGS, 0, 4, DFLAGS,
+ RK3562_CLKGATE_CON(11), 8, GFLAGS),
+ GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_isp", 0,
+ RK3562_CLKGATE_CON(11), 9, GFLAGS),
+ GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi", 0,
+ RK3562_CLKGATE_CON(11), 10, GFLAGS),
+ COMPOSITE(DCLK_VICAP, "dclk_vicap", gpll_cpll_pvtpll_dmyapll_p, 0,
+ RK3562_CLKSEL_CON(27), 14, 2, MFLAGS, 8, 4, DFLAGS,
+ RK3562_CLKGATE_CON(11), 11, GFLAGS),
+ GATE(CSIRX0_CLK_DATA, "csirx0_clk_data", "csirx0_clk_data_io", 0,
+ RK3562_CLKGATE_CON(11), 12, GFLAGS),
+ GATE(CSIRX1_CLK_DATA, "csirx1_clk_data", "csirx1_clk_data_io", 0,
+ RK3562_CLKGATE_CON(11), 13, GFLAGS),
+ GATE(CSIRX2_CLK_DATA, "csirx2_clk_data", "csirx2_clk_data_io", 0,
+ RK3562_CLKGATE_CON(11), 14, GFLAGS),
+ GATE(CSIRX3_CLK_DATA, "csirx3_clk_data", "csirx3_clk_data_io", 0,
+ RK3562_CLKGATE_CON(11), 15, GFLAGS),
+ GATE(PCLK_CSIHOST0, "pclk_csihost0", "pclk_vi", 0,
+ RK3562_CLKGATE_CON(12), 0, GFLAGS),
+ GATE(PCLK_CSIHOST1, "pclk_csihost1", "pclk_vi", 0,
+ RK3562_CLKGATE_CON(12), 1, GFLAGS),
+ GATE(PCLK_CSIHOST2, "pclk_csihost2", "pclk_vi", 0,
+ RK3562_CLKGATE_CON(12), 2, GFLAGS),
+ GATE(PCLK_CSIHOST3, "pclk_csihost3", "pclk_vi", 0,
+ RK3562_CLKGATE_CON(12), 3, GFLAGS),
+ GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_vi", 0,
+ RK3562_CLKGATE_CON(12), 4, GFLAGS),
+ GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_vi", 0,
+ RK3562_CLKGATE_CON(12), 5, GFLAGS),
+
+ /* PD_VO */
+ COMPOSITE(ACLK_VO_PRE, "aclk_vo_pre", gpll_cpll_vpll_dmyhpll_p, 0,
+ RK3562_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3562_CLKGATE_CON(13), 0, GFLAGS),
+ COMPOSITE_NOMUX(HCLK_VO_PRE, "hclk_vo_pre", "aclk_vo", 0,
+ RK3562_CLKSEL_CON(29), 0, 5, DFLAGS,
+ RK3562_CLKGATE_CON(13), 1, GFLAGS),
+ GATE(ACLK_VOP, "aclk_vop", "aclk_vo", 0,
+ RK3562_CLKGATE_CON(13), 6, GFLAGS),
+ GATE(HCLK_VOP, "hclk_vop", "hclk_vo_pre", 0,
+ RK3562_CLKGATE_CON(13), 7, GFLAGS),
+ COMPOSITE(DCLK_VOP, "dclk_vop", gpll_dmyhpll_vpll_apll_p, CLK_SET_RATE_NO_REPARENT,
+ RK3562_CLKSEL_CON(30), 14, 2, MFLAGS, 0, 8, DFLAGS,
+ RK3562_CLKGATE_CON(13), 8, GFLAGS),
+ COMPOSITE(DCLK_VOP1, "dclk_vop1", gpll_dmyhpll_vpll_apll_p, CLK_SET_RATE_NO_REPARENT,
+ RK3562_CLKSEL_CON(31), 14, 2, MFLAGS, 0, 8, DFLAGS,
+ RK3562_CLKGATE_CON(13), 9, GFLAGS),
+};
+
+static void __init rk3562_clk_init(struct device_node *np)
+{
+ struct rockchip_clk_provider *ctx;
+ unsigned long clk_nr_clks;
+ void __iomem *reg_base;
+
+ clk_nr_clks = rockchip_clk_find_max_clk_id(rk3562_clk_branches,
+ ARRAY_SIZE(rk3562_clk_branches)) + 1;
+
+ reg_base = of_iomap(np, 0);
+ if (!reg_base) {
+ pr_err("%s: could not map cru region\n", __func__);
+ return;
+ }
+
+ ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
+ if (IS_ERR(ctx)) {
+ pr_err("%s: rockchip clk init failed\n", __func__);
+ iounmap(reg_base);
+ return;
+ }
+
+ rockchip_clk_register_plls(ctx, rk3562_pll_clks,
+ ARRAY_SIZE(rk3562_pll_clks),
+ RK3562_GRF_SOC_STATUS0);
+
+ rockchip_clk_register_branches(ctx, rk3562_clk_branches,
+ ARRAY_SIZE(rk3562_clk_branches));
+
+ rk3562_rst_init(np, reg_base);
+
+ rockchip_register_restart_notifier(ctx, RK3562_GLB_SRST_FST, NULL);
+
+ rockchip_clk_of_add_provider(np, ctx);
+}
+
+CLK_OF_DECLARE(rk3562_cru, "rockchip,rk3562-cru", rk3562_clk_init);
+
+struct clk_rk3562_inits {
+ void (*inits)(struct device_node *np);
+};
+
+static const struct clk_rk3562_inits clk_rk3562_cru_init = {
+ .inits = rk3562_clk_init,
+};
+
+static const struct of_device_id clk_rk3562_match_table[] = {
+ {
+ .compatible = "rockchip,rk3562-cru",
+ .data = &clk_rk3562_cru_init,
+ },
+ { }
+};
+
+static int clk_rk3562_probe(struct platform_device *pdev)
+{
+ const struct clk_rk3562_inits *init_data;
+ struct device *dev = &pdev->dev;
+
+ init_data = device_get_match_data(dev);
+ if (!init_data)
+ return -EINVAL;
+
+ if (init_data->inits)
+ init_data->inits(dev->of_node);
+
+ return 0;
+}
+
+static struct platform_driver clk_rk3562_driver = {
+ .probe = clk_rk3562_probe,
+ .driver = {
+ .name = "clk-rk3562",
+ .of_match_table = clk_rk3562_match_table,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver_probe(clk_rk3562_driver, clk_rk3562_probe);
diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index 53d10b1c627b..7d9279291e76 100644
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -1602,6 +1602,7 @@ static const char *const rk3568_cru_critical_clocks[] __initconst = {
"pclk_php",
"hclk_usb",
"pclk_usb",
+ "hclk_vi",
"hclk_vo",
};
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 9b37d44b9e5d..df2b2d706450 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -207,6 +207,65 @@ struct clk;
#define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
#define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
+#define RK3528_PMU_CRU_BASE 0x10000
+#define RK3528_PCIE_CRU_BASE 0x20000
+#define RK3528_DDRPHY_CRU_BASE 0x28000
+#define RK3528_PLL_CON(x) RK2928_PLL_CON(x)
+#define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE)
+#define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE)
+#define RK3528_MODE_CON 0x280
+#define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
+#define RK3528_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
+#define RK3528_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
+#define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE)
+#define RK3528_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PMU_CRU_BASE)
+#define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)
+#define RK3528_PCIE_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PCIE_CRU_BASE)
+#define RK3528_DDRPHY_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_DDRPHY_CRU_BASE)
+#define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE)
+#define RK3528_GLB_CNT_TH 0xc00
+#define RK3528_GLB_SRST_FST 0xc08
+#define RK3528_GLB_SRST_SND 0xc0c
+
+#define RK3562_PMU0_CRU_BASE 0x10000
+#define RK3562_PMU1_CRU_BASE 0x18000
+#define RK3562_DDR_CRU_BASE 0x20000
+#define RK3562_SUBDDR_CRU_BASE 0x28000
+#define RK3562_PERI_CRU_BASE 0x30000
+
+#define RK3562_PLL_CON(x) RK2928_PLL_CON(x)
+#define RK3562_PMU1_PLL_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x40)
+#define RK3562_SUBDDR_PLL_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x20)
+#define RK3562_MODE_CON 0x600
+#define RK3562_PMU1_MODE_CON (RK3562_PMU1_CRU_BASE + 0x380)
+#define RK3562_SUBDDR_MODE_CON (RK3562_SUBDDR_CRU_BASE + 0x380)
+#define RK3562_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
+#define RK3562_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
+#define RK3562_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
+#define RK3562_DDR_CLKSEL_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x100)
+#define RK3562_DDR_CLKGATE_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x180)
+#define RK3562_DDR_SOFTRST_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x200)
+#define RK3562_SUBDDR_CLKSEL_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x100)
+#define RK3562_SUBDDR_CLKGATE_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x180)
+#define RK3562_SUBDDR_SOFTRST_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x200)
+#define RK3562_PERI_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x100)
+#define RK3562_PERI_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x300)
+#define RK3562_PERI_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x400)
+#define RK3562_PMU0_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x100)
+#define RK3562_PMU0_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x180)
+#define RK3562_PMU0_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x200)
+#define RK3562_PMU1_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x100)
+#define RK3562_PMU1_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x180)
+#define RK3562_PMU1_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x200)
+#define RK3562_GLB_SRST_FST 0x614
+#define RK3562_GLB_SRST_SND 0x618
+#define RK3562_GLB_RST_CON 0x61c
+#define RK3562_GLB_RST_ST 0x620
+#define RK3562_SDMMC0_CON0 0x624
+#define RK3562_SDMMC0_CON1 0x628
+#define RK3562_SDMMC1_CON0 0x62c
+#define RK3562_SDMMC1_CON1 0x630
+
#define RK3568_PLL_CON(x) RK2928_PLL_CON(x)
#define RK3568_MODE_CON0 0xc0
#define RK3568_MISC_CON0 0xc4
@@ -444,6 +503,7 @@ struct rockchip_pll_rate_table {
* Flags:
* ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
* rate_table parameters and ajust them if necessary.
+ * ROCKCHIP_PLL_FIXED_MODE - the pll operates in normal mode only
*/
struct rockchip_pll_clock {
unsigned int id;
@@ -461,6 +521,7 @@ struct rockchip_pll_clock {
};
#define ROCKCHIP_PLL_SYNC_RATE BIT(0)
+#define ROCKCHIP_PLL_FIXED_MODE BIT(1)
#define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
_lshift, _pflags, _rtable) \
@@ -1118,6 +1179,8 @@ static inline void rockchip_register_softrst(struct device_node *np,
return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags);
}
+void rk3528_rst_init(struct device_node *np, void __iomem *reg_base);
+void rk3562_rst_init(struct device_node *np, void __iomem *reg_base);
void rk3576_rst_init(struct device_node *np, void __iomem *reg_base);
void rk3588_rst_init(struct device_node *np, void __iomem *reg_base);
diff --git a/drivers/clk/rockchip/rst-rk3528.c b/drivers/clk/rockchip/rst-rk3528.c
new file mode 100644
index 000000000000..b24f2c367929
--- /dev/null
+++ b/drivers/clk/rockchip/rst-rk3528.c
@@ -0,0 +1,306 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ * Based on Sebastian Reichel's implementation for RK3588
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <dt-bindings/reset/rockchip,rk3528-cru.h>
+#include "clk.h"
+
+/* 0xFF4A0000 + 0x0A00 */
+#define RK3528_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
+
+/* mapping table for reset ID to register offset */
+static const int rk3528_register_offset[] = {
+ /* CRU_SOFTRST_CON03 */
+ RK3528_CRU_RESET_OFFSET(SRST_CORE0_PO, 3, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE1_PO, 3, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE2_PO, 3, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE3_PO, 3, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE0, 3, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE1, 3, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE2, 3, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE3, 3, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_NL2, 3, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE_BIU, 3, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE_CRYPTO, 3, 10),
+
+ /* CRU_SOFTRST_CON05 */
+ RK3528_CRU_RESET_OFFSET(SRST_P_DBG, 5, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_POT_DBG, 5, 14),
+ RK3528_CRU_RESET_OFFSET(SRST_NT_DBG, 5, 15),
+
+ /* CRU_SOFTRST_CON06 */
+ RK3528_CRU_RESET_OFFSET(SRST_P_CORE_GRF, 6, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_P_DAPLITE_BIU, 6, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_P_CPU_BIU, 6, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 6, 7),
+
+ /* CRU_SOFTRST_CON08 */
+ RK3528_CRU_RESET_OFFSET(SRST_A_BUS_VOPGL_BIU, 8, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_A_BUS_H_BIU, 8, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_A_SYSMEM_BIU, 8, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 8, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 8, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 8, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_P_DFT2APB, 8, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_P_BUS_GRF, 8, 15),
+
+ /* CRU_SOFTRST_CON09 */
+ RK3528_CRU_RESET_OFFSET(SRST_A_BUS_M_BIU, 9, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_A_GIC, 9, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 9, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_A_DMAC, 9, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_P_TIMER, 9, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_TIMER0, 9, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_TIMER1, 9, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_TIMER2, 9, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_TIMER3, 9, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_TIMER4, 9, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_TIMER5, 9, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_P_JDBCK_DAP, 9, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_JDBCK_DAP, 9, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_P_WDT_NS, 9, 15),
+
+ /* CRU_SOFTRST_CON10 */
+ RK3528_CRU_RESET_OFFSET(SRST_T_WDT_NS, 10, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_H_TRNG_NS, 10, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_P_UART0, 10, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_S_UART0, 10, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_PKA_CRYPTO, 10, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_A_CRYPTO, 10, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_H_CRYPTO, 10, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 10, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 10, 14),
+
+ /* CRU_SOFTRST_CON11 */
+ RK3528_CRU_RESET_OFFSET(SRST_P_PWM0, 11, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_PWM0, 11, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_P_PWM1, 11, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_PWM1, 11, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_P_SCR, 11, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_A_DCF, 11, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_P_INTMUX, 11, 12),
+
+ /* CRU_SOFTRST_CON25 */
+ RK3528_CRU_RESET_OFFSET(SRST_A_VPU_BIU, 25, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_H_VPU_BIU, 25, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_P_VPU_BIU, 25, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_A_VPU, 25, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_H_VPU, 25, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_P_CRU_PCIE, 25, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_P_VPU_GRF, 25, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_H_SFC, 25, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_S_SFC, 25, 14),
+ RK3528_CRU_RESET_OFFSET(SRST_C_EMMC, 25, 15),
+
+ /* CRU_SOFTRST_CON26 */
+ RK3528_CRU_RESET_OFFSET(SRST_H_EMMC, 26, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_A_EMMC, 26, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_B_EMMC, 26, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_T_EMMC, 26, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_P_GPIO1, 26, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO1, 26, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_A_VPU_L_BIU, 26, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_P_VPU_IOC, 26, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S0, 26, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S0, 26, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S2, 26, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S2, 26, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_P_ACODEC, 26, 13),
+
+ /* CRU_SOFTRST_CON27 */
+ RK3528_CRU_RESET_OFFSET(SRST_P_GPIO3, 27, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO3, 27, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_P_SPI1, 27, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_SPI1, 27, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_P_UART2, 27, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_S_UART2, 27, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_P_UART5, 27, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_S_UART5, 27, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_P_UART6, 27, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_S_UART6, 27, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_P_UART7, 27, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_S_UART7, 27, 14),
+ RK3528_CRU_RESET_OFFSET(SRST_P_I2C3, 27, 15),
+
+ /* CRU_SOFTRST_CON28 */
+ RK3528_CRU_RESET_OFFSET(SRST_I2C3, 28, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_P_I2C5, 28, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_I2C5, 28, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_P_I2C6, 28, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_I2C6, 28, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_A_MAC, 28, 5),
+
+ /* CRU_SOFTRST_CON30 */
+ RK3528_CRU_RESET_OFFSET(SRST_P_PCIE, 30, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_PCIE_PIPE_PHY, 30, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_PCIE_POWER_UP, 30, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_P_PCIE_PHY, 30, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_P_PIPE_GRF, 30, 7),
+
+ /* CRU_SOFTRST_CON32 */
+ RK3528_CRU_RESET_OFFSET(SRST_H_SDIO0, 32, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_H_SDIO1, 32, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_TS_0, 32, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_TS_1, 32, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_P_CAN2, 32, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_CAN2, 32, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_P_CAN3, 32, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_CAN3, 32, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_P_SARADC, 32, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_SARADC, 32, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_SARADC_PHY, 32, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_P_TSADC, 32, 14),
+ RK3528_CRU_RESET_OFFSET(SRST_TSADC, 32, 15),
+
+ /* CRU_SOFTRST_CON33 */
+ RK3528_CRU_RESET_OFFSET(SRST_A_USB3OTG, 33, 1),
+
+ /* CRU_SOFTRST_CON34 */
+ RK3528_CRU_RESET_OFFSET(SRST_A_GPU_BIU, 34, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 34, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_A_GPU, 34, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_GPU, 34, 9),
+
+ /* CRU_SOFTRST_CON36 */
+ RK3528_CRU_RESET_OFFSET(SRST_H_RKVENC_BIU, 36, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC_BIU, 36, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_BIU, 36, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_H_RKVENC, 36, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC, 36, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE_RKVENC, 36, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S1, 36, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S1, 36, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_P_I2C1, 36, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_I2C1, 36, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_P_I2C0, 36, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_I2C0, 36, 14),
+
+ /* CRU_SOFTRST_CON37 */
+ RK3528_CRU_RESET_OFFSET(SRST_P_SPI0, 37, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_SPI0, 37, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_P_GPIO4, 37, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO4, 37, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_IOC, 37, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_H_SPDIF, 37, 14),
+ RK3528_CRU_RESET_OFFSET(SRST_M_SPDIF, 37, 15),
+
+ /* CRU_SOFTRST_CON38 */
+ RK3528_CRU_RESET_OFFSET(SRST_H_PDM, 38, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_M_PDM, 38, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_P_UART1, 38, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_S_UART1, 38, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_P_UART3, 38, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_S_UART3, 38, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_GRF, 38, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_P_CAN0, 38, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_CAN0, 38, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_P_CAN1, 38, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_CAN1, 38, 10),
+
+ /* CRU_SOFTRST_CON39 */
+ RK3528_CRU_RESET_OFFSET(SRST_A_VO_BIU, 39, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_H_VO_BIU, 39, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_P_VO_BIU, 39, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_H_RGA2E, 39, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_A_RGA2E, 39, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE_RGA2E, 39, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_H_VDPP, 39, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_A_VDPP, 39, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_CORE_VDPP, 39, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_P_VO_GRF, 39, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_P_CRU, 39, 15),
+
+ /* CRU_SOFTRST_CON40 */
+ RK3528_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 40, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_H_VOP, 40, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_D_VOP0, 40, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_D_VOP1, 40, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_A_VOP, 40, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_P_HDMI, 40, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_HDMI, 40, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_P_HDMIPHY, 40, 14),
+ RK3528_CRU_RESET_OFFSET(SRST_H_HDCP_KEY, 40, 15),
+
+ /* CRU_SOFTRST_CON41 */
+ RK3528_CRU_RESET_OFFSET(SRST_A_HDCP, 41, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_H_HDCP, 41, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_P_HDCP, 41, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_H_CVBS, 41, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_D_CVBS_VOP, 41, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_D_4X_CVBS_VOP, 41, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER, 41, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_H_JPEG_DECODER, 41, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_A_VO_L_BIU, 41, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_A_MAC_VO, 41, 10),
+
+ /* CRU_SOFTRST_CON42 */
+ RK3528_CRU_RESET_OFFSET(SRST_A_JPEG_BIU, 42, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S3, 42, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S3, 42, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_MACPHY, 42, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_P_VCDCPHY, 42, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_P_GPIO2, 42, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO2, 42, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_P_VO_IOC, 42, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_H_SDMMC0, 42, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 42, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 42, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_USER_OTPC_NS, 42, 13),
+
+ /* CRU_SOFTRST_CON43 */
+ RK3528_CRU_RESET_OFFSET(SRST_HDMIHDP0, 43, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_H_USBHOST, 43, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_H_USBHOST_ARB, 43, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_HOST_UTMI, 43, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_P_UART4, 43, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_S_UART4, 43, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_P_I2C4, 43, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_I2C4, 43, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_P_I2C7, 43, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_I2C7, 43, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_P_USBPHY, 43, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_USBPHY_POR, 43, 14),
+ RK3528_CRU_RESET_OFFSET(SRST_USBPHY_OTG, 43, 15),
+
+ /* CRU_SOFTRST_CON44 */
+ RK3528_CRU_RESET_OFFSET(SRST_USBPHY_HOST, 44, 0),
+ RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY_CRU, 44, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC_BIU, 44, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC_BIU, 44, 7),
+ RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC, 44, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC, 44, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_HEVC_CA_RKVDEC, 44, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_RKVDEC, 44, 12),
+
+ /* CRU_SOFTRST_CON45 */
+ RK3528_CRU_RESET_OFFSET(SRST_P_DDR_BIU, 45, 1),
+ RK3528_CRU_RESET_OFFSET(SRST_P_DDRC, 45, 2),
+ RK3528_CRU_RESET_OFFSET(SRST_P_DDRMON, 45, 3),
+ RK3528_CRU_RESET_OFFSET(SRST_TIMER_DDRMON, 45, 4),
+ RK3528_CRU_RESET_OFFSET(SRST_P_MSCH_BIU, 45, 5),
+ RK3528_CRU_RESET_OFFSET(SRST_P_DDR_GRF, 45, 6),
+ RK3528_CRU_RESET_OFFSET(SRST_P_DDR_HWLP, 45, 8),
+ RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY, 45, 9),
+ RK3528_CRU_RESET_OFFSET(SRST_MSCH_BIU, 45, 10),
+ RK3528_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL, 45, 11),
+ RK3528_CRU_RESET_OFFSET(SRST_DDR_UPCTL, 45, 12),
+ RK3528_CRU_RESET_OFFSET(SRST_DDRMON, 45, 13),
+ RK3528_CRU_RESET_OFFSET(SRST_A_DDR_SCRAMBLE, 45, 14),
+ RK3528_CRU_RESET_OFFSET(SRST_A_SPLIT, 45, 15),
+
+ /* CRU_SOFTRST_CON46 */
+ RK3528_CRU_RESET_OFFSET(SRST_DDR_PHY, 46, 0),
+};
+
+void rk3528_rst_init(struct device_node *np, void __iomem *reg_base)
+{
+ rockchip_register_softrst_lut(np,
+ rk3528_register_offset,
+ ARRAY_SIZE(rk3528_register_offset),
+ reg_base + RK3528_SOFTRST_CON(0),
+ ROCKCHIP_SOFTRST_HIWORD_MASK);
+}
diff --git a/drivers/clk/rockchip/rst-rk3562.c b/drivers/clk/rockchip/rst-rk3562.c
new file mode 100644
index 000000000000..a3854eaef3be
--- /dev/null
+++ b/drivers/clk/rockchip/rst-rk3562.c
@@ -0,0 +1,429 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2024 Collabora Ltd.
+ * Author: Detlev Casanova <detlev.casanova@collabora.com>
+ * Based on Sebastien Reichel's implementation for RK3588
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <dt-bindings/reset/rockchip,rk3562-cru.h>
+#include "clk.h"
+
+/* 0xff100000 + 0x0A00 */
+#define RK3562_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
+/* 0xff110000 + 0x0A00 */
+#define RK3562_PMU0CRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit)
+/* 0xff118000 + 0x0A00 */
+#define RK3562_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x18000*4 + reg * 16 + bit)
+/* 0xff120000 + 0x0A00 */
+#define RK3562_DDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000*4 + reg * 16 + bit)
+/* 0xff128000 + 0x0A00 */
+#define RK3562_SUBDDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x28000*4 + reg * 16 + bit)
+/* 0xff130000 + 0x0A00 */
+#define RK3562_PERICRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000*4 + reg * 16 + bit)
+
+/* mapping table for reset ID to register offset */
+static const int rk3562_register_offset[] = {
+ /* SOFTRST_CON01 */
+ RK3562_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 0),
+ RK3562_CRU_RESET_OFFSET(SRST_A_TOP_VIO_BIU, 1, 1),
+ RK3562_CRU_RESET_OFFSET(SRST_REF_PVTPLL_LOGIC, 1, 2),
+
+ /* SOFTRST_CON03 */
+ RK3562_CRU_RESET_OFFSET(SRST_NCOREPORESET0, 3, 0),
+ RK3562_CRU_RESET_OFFSET(SRST_NCOREPORESET1, 3, 1),
+ RK3562_CRU_RESET_OFFSET(SRST_NCOREPORESET2, 3, 2),
+ RK3562_CRU_RESET_OFFSET(SRST_NCOREPORESET3, 3, 3),
+ RK3562_CRU_RESET_OFFSET(SRST_NCORESET0, 3, 4),
+ RK3562_CRU_RESET_OFFSET(SRST_NCORESET1, 3, 5),
+ RK3562_CRU_RESET_OFFSET(SRST_NCORESET2, 3, 6),
+ RK3562_CRU_RESET_OFFSET(SRST_NCORESET3, 3, 7),
+ RK3562_CRU_RESET_OFFSET(SRST_NL2RESET, 3, 8),
+
+ /* SOFTRST_CON04 */
+ RK3562_CRU_RESET_OFFSET(SRST_DAP, 4, 9),
+ RK3562_CRU_RESET_OFFSET(SRST_P_DBG_DAPLITE, 4, 10),
+ RK3562_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 4, 13),
+
+ /* SOFTRST_CON05 */
+ RK3562_CRU_RESET_OFFSET(SRST_A_CORE_BIU, 5, 0),
+ RK3562_CRU_RESET_OFFSET(SRST_P_CORE_BIU, 5, 1),
+ RK3562_CRU_RESET_OFFSET(SRST_H_CORE_BIU, 5, 2),
+
+ /* SOFTRST_CON06 */
+ RK3562_CRU_RESET_OFFSET(SRST_A_NPU_BIU, 6, 2),
+ RK3562_CRU_RESET_OFFSET(SRST_H_NPU_BIU, 6, 3),
+ RK3562_CRU_RESET_OFFSET(SRST_A_RKNN, 6, 4),
+ RK3562_CRU_RESET_OFFSET(SRST_H_RKNN, 6, 5),
+ RK3562_CRU_RESET_OFFSET(SRST_REF_PVTPLL_NPU, 6, 6),
+
+ /* SOFTRST_CON08 */
+ RK3562_CRU_RESET_OFFSET(SRST_A_GPU_BIU, 8, 3),
+ RK3562_CRU_RESET_OFFSET(SRST_GPU, 8, 4),
+ RK3562_CRU_RESET_OFFSET(SRST_REF_PVTPLL_GPU, 8, 5),
+ RK3562_CRU_RESET_OFFSET(SRST_GPU_BRG_BIU, 8, 8),
+
+ /* SOFTRST_CON09 */
+ RK3562_CRU_RESET_OFFSET(SRST_RKVENC_CORE, 9, 0),
+ RK3562_CRU_RESET_OFFSET(SRST_A_VEPU_BIU, 9, 3),
+ RK3562_CRU_RESET_OFFSET(SRST_H_VEPU_BIU, 9, 4),
+ RK3562_CRU_RESET_OFFSET(SRST_A_RKVENC, 9, 5),
+ RK3562_CRU_RESET_OFFSET(SRST_H_RKVENC, 9, 6),
+
+ /* SOFTRST_CON10 */
+ RK3562_CRU_RESET_OFFSET(SRST_RKVDEC_HEVC_CA, 10, 2),
+ RK3562_CRU_RESET_OFFSET(SRST_A_VDPU_BIU, 10, 5),
+ RK3562_CRU_RESET_OFFSET(SRST_H_VDPU_BIU, 10, 6),
+ RK3562_CRU_RESET_OFFSET(SRST_A_RKVDEC, 10, 7),
+ RK3562_CRU_RESET_OFFSET(SRST_H_RKVDEC, 10, 8),
+
+ /* SOFTRST_CON11 */
+ RK3562_CRU_RESET_OFFSET(SRST_A_VI_BIU, 11, 3),
+ RK3562_CRU_RESET_OFFSET(SRST_H_VI_BIU, 11, 4),
+ RK3562_CRU_RESET_OFFSET(SRST_P_VI_BIU, 11, 5),
+ RK3562_CRU_RESET_OFFSET(SRST_ISP, 11, 8),
+ RK3562_CRU_RESET_OFFSET(SRST_A_VICAP, 11, 9),
+ RK3562_CRU_RESET_OFFSET(SRST_H_VICAP, 11, 10),
+ RK3562_CRU_RESET_OFFSET(SRST_D_VICAP, 11, 11),
+ RK3562_CRU_RESET_OFFSET(SRST_I0_VICAP, 11, 12),
+ RK3562_CRU_RESET_OFFSET(SRST_I1_VICAP, 11, 13),
+ RK3562_CRU_RESET_OFFSET(SRST_I2_VICAP, 11, 14),
+ RK3562_CRU_RESET_OFFSET(SRST_I3_VICAP, 11, 15),
+
+ /* SOFTRST_CON12 */
+ RK3562_CRU_RESET_OFFSET(SRST_P_CSIHOST0, 12, 0),
+ RK3562_CRU_RESET_OFFSET(SRST_P_CSIHOST1, 12, 1),
+ RK3562_CRU_RESET_OFFSET(SRST_P_CSIHOST2, 12, 2),
+ RK3562_CRU_RESET_OFFSET(SRST_P_CSIHOST3, 12, 3),
+ RK3562_CRU_RESET_OFFSET(SRST_P_CSIPHY0, 12, 4),
+ RK3562_CRU_RESET_OFFSET(SRST_P_CSIPHY1, 12, 5),
+
+ /* SOFTRST_CON13 */
+ RK3562_CRU_RESET_OFFSET(SRST_A_VO_BIU, 13, 3),
+ RK3562_CRU_RESET_OFFSET(SRST_H_VO_BIU, 13, 4),
+ RK3562_CRU_RESET_OFFSET(SRST_A_VOP, 13, 6),
+ RK3562_CRU_RESET_OFFSET(SRST_H_VOP, 13, 7),
+ RK3562_CRU_RESET_OFFSET(SRST_D_VOP, 13, 8),
+ RK3562_CRU_RESET_OFFSET(SRST_D_VOP1, 13, 9),
+
+ /* SOFTRST_CON14 */
+ RK3562_CRU_RESET_OFFSET(SRST_A_RGA_BIU, 14, 3),
+ RK3562_CRU_RESET_OFFSET(SRST_H_RGA_BIU, 14, 4),
+ RK3562_CRU_RESET_OFFSET(SRST_A_RGA, 14, 6),
+ RK3562_CRU_RESET_OFFSET(SRST_H_RGA, 14, 7),
+ RK3562_CRU_RESET_OFFSET(SRST_RGA_CORE, 14, 8),
+ RK3562_CRU_RESET_OFFSET(SRST_A_JDEC, 14, 9),
+ RK3562_CRU_RESET_OFFSET(SRST_H_JDEC, 14, 10),
+
+ /* SOFTRST_CON15 */
+ RK3562_CRU_RESET_OFFSET(SRST_B_EBK_BIU, 15, 2),
+ RK3562_CRU_RESET_OFFSET(SRST_P_EBK_BIU, 15, 3),
+ RK3562_CRU_RESET_OFFSET(SRST_AHB2AXI_EBC, 15, 4),
+ RK3562_CRU_RESET_OFFSET(SRST_H_EBC, 15, 5),
+ RK3562_CRU_RESET_OFFSET(SRST_D_EBC, 15, 6),
+ RK3562_CRU_RESET_OFFSET(SRST_H_EINK, 15, 7),
+ RK3562_CRU_RESET_OFFSET(SRST_P_EINK, 15, 8),
+
+ /* SOFTRST_CON16 */
+ RK3562_CRU_RESET_OFFSET(SRST_P_PHP_BIU, 16, 2),
+ RK3562_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 16, 3),
+ RK3562_CRU_RESET_OFFSET(SRST_P_PCIE20, 16, 7),
+ RK3562_CRU_RESET_OFFSET(SRST_PCIE20_POWERUP, 16, 8),
+ RK3562_CRU_RESET_OFFSET(SRST_USB3OTG, 16, 10),
+
+ /* SOFTRST_CON17 */
+ RK3562_CRU_RESET_OFFSET(SRST_PIPEPHY, 17, 3),
+
+ /* SOFTRST_CON18 */
+ RK3562_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 18, 3),
+ RK3562_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 18, 4),
+ RK3562_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 18, 5),
+
+ /* SOFTRST_CON19 */
+ RK3562_CRU_RESET_OFFSET(SRST_P_I2C1, 19, 0),
+ RK3562_CRU_RESET_OFFSET(SRST_P_I2C2, 19, 1),
+ RK3562_CRU_RESET_OFFSET(SRST_P_I2C3, 19, 2),
+ RK3562_CRU_RESET_OFFSET(SRST_P_I2C4, 19, 3),
+ RK3562_CRU_RESET_OFFSET(SRST_P_I2C5, 19, 4),
+ RK3562_CRU_RESET_OFFSET(SRST_I2C1, 19, 6),
+ RK3562_CRU_RESET_OFFSET(SRST_I2C2, 19, 7),
+ RK3562_CRU_RESET_OFFSET(SRST_I2C3, 19, 8),
+ RK3562_CRU_RESET_OFFSET(SRST_I2C4, 19, 9),
+ RK3562_CRU_RESET_OFFSET(SRST_I2C5, 19, 10),
+
+ /* SOFTRST_CON20 */
+ RK3562_CRU_RESET_OFFSET(SRST_BUS_GPIO3, 20, 5),
+ RK3562_CRU_RESET_OFFSET(SRST_BUS_GPIO4, 20, 6),
+
+ /* SOFTRST_CON21 */
+ RK3562_CRU_RESET_OFFSET(SRST_P_TIMER, 21, 0),
+ RK3562_CRU_RESET_OFFSET(SRST_TIMER0, 21, 1),
+ RK3562_CRU_RESET_OFFSET(SRST_TIMER1, 21, 2),
+ RK3562_CRU_RESET_OFFSET(SRST_TIMER2, 21, 3),
+ RK3562_CRU_RESET_OFFSET(SRST_TIMER3, 21, 4),
+ RK3562_CRU_RESET_OFFSET(SRST_TIMER4, 21, 5),
+ RK3562_CRU_RESET_OFFSET(SRST_TIMER5, 21, 6),
+ RK3562_CRU_RESET_OFFSET(SRST_P_STIMER, 21, 7),
+ RK3562_CRU_RESET_OFFSET(SRST_STIMER0, 21, 8),
+ RK3562_CRU_RESET_OFFSET(SRST_STIMER1, 21, 9),
+
+ /* SOFTRST_CON22 */
+ RK3562_CRU_RESET_OFFSET(SRST_P_WDTNS, 22, 0),
+ RK3562_CRU_RESET_OFFSET(SRST_WDTNS, 22, 1),
+ RK3562_CRU_RESET_OFFSET(SRST_P_GRF, 22, 2),
+ RK3562_CRU_RESET_OFFSET(SRST_P_SGRF, 22, 3),
+ RK3562_CRU_RESET_OFFSET(SRST_P_MAILBOX, 22, 4),
+ RK3562_CRU_RESET_OFFSET(SRST_P_INTC, 22, 5),
+ RK3562_CRU_RESET_OFFSET(SRST_A_BUS_GIC400, 22, 6),
+ RK3562_CRU_RESET_OFFSET(SRST_A_BUS_GIC400_DEBUG, 22, 7),
+
+ /* SOFTRST_CON23 */
+ RK3562_CRU_RESET_OFFSET(SRST_A_BUS_SPINLOCK, 23, 0),
+ RK3562_CRU_RESET_OFFSET(SRST_A_DCF, 23, 1),
+ RK3562_CRU_RESET_OFFSET(SRST_P_DCF, 23, 2),
+ RK3562_CRU_RESET_OFFSET(SRST_F_BUS_CM0_CORE, 23, 3),
+ RK3562_CRU_RESET_OFFSET(SRST_T_BUS_CM0_JTAG, 23, 5),
+ RK3562_CRU_RESET_OFFSET(SRST_H_ICACHE, 23, 8),
+ RK3562_CRU_RESET_OFFSET(SRST_H_DCACHE, 23, 9),
+
+ /* SOFTRST_CON24 */
+ RK3562_CRU_RESET_OFFSET(SRST_P_TSADC, 24, 0),
+ RK3562_CRU_RESET_OFFSET(SRST_TSADC, 24, 1),
+ RK3562_CRU_RESET_OFFSET(SRST_TSADCPHY, 24, 2),
+ RK3562_CRU_RESET_OFFSET(SRST_P_DFT2APB, 24, 4),
+
+ /* SOFTRST_CON25 */
+ RK3562_CRU_RESET_OFFSET(SRST_A_GMAC, 25, 0),
+ RK3562_CRU_RESET_OFFSET(SRST_P_APB2ASB_VCCIO156, 25, 1),
+ RK3562_CRU_RESET_OFFSET(SRST_P_DSIPHY, 25, 5),
+ RK3562_CRU_RESET_OFFSET(SRST_P_DSITX, 25, 8),
+ RK3562_CRU_RESET_OFFSET(SRST_P_CPU_EMA_DET, 25, 9),
+ RK3562_CRU_RESET_OFFSET(SRST_P_HASH, 25, 10),
+ RK3562_CRU_RESET_OFFSET(SRST_P_TOPCRU, 25, 11),
+
+ /* SOFTRST_CON26 */
+ RK3562_CRU_RESET_OFFSET(SRST_P_ASB2APB_VCCIO156, 26, 0),
+ RK3562_CRU_RESET_OFFSET(SRST_P_IOC_VCCIO156, 26, 1),
+ RK3562_CRU_RESET_OFFSET(SRST_P_GPIO3_VCCIO156, 26, 2),
+ RK3562_CRU_RESET_OFFSET(SRST_P_GPIO4_VCCIO156, 26, 3),
+ RK3562_CRU_RESET_OFFSET(SRST_P_SARADC_VCCIO156, 26, 4),
+ RK3562_CRU_RESET_OFFSET(SRST_SARADC_VCCIO156, 26, 5),
+ RK3562_CRU_RESET_OFFSET(SRST_SARADC_VCCIO156_PHY, 26, 6),
+
+ /* SOFTRST_CON27 */
+ RK3562_CRU_RESET_OFFSET(SRST_A_MAC100, 27, 1),
+
+ /* PMU0_SOFTRST_CON00 */
+ RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_CRU, 0, 0),
+ RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_PMU, 0, 1),
+ RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_PMU, 0, 2),
+ RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_HP_TIMER, 0, 3),
+ RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_HP_TIMER, 0, 4),
+ RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_32K_HP_TIMER, 0, 5),
+ RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_PVTM, 0, 6),
+ RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_PVTM, 0, 7),
+ RK3562_PMU0CRU_RESET_OFFSET(SRST_P_IOC_PMUIO, 0, 8),
+ RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_GPIO0, 0, 9),
+ RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_GPIO0, 0, 10),
+ RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_GRF, 0, 11),
+ RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_SGRF, 0, 12),
+
+ /* PMU0_SOFTRST_CON01 */
+ RK3562_PMU0CRU_RESET_OFFSET(SRST_DDR_FAIL_SAFE, 1, 0),
+ RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_SCRKEYGEN, 1, 1),
+
+ /* PMU0_SOFTRST_CON02 */
+ RK3562_PMU0CRU_RESET_OFFSET(SRST_P_PMU0_I2C0, 2, 8),
+ RK3562_PMU0CRU_RESET_OFFSET(SRST_PMU0_I2C0, 2, 9),
+
+ /* PMU1_SOFTRST_CON00 */
+ RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_CRU, 0, 0),
+ RK3562_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_MEM, 0, 2),
+ RK3562_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 0, 3),
+ RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_BIU, 0, 4),
+ RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_UART0, 0, 7),
+ RK3562_PMU1CRU_RESET_OFFSET(SRST_S_PMU1_UART0, 0, 10),
+
+ /* PMU1_SOFTRST_CON01 */
+ RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_SPI0, 1, 0),
+ RK3562_PMU1CRU_RESET_OFFSET(SRST_PMU1_SPI0, 1, 1),
+ RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_PWM0, 1, 3),
+ RK3562_PMU1CRU_RESET_OFFSET(SRST_PMU1_PWM0, 1, 4),
+
+ /* PMU1_SOFTRST_CON02 */
+ RK3562_PMU1CRU_RESET_OFFSET(SRST_F_PMU1_CM0_CORE, 2, 0),
+ RK3562_PMU1CRU_RESET_OFFSET(SRST_T_PMU1_CM0_JTAG, 2, 2),
+ RK3562_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_WDTNS, 2, 3),
+ RK3562_PMU1CRU_RESET_OFFSET(SRST_PMU1_WDTNS, 2, 4),
+ RK3562_PMU1CRU_RESET_OFFSET(SRST_PMU1_MAILBOX, 2, 8),
+
+ /* DDR_SOFTRST_CON00 */
+ RK3562_DDRCRU_RESET_OFFSET(SRST_MSCH_BRG_BIU, 0, 4),
+ RK3562_DDRCRU_RESET_OFFSET(SRST_P_MSCH_BIU, 0, 5),
+ RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_HWLP, 0, 6),
+ RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_PHY, 0, 8),
+ RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_DFICTL, 0, 9),
+ RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_DMA2DDR, 0, 10),
+
+ /* DDR_SOFTRST_CON01 */
+ RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_MON, 1, 0),
+ RK3562_DDRCRU_RESET_OFFSET(SRST_TM_DDR_MON, 1, 1),
+ RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_GRF, 1, 2),
+ RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_CRU, 1, 3),
+ RK3562_DDRCRU_RESET_OFFSET(SRST_P_SUBDDR_CRU, 1, 4),
+
+ /* SUBDDR_SOFTRST_CON00 */
+ RK3562_SUBDDRCRU_RESET_OFFSET(SRST_MSCH_BIU, 0, 1),
+ RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_PHY, 0, 4),
+ RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_DFICTL, 0, 5),
+ RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_SCRAMBLE, 0, 6),
+ RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_MON, 0, 7),
+ RK3562_SUBDDRCRU_RESET_OFFSET(SRST_A_DDR_SPLIT, 0, 8),
+ RK3562_SUBDDRCRU_RESET_OFFSET(SRST_DDR_DMA2DDR, 0, 9),
+
+ /* PERI_SOFTRST_CON01 */
+ RK3562_PERICRU_RESET_OFFSET(SRST_A_PERI_BIU, 1, 3),
+ RK3562_PERICRU_RESET_OFFSET(SRST_H_PERI_BIU, 1, 4),
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_PERI_BIU, 1, 5),
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_PERICRU, 1, 6),
+
+ /* PERI_SOFTRST_CON02 */
+ RK3562_PERICRU_RESET_OFFSET(SRST_H_SAI0_8CH, 2, 0),
+ RK3562_PERICRU_RESET_OFFSET(SRST_M_SAI0_8CH, 2, 3),
+ RK3562_PERICRU_RESET_OFFSET(SRST_H_SAI1_8CH, 2, 5),
+ RK3562_PERICRU_RESET_OFFSET(SRST_M_SAI1_8CH, 2, 8),
+ RK3562_PERICRU_RESET_OFFSET(SRST_H_SAI2_2CH, 2, 10),
+ RK3562_PERICRU_RESET_OFFSET(SRST_M_SAI2_2CH, 2, 13),
+
+ /* PERI_SOFTRST_CON03 */
+ RK3562_PERICRU_RESET_OFFSET(SRST_H_DSM, 3, 1),
+ RK3562_PERICRU_RESET_OFFSET(SRST_DSM, 3, 2),
+ RK3562_PERICRU_RESET_OFFSET(SRST_H_PDM, 3, 4),
+ RK3562_PERICRU_RESET_OFFSET(SRST_M_PDM, 3, 5),
+ RK3562_PERICRU_RESET_OFFSET(SRST_H_SPDIF, 3, 8),
+ RK3562_PERICRU_RESET_OFFSET(SRST_M_SPDIF, 3, 11),
+
+ /* PERI_SOFTRST_CON04 */
+ RK3562_PERICRU_RESET_OFFSET(SRST_H_SDMMC0, 4, 0),
+ RK3562_PERICRU_RESET_OFFSET(SRST_H_SDMMC1, 4, 2),
+ RK3562_PERICRU_RESET_OFFSET(SRST_H_EMMC, 4, 8),
+ RK3562_PERICRU_RESET_OFFSET(SRST_A_EMMC, 4, 9),
+ RK3562_PERICRU_RESET_OFFSET(SRST_C_EMMC, 4, 10),
+ RK3562_PERICRU_RESET_OFFSET(SRST_B_EMMC, 4, 11),
+ RK3562_PERICRU_RESET_OFFSET(SRST_T_EMMC, 4, 12),
+ RK3562_PERICRU_RESET_OFFSET(SRST_S_SFC, 4, 13),
+ RK3562_PERICRU_RESET_OFFSET(SRST_H_SFC, 4, 14),
+
+ /* PERI_SOFTRST_CON05 */
+ RK3562_PERICRU_RESET_OFFSET(SRST_H_USB2HOST, 5, 0),
+ RK3562_PERICRU_RESET_OFFSET(SRST_H_USB2HOST_ARB, 5, 1),
+ RK3562_PERICRU_RESET_OFFSET(SRST_USB2HOST_UTMI, 5, 2),
+
+ /* PERI_SOFTRST_CON06 */
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_SPI1, 6, 0),
+ RK3562_PERICRU_RESET_OFFSET(SRST_SPI1, 6, 1),
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_SPI2, 6, 3),
+ RK3562_PERICRU_RESET_OFFSET(SRST_SPI2, 6, 4),
+
+ /* PERI_SOFTRST_CON07 */
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_UART1, 7, 0),
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_UART2, 7, 1),
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_UART3, 7, 2),
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_UART4, 7, 3),
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_UART5, 7, 4),
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_UART6, 7, 5),
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_UART7, 7, 6),
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_UART8, 7, 7),
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_UART9, 7, 8),
+ RK3562_PERICRU_RESET_OFFSET(SRST_S_UART1, 7, 11),
+ RK3562_PERICRU_RESET_OFFSET(SRST_S_UART2, 7, 14),
+
+ /* PERI_SOFTRST_CON08 */
+ RK3562_PERICRU_RESET_OFFSET(SRST_S_UART3, 8, 1),
+ RK3562_PERICRU_RESET_OFFSET(SRST_S_UART4, 8, 4),
+ RK3562_PERICRU_RESET_OFFSET(SRST_S_UART5, 8, 7),
+ RK3562_PERICRU_RESET_OFFSET(SRST_S_UART6, 8, 10),
+ RK3562_PERICRU_RESET_OFFSET(SRST_S_UART7, 8, 13),
+
+ /* PERI_SOFTRST_CON09 */
+ RK3562_PERICRU_RESET_OFFSET(SRST_S_UART8, 9, 0),
+ RK3562_PERICRU_RESET_OFFSET(SRST_S_UART9, 9, 3),
+
+ /* PERI_SOFTRST_CON10 */
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_PWM1_PERI, 10, 0),
+ RK3562_PERICRU_RESET_OFFSET(SRST_PWM1_PERI, 10, 1),
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_PWM2_PERI, 10, 3),
+ RK3562_PERICRU_RESET_OFFSET(SRST_PWM2_PERI, 10, 4),
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_PWM3_PERI, 10, 6),
+ RK3562_PERICRU_RESET_OFFSET(SRST_PWM3_PERI, 10, 7),
+
+ /* PERI_SOFTRST_CON11 */
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_CAN0, 11, 0),
+ RK3562_PERICRU_RESET_OFFSET(SRST_CAN0, 11, 1),
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_CAN1, 11, 2),
+ RK3562_PERICRU_RESET_OFFSET(SRST_CAN1, 11, 3),
+
+ /* PERI_SOFTRST_CON12 */
+ RK3562_PERICRU_RESET_OFFSET(SRST_A_CRYPTO, 12, 0),
+ RK3562_PERICRU_RESET_OFFSET(SRST_H_CRYPTO, 12, 1),
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_CRYPTO, 12, 2),
+ RK3562_PERICRU_RESET_OFFSET(SRST_CORE_CRYPTO, 12, 3),
+ RK3562_PERICRU_RESET_OFFSET(SRST_PKA_CRYPTO, 12, 4),
+ RK3562_PERICRU_RESET_OFFSET(SRST_H_KLAD, 12, 5),
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_KEY_READER, 12, 6),
+ RK3562_PERICRU_RESET_OFFSET(SRST_H_RK_RNG_NS, 12, 7),
+ RK3562_PERICRU_RESET_OFFSET(SRST_H_RK_RNG_S, 12, 8),
+ RK3562_PERICRU_RESET_OFFSET(SRST_H_TRNG_NS, 12, 9),
+ RK3562_PERICRU_RESET_OFFSET(SRST_H_TRNG_S, 12, 10),
+ RK3562_PERICRU_RESET_OFFSET(SRST_H_CRYPTO_S, 12, 11),
+
+ /* PERI_SOFTRST_CON13 */
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_PERI_WDT, 13, 0),
+ RK3562_PERICRU_RESET_OFFSET(SRST_T_PERI_WDT, 13, 1),
+ RK3562_PERICRU_RESET_OFFSET(SRST_A_SYSMEM, 13, 2),
+ RK3562_PERICRU_RESET_OFFSET(SRST_H_BOOTROM, 13, 3),
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_PERI_GRF, 13, 4),
+ RK3562_PERICRU_RESET_OFFSET(SRST_A_DMAC, 13, 5),
+ RK3562_PERICRU_RESET_OFFSET(SRST_A_RKDMAC, 13, 6),
+
+ /* PERI_SOFTRST_CON14 */
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_OTPC_NS, 14, 0),
+ RK3562_PERICRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 14, 1),
+ RK3562_PERICRU_RESET_OFFSET(SRST_USER_OTPC_NS, 14, 2),
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_OTPC_S, 14, 3),
+ RK3562_PERICRU_RESET_OFFSET(SRST_SBPI_OTPC_S, 14, 4),
+ RK3562_PERICRU_RESET_OFFSET(SRST_USER_OTPC_S, 14, 5),
+ RK3562_PERICRU_RESET_OFFSET(SRST_OTPC_ARB, 14, 6),
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_OTPPHY, 14, 7),
+ RK3562_PERICRU_RESET_OFFSET(SRST_OTP_NPOR, 14, 8),
+
+ /* PERI_SOFTRST_CON15 */
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_USB2PHY, 15, 0),
+ RK3562_PERICRU_RESET_OFFSET(SRST_USB2PHY_POR, 15, 4),
+ RK3562_PERICRU_RESET_OFFSET(SRST_USB2PHY_OTG, 15, 5),
+ RK3562_PERICRU_RESET_OFFSET(SRST_USB2PHY_HOST, 15, 6),
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_PIPEPHY, 15, 7),
+
+ /* PERI_SOFTRST_CON16 */
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_SARADC, 16, 4),
+ RK3562_PERICRU_RESET_OFFSET(SRST_SARADC, 16, 5),
+ RK3562_PERICRU_RESET_OFFSET(SRST_SARADC_PHY, 16, 6),
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_IOC_VCCIO234, 16, 12),
+
+ /* PERI_SOFTRST_CON17 */
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_PERI_GPIO1, 17, 0),
+ RK3562_PERICRU_RESET_OFFSET(SRST_P_PERI_GPIO2, 17, 1),
+ RK3562_PERICRU_RESET_OFFSET(SRST_PERI_GPIO1, 17, 2),
+ RK3562_PERICRU_RESET_OFFSET(SRST_PERI_GPIO2, 17, 3),
+};
+
+void rk3562_rst_init(struct device_node *np, void __iomem *reg_base)
+{
+ rockchip_register_softrst_lut(np,
+ rk3562_register_offset,
+ ARRAY_SIZE(rk3562_register_offset),
+ reg_base + RK3562_SOFTRST_CON(0),
+ ROCKCHIP_SOFTRST_HIWORD_MASK);
+}
diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h
index 01e14ab252a7..dd988cc9d582 100644
--- a/include/dt-bindings/clock/rk3188-cru-common.h
+++ b/include/dt-bindings/clock/rk3188-cru-common.h
@@ -103,6 +103,8 @@
#define PCLK_PERI 351
#define PCLK_DDRUPCTL 352
#define PCLK_PUBL 353
+#define PCLK_CIF0 354
+#define PCLK_CIF1 355
/* hclk gates */
#define HCLK_SDMMC 448
diff --git a/include/dt-bindings/clock/rockchip,rk3528-cru.h b/include/dt-bindings/clock/rockchip,rk3528-cru.h
new file mode 100644
index 000000000000..55a448f5ed6d
--- /dev/null
+++ b/include/dt-bindings/clock/rockchip,rk3528-cru.h
@@ -0,0 +1,453 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
+ * Author: Joseph Chen <chenjh@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
+
+/* cru-clocks indices */
+#define PLL_APLL 0
+#define PLL_CPLL 1
+#define PLL_GPLL 2
+#define PLL_PPLL 3
+#define PLL_DPLL 4
+#define ARMCLK 5
+#define XIN_OSC0_HALF 6
+#define CLK_MATRIX_50M_SRC 7
+#define CLK_MATRIX_100M_SRC 8
+#define CLK_MATRIX_150M_SRC 9
+#define CLK_MATRIX_200M_SRC 10
+#define CLK_MATRIX_250M_SRC 11
+#define CLK_MATRIX_300M_SRC 12
+#define CLK_MATRIX_339M_SRC 13
+#define CLK_MATRIX_400M_SRC 14
+#define CLK_MATRIX_500M_SRC 15
+#define CLK_MATRIX_600M_SRC 16
+#define CLK_UART0_SRC 17
+#define CLK_UART0_FRAC 18
+#define SCLK_UART0 19
+#define CLK_UART1_SRC 20
+#define CLK_UART1_FRAC 21
+#define SCLK_UART1 22
+#define CLK_UART2_SRC 23
+#define CLK_UART2_FRAC 24
+#define SCLK_UART2 25
+#define CLK_UART3_SRC 26
+#define CLK_UART3_FRAC 27
+#define SCLK_UART3 28
+#define CLK_UART4_SRC 29
+#define CLK_UART4_FRAC 30
+#define SCLK_UART4 31
+#define CLK_UART5_SRC 32
+#define CLK_UART5_FRAC 33
+#define SCLK_UART5 34
+#define CLK_UART6_SRC 35
+#define CLK_UART6_FRAC 36
+#define SCLK_UART6 37
+#define CLK_UART7_SRC 38
+#define CLK_UART7_FRAC 39
+#define SCLK_UART7 40
+#define CLK_I2S0_2CH_SRC 41
+#define CLK_I2S0_2CH_FRAC 42
+#define MCLK_I2S0_2CH_SAI_SRC 43
+#define CLK_I2S3_8CH_SRC 44
+#define CLK_I2S3_8CH_FRAC 45
+#define MCLK_I2S3_8CH_SAI_SRC 46
+#define CLK_I2S1_8CH_SRC 47
+#define CLK_I2S1_8CH_FRAC 48
+#define MCLK_I2S1_8CH_SAI_SRC 49
+#define CLK_I2S2_2CH_SRC 50
+#define CLK_I2S2_2CH_FRAC 51
+#define MCLK_I2S2_2CH_SAI_SRC 52
+#define CLK_SPDIF_SRC 53
+#define CLK_SPDIF_FRAC 54
+#define MCLK_SPDIF_SRC 55
+#define DCLK_VOP_SRC0 56
+#define DCLK_VOP_SRC1 57
+#define CLK_HSM 58
+#define CLK_CORE_SRC_ACS 59
+#define CLK_CORE_SRC_PVTMUX 60
+#define CLK_CORE_SRC 61
+#define CLK_CORE 62
+#define ACLK_M_CORE_BIU 63
+#define CLK_CORE_PVTPLL_SRC 64
+#define PCLK_DBG 65
+#define SWCLKTCK 66
+#define CLK_SCANHS_CORE 67
+#define CLK_SCANHS_ACLKM_CORE 68
+#define CLK_SCANHS_PCLK_DBG 69
+#define CLK_SCANHS_PCLK_CPU_BIU 70
+#define PCLK_CPU_ROOT 71
+#define PCLK_CORE_GRF 72
+#define PCLK_DAPLITE_BIU 73
+#define PCLK_CPU_BIU 74
+#define CLK_REF_PVTPLL_CORE 75
+#define ACLK_BUS_VOPGL_ROOT 76
+#define ACLK_BUS_VOPGL_BIU 77
+#define ACLK_BUS_H_ROOT 78
+#define ACLK_BUS_H_BIU 79
+#define ACLK_BUS_ROOT 80
+#define HCLK_BUS_ROOT 81
+#define PCLK_BUS_ROOT 82
+#define ACLK_BUS_M_ROOT 83
+#define ACLK_SYSMEM_BIU 84
+#define CLK_TIMER_ROOT 85
+#define ACLK_BUS_BIU 86
+#define HCLK_BUS_BIU 87
+#define PCLK_BUS_BIU 88
+#define PCLK_DFT2APB 89
+#define PCLK_BUS_GRF 90
+#define ACLK_BUS_M_BIU 91
+#define ACLK_GIC 92
+#define ACLK_SPINLOCK 93
+#define ACLK_DMAC 94
+#define PCLK_TIMER 95
+#define CLK_TIMER0 96
+#define CLK_TIMER1 97
+#define CLK_TIMER2 98
+#define CLK_TIMER3 99
+#define CLK_TIMER4 100
+#define CLK_TIMER5 101
+#define PCLK_JDBCK_DAP 102
+#define CLK_JDBCK_DAP 103
+#define PCLK_WDT_NS 104
+#define TCLK_WDT_NS 105
+#define HCLK_TRNG_NS 106
+#define PCLK_UART0 107
+#define PCLK_DMA2DDR 108
+#define ACLK_DMA2DDR 109
+#define PCLK_PWM0 110
+#define CLK_PWM0 111
+#define CLK_CAPTURE_PWM0 112
+#define PCLK_PWM1 113
+#define CLK_PWM1 114
+#define CLK_CAPTURE_PWM1 115
+#define PCLK_SCR 116
+#define ACLK_DCF 117
+#define PCLK_INTMUX 118
+#define CLK_PPLL_I 119
+#define CLK_PPLL_MUX 120
+#define CLK_PPLL_100M_MATRIX 121
+#define CLK_PPLL_50M_MATRIX 122
+#define CLK_REF_PCIE_INNER_PHY 123
+#define CLK_REF_PCIE_100M_PHY 124
+#define ACLK_VPU_L_ROOT 125
+#define CLK_GMAC1_VPU_25M 126
+#define CLK_PPLL_125M_MATRIX 127
+#define ACLK_VPU_ROOT 128
+#define HCLK_VPU_ROOT 129
+#define PCLK_VPU_ROOT 130
+#define ACLK_VPU_BIU 131
+#define HCLK_VPU_BIU 132
+#define PCLK_VPU_BIU 133
+#define ACLK_VPU 134
+#define HCLK_VPU 135
+#define PCLK_CRU_PCIE 136
+#define PCLK_VPU_GRF 137
+#define HCLK_SFC 138
+#define SCLK_SFC 139
+#define CCLK_SRC_EMMC 140
+#define HCLK_EMMC 141
+#define ACLK_EMMC 142
+#define BCLK_EMMC 143
+#define TCLK_EMMC 144
+#define PCLK_GPIO1 145
+#define DBCLK_GPIO1 146
+#define ACLK_VPU_L_BIU 147
+#define PCLK_VPU_IOC 148
+#define HCLK_SAI_I2S0 149
+#define MCLK_SAI_I2S0 150
+#define HCLK_SAI_I2S2 151
+#define MCLK_SAI_I2S2 152
+#define PCLK_ACODEC 153
+#define MCLK_ACODEC_TX 154
+#define PCLK_GPIO3 155
+#define DBCLK_GPIO3 156
+#define PCLK_SPI1 157
+#define CLK_SPI1 158
+#define SCLK_IN_SPI1 159
+#define PCLK_UART2 160
+#define PCLK_UART5 161
+#define PCLK_UART6 162
+#define PCLK_UART7 163
+#define PCLK_I2C3 164
+#define CLK_I2C3 165
+#define PCLK_I2C5 166
+#define CLK_I2C5 167
+#define PCLK_I2C6 168
+#define CLK_I2C6 169
+#define ACLK_MAC_VPU 170
+#define PCLK_MAC_VPU 171
+#define CLK_GMAC1_RMII_VPU 172
+#define CLK_GMAC1_SRC_VPU 173
+#define PCLK_PCIE 174
+#define CLK_PCIE_AUX 175
+#define ACLK_PCIE 176
+#define HCLK_PCIE_SLV 177
+#define HCLK_PCIE_DBI 178
+#define PCLK_PCIE_PHY 179
+#define PCLK_PIPE_GRF 180
+#define CLK_PIPE_USB3OTG_COMBO 181
+#define CLK_UTMI_USB3OTG 182
+#define CLK_PCIE_PIPE_PHY 183
+#define CCLK_SRC_SDIO0 184
+#define HCLK_SDIO0 185
+#define CCLK_SRC_SDIO1 186
+#define HCLK_SDIO1 187
+#define CLK_TS_0 188
+#define CLK_TS_1 189
+#define PCLK_CAN2 190
+#define CLK_CAN2 191
+#define PCLK_CAN3 192
+#define CLK_CAN3 193
+#define PCLK_SARADC 194
+#define CLK_SARADC 195
+#define PCLK_TSADC 196
+#define CLK_TSADC 197
+#define CLK_TSADC_TSEN 198
+#define ACLK_USB3OTG 199
+#define CLK_REF_USB3OTG 200
+#define CLK_SUSPEND_USB3OTG 201
+#define ACLK_GPU_ROOT 202
+#define PCLK_GPU_ROOT 203
+#define ACLK_GPU_BIU 204
+#define PCLK_GPU_BIU 205
+#define ACLK_GPU 206
+#define CLK_GPU_PVTPLL_SRC 207
+#define ACLK_GPU_MALI 208
+#define HCLK_RKVENC_ROOT 209
+#define ACLK_RKVENC_ROOT 210
+#define PCLK_RKVENC_ROOT 211
+#define HCLK_RKVENC_BIU 212
+#define ACLK_RKVENC_BIU 213
+#define PCLK_RKVENC_BIU 214
+#define HCLK_RKVENC 215
+#define ACLK_RKVENC 216
+#define CLK_CORE_RKVENC 217
+#define HCLK_SAI_I2S1 218
+#define MCLK_SAI_I2S1 219
+#define PCLK_I2C1 220
+#define CLK_I2C1 221
+#define PCLK_I2C0 222
+#define CLK_I2C0 223
+#define CLK_UART_JTAG 224
+#define PCLK_SPI0 225
+#define CLK_SPI0 226
+#define SCLK_IN_SPI0 227
+#define PCLK_GPIO4 228
+#define DBCLK_GPIO4 229
+#define PCLK_RKVENC_IOC 230
+#define HCLK_SPDIF 231
+#define MCLK_SPDIF 232
+#define HCLK_PDM 233
+#define MCLK_PDM 234
+#define PCLK_UART1 235
+#define PCLK_UART3 236
+#define PCLK_RKVENC_GRF 237
+#define PCLK_CAN0 238
+#define CLK_CAN0 239
+#define PCLK_CAN1 240
+#define CLK_CAN1 241
+#define ACLK_VO_ROOT 242
+#define HCLK_VO_ROOT 243
+#define PCLK_VO_ROOT 244
+#define ACLK_VO_BIU 245
+#define HCLK_VO_BIU 246
+#define PCLK_VO_BIU 247
+#define HCLK_RGA2E 248
+#define ACLK_RGA2E 249
+#define CLK_CORE_RGA2E 250
+#define HCLK_VDPP 251
+#define ACLK_VDPP 252
+#define CLK_CORE_VDPP 253
+#define PCLK_VO_GRF 254
+#define PCLK_CRU 255
+#define ACLK_VOP_ROOT 256
+#define ACLK_VOP_BIU 257
+#define HCLK_VOP 258
+#define DCLK_VOP0 259
+#define DCLK_VOP1 260
+#define ACLK_VOP 261
+#define PCLK_HDMI 262
+#define CLK_SFR_HDMI 263
+#define CLK_CEC_HDMI 264
+#define CLK_SPDIF_HDMI 265
+#define CLK_HDMIPHY_TMDSSRC 266
+#define CLK_HDMIPHY_PREP 267
+#define PCLK_HDMIPHY 268
+#define HCLK_HDCP_KEY 269
+#define ACLK_HDCP 270
+#define HCLK_HDCP 271
+#define PCLK_HDCP 272
+#define HCLK_CVBS 273
+#define DCLK_CVBS 274
+#define DCLK_4X_CVBS 275
+#define ACLK_JPEG_DECODER 276
+#define HCLK_JPEG_DECODER 277
+#define ACLK_VO_L_ROOT 278
+#define ACLK_VO_L_BIU 279
+#define ACLK_MAC_VO 280
+#define PCLK_MAC_VO 281
+#define CLK_GMAC0_SRC 282
+#define CLK_GMAC0_RMII_50M 283
+#define CLK_GMAC0_TX 284
+#define CLK_GMAC0_RX 285
+#define ACLK_JPEG_ROOT 286
+#define ACLK_JPEG_BIU 287
+#define HCLK_SAI_I2S3 288
+#define MCLK_SAI_I2S3 289
+#define CLK_MACPHY 290
+#define PCLK_VCDCPHY 291
+#define PCLK_GPIO2 292
+#define DBCLK_GPIO2 293
+#define PCLK_VO_IOC 294
+#define CCLK_SRC_SDMMC0 295
+#define HCLK_SDMMC0 296
+#define PCLK_OTPC_NS 297
+#define CLK_SBPI_OTPC_NS 298
+#define CLK_USER_OTPC_NS 299
+#define CLK_HDMIHDP0 300
+#define HCLK_USBHOST 301
+#define HCLK_USBHOST_ARB 302
+#define CLK_USBHOST_OHCI 303
+#define CLK_USBHOST_UTMI 304
+#define PCLK_UART4 305
+#define PCLK_I2C4 306
+#define CLK_I2C4 307
+#define PCLK_I2C7 308
+#define CLK_I2C7 309
+#define PCLK_USBPHY 310
+#define CLK_REF_USBPHY 311
+#define HCLK_RKVDEC_ROOT 312
+#define ACLK_RKVDEC_ROOT_NDFT 313
+#define PCLK_DDRPHY_CRU 314
+#define HCLK_RKVDEC_BIU 315
+#define ACLK_RKVDEC_BIU 316
+#define ACLK_RKVDEC 317
+#define HCLK_RKVDEC 318
+#define CLK_HEVC_CA_RKVDEC 319
+#define ACLK_RKVDEC_PVTMUX_ROOT 320
+#define CLK_RKVDEC_PVTPLL_SRC 321
+#define PCLK_DDR_ROOT 322
+#define PCLK_DDR_BIU 323
+#define PCLK_DDRC 324
+#define PCLK_DDRMON 325
+#define CLK_TIMER_DDRMON 326
+#define PCLK_MSCH_BIU 327
+#define PCLK_DDR_GRF 328
+#define PCLK_DDR_HWLP 329
+#define PCLK_DDRPHY 330
+#define CLK_MSCH_BIU 331
+#define ACLK_DDR_UPCTL 332
+#define CLK_DDR_UPCTL 333
+#define CLK_DDRMON 334
+#define ACLK_DDR_SCRAMBLE 335
+#define ACLK_SPLIT 336
+#define CLK_DDRC_SRC 337
+#define CLK_DDR_PHY 338
+#define PCLK_OTPC_S 339
+#define CLK_SBPI_OTPC_S 340
+#define CLK_USER_OTPC_S 341
+#define PCLK_KEYREADER 342
+#define PCLK_BUS_SGRF 343
+#define PCLK_STIMER 344
+#define CLK_STIMER0 345
+#define CLK_STIMER1 346
+#define PCLK_WDT_S 347
+#define TCLK_WDT_S 348
+#define HCLK_TRNG_S 349
+#define HCLK_BOOTROM 350
+#define PCLK_DCF 351
+#define ACLK_SYSMEM 352
+#define HCLK_TSP 353
+#define ACLK_TSP 354
+#define CLK_CORE_TSP 355
+#define CLK_OTPC_ARB 356
+#define PCLK_OTP_MASK 357
+#define CLK_PMC_OTP 358
+#define PCLK_PMU_ROOT 359
+#define HCLK_PMU_ROOT 360
+#define PCLK_I2C2 361
+#define CLK_I2C2 362
+#define HCLK_PMU_BIU 363
+#define PCLK_PMU_BIU 364
+#define FCLK_MCU 365
+#define RTC_CLK_MCU 366
+#define PCLK_OSCCHK 367
+#define CLK_PMU_MCU_JTAG 368
+#define PCLK_PMU 369
+#define PCLK_GPIO0 370
+#define DBCLK_GPIO0 371
+#define XIN_OSC0_DIV 372
+#define CLK_DEEPSLOW 373
+#define CLK_DDR_FAIL_SAFE 374
+#define PCLK_PMU_HP_TIMER 375
+#define CLK_PMU_HP_TIMER 376
+#define CLK_PMU_32K_HP_TIMER 377
+#define PCLK_PMU_IOC 378
+#define PCLK_PMU_CRU 379
+#define PCLK_PMU_GRF 380
+#define PCLK_PMU_WDT 381
+#define TCLK_PMU_WDT 382
+#define PCLK_PMU_MAILBOX 383
+#define PCLK_SCRKEYGEN 384
+#define CLK_SCRKEYGEN 385
+#define CLK_PVTM_OSCCHK 386
+#define CLK_REFOUT 387
+#define CLK_PVTM_PMU 388
+#define PCLK_PVTM_PMU 389
+#define PCLK_PMU_SGRF 390
+#define HCLK_PMU_SRAM 391
+#define CLK_UART0 392
+#define CLK_UART1 393
+#define CLK_UART2 394
+#define CLK_UART3 395
+#define CLK_UART4 396
+#define CLK_UART5 397
+#define CLK_UART6 398
+#define CLK_UART7 399
+#define MCLK_I2S0_2CH_SAI_SRC_PRE 400
+#define MCLK_I2S1_8CH_SAI_SRC_PRE 401
+#define MCLK_I2S2_2CH_SAI_SRC_PRE 402
+#define MCLK_I2S3_8CH_SAI_SRC_PRE 403
+#define MCLK_SDPDIF_SRC_PRE 404
+
+/* scmi-clocks indices */
+#define SCMI_PCLK_KEYREADER 0
+#define SCMI_HCLK_KLAD 1
+#define SCMI_PCLK_KLAD 2
+#define SCMI_HCLK_TRNG_S 3
+#define SCMI_HCLK_CRYPTO_S 4
+#define SCMI_PCLK_WDT_S 5
+#define SCMI_TCLK_WDT_S 6
+#define SCMI_PCLK_STIMER 7
+#define SCMI_CLK_STIMER0 8
+#define SCMI_CLK_STIMER1 9
+#define SCMI_PCLK_OTP_MASK 10
+#define SCMI_PCLK_OTPC_S 11
+#define SCMI_CLK_SBPI_OTPC_S 12
+#define SCMI_CLK_USER_OTPC_S 13
+#define SCMI_CLK_PMC_OTP 14
+#define SCMI_CLK_OTPC_ARB 15
+#define SCMI_CLK_CORE_TSP 16
+#define SCMI_ACLK_TSP 17
+#define SCMI_HCLK_TSP 18
+#define SCMI_PCLK_DCF 19
+#define SCMI_CLK_DDR 20
+#define SCMI_CLK_CPU 21
+#define SCMI_CLK_GPU 22
+#define SCMI_CORE_CRYPTO 23
+#define SCMI_ACLK_CRYPTO 24
+#define SCMI_PKA_CRYPTO 25
+#define SCMI_HCLK_CRYPTO 26
+#define SCMI_CORE_CRYPTO_S 27
+#define SCMI_ACLK_CRYPTO_S 28
+#define SCMI_PKA_CRYPTO_S 29
+#define SCMI_CORE_KLAD 30
+#define SCMI_ACLK_KLAD 31
+#define SCMI_HCLK_TRNG 32
+
+#endif // _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
diff --git a/include/dt-bindings/clock/rockchip,rk3562-cru.h b/include/dt-bindings/clock/rockchip,rk3562-cru.h
new file mode 100644
index 000000000000..a5b0b153209c
--- /dev/null
+++ b/include/dt-bindings/clock/rockchip,rk3562-cru.h
@@ -0,0 +1,379 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2022-2025 Rockchip Electronics Co., Ltd.
+ * Author: Finley Xiao <finley.xiao@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H
+
+/* cru-clocks indices */
+
+/* cru plls */
+#define PLL_DMPLL0 0
+#define PLL_APLL 1
+#define PLL_GPLL 2
+#define PLL_VPLL 3
+#define PLL_HPLL 4
+#define PLL_CPLL 5
+#define PLL_DPLL 6
+#define PLL_DMPLL1 7
+
+/* cru clocks */
+#define ARMCLK 8
+#define CLK_GPU 9
+#define ACLK_RKNN 10
+#define CLK_DDR 11
+#define CLK_MATRIX_50M_SRC 12
+#define CLK_MATRIX_100M_SRC 13
+#define CLK_MATRIX_125M_SRC 14
+#define CLK_MATRIX_200M_SRC 15
+#define CLK_MATRIX_300M_SRC 16
+#define ACLK_TOP 17
+#define ACLK_TOP_VIO 18
+#define CLK_CAM0_OUT2IO 19
+#define CLK_CAM1_OUT2IO 20
+#define CLK_CAM2_OUT2IO 21
+#define CLK_CAM3_OUT2IO 22
+#define ACLK_BUS 23
+#define HCLK_BUS 24
+#define PCLK_BUS 25
+#define PCLK_I2C1 26
+#define PCLK_I2C2 27
+#define PCLK_I2C3 28
+#define PCLK_I2C4 29
+#define PCLK_I2C5 30
+#define CLK_I2C 31
+#define CLK_I2C1 32
+#define CLK_I2C2 33
+#define CLK_I2C3 34
+#define CLK_I2C4 35
+#define CLK_I2C5 36
+#define DCLK_BUS_GPIO 37
+#define DCLK_BUS_GPIO3 38
+#define DCLK_BUS_GPIO4 39
+#define PCLK_TIMER 40
+#define CLK_TIMER0 41
+#define CLK_TIMER1 42
+#define CLK_TIMER2 43
+#define CLK_TIMER3 44
+#define CLK_TIMER4 45
+#define CLK_TIMER5 46
+#define PCLK_STIMER 47
+#define CLK_STIMER0 48
+#define CLK_STIMER1 49
+#define PCLK_WDTNS 50
+#define CLK_WDTNS 51
+#define PCLK_GRF 52
+#define PCLK_SGRF 53
+#define PCLK_MAILBOX 54
+#define PCLK_INTC 55
+#define ACLK_BUS_GIC400 56
+#define ACLK_BUS_SPINLOCK 57
+#define ACLK_DCF 58
+#define PCLK_DCF 59
+#define FCLK_BUS_CM0_CORE 60
+#define CLK_BUS_CM0_RTC 61
+#define HCLK_ICACHE 62
+#define HCLK_DCACHE 63
+#define PCLK_TSADC 64
+#define CLK_TSADC 65
+#define CLK_TSADC_TSEN 66
+#define PCLK_DFT2APB 67
+#define CLK_SARADC_VCCIO156 68
+#define PCLK_GMAC 69
+#define ACLK_GMAC 70
+#define CLK_GMAC_125M_CRU_I 71
+#define CLK_GMAC_50M_CRU_I 72
+#define CLK_GMAC_50M_O 73
+#define CLK_GMAC_ETH_OUT2IO 74
+#define PCLK_APB2ASB_VCCIO156 75
+#define PCLK_TO_VCCIO156 76
+#define PCLK_DSIPHY 77
+#define PCLK_DSITX 78
+#define PCLK_CPU_EMA_DET 79
+#define PCLK_HASH 80
+#define PCLK_TOPCRU 81
+#define PCLK_ASB2APB_VCCIO156 82
+#define PCLK_IOC_VCCIO156 83
+#define PCLK_GPIO3_VCCIO156 84
+#define PCLK_GPIO4_VCCIO156 85
+#define PCLK_SARADC_VCCIO156 86
+#define PCLK_MAC100 87
+#define ACLK_MAC100 89
+#define CLK_MAC100_50M_MATRIX 90
+#define HCLK_CORE 91
+#define PCLK_DDR 92
+#define CLK_MSCH_BRG_BIU 93
+#define PCLK_DDR_HWLP 94
+#define PCLK_DDR_UPCTL 95
+#define PCLK_DDR_PHY 96
+#define PCLK_DDR_DFICTL 97
+#define PCLK_DDR_DMA2DDR 98
+#define PCLK_DDR_MON 99
+#define TMCLK_DDR_MON 100
+#define PCLK_DDR_GRF 101
+#define PCLK_DDR_CRU 102
+#define PCLK_SUBDDR_CRU 103
+#define CLK_GPU_PRE 104
+#define ACLK_GPU_PRE 105
+#define CLK_GPU_BRG 107
+#define CLK_NPU_PRE 108
+#define HCLK_NPU_PRE 109
+#define HCLK_RKNN 111
+#define ACLK_PERI 112
+#define HCLK_PERI 113
+#define PCLK_PERI 114
+#define PCLK_PERICRU 115
+#define HCLK_SAI0 116
+#define CLK_SAI0_SRC 117
+#define CLK_SAI0_FRAC 118
+#define CLK_SAI0 119
+#define MCLK_SAI0 120
+#define MCLK_SAI0_OUT2IO 121
+#define HCLK_SAI1 122
+#define CLK_SAI1_SRC 123
+#define CLK_SAI1_FRAC 124
+#define CLK_SAI1 125
+#define MCLK_SAI1 126
+#define MCLK_SAI1_OUT2IO 127
+#define HCLK_SAI2 128
+#define CLK_SAI2_SRC 129
+#define CLK_SAI2_FRAC 130
+#define CLK_SAI2 131
+#define MCLK_SAI2 132
+#define MCLK_SAI2_OUT2IO 133
+#define HCLK_DSM 134
+#define CLK_DSM 135
+#define HCLK_PDM 136
+#define MCLK_PDM 137
+#define HCLK_SPDIF 138
+#define CLK_SPDIF_SRC 139
+#define CLK_SPDIF_FRAC 140
+#define CLK_SPDIF 141
+#define MCLK_SPDIF 142
+#define HCLK_SDMMC0 143
+#define CCLK_SDMMC0 144
+#define HCLK_SDMMC1 145
+#define CCLK_SDMMC1 146
+#define SCLK_SDMMC0_DRV 147
+#define SCLK_SDMMC0_SAMPLE 148
+#define SCLK_SDMMC1_DRV 149
+#define SCLK_SDMMC1_SAMPLE 150
+#define HCLK_EMMC 151
+#define ACLK_EMMC 152
+#define CCLK_EMMC 153
+#define BCLK_EMMC 154
+#define TMCLK_EMMC 155
+#define SCLK_SFC 156
+#define HCLK_SFC 157
+#define HCLK_USB2HOST 158
+#define HCLK_USB2HOST_ARB 159
+#define PCLK_SPI1 160
+#define CLK_SPI1 161
+#define SCLK_IN_SPI1 162
+#define PCLK_SPI2 163
+#define CLK_SPI2 164
+#define SCLK_IN_SPI2 165
+#define PCLK_UART1 166
+#define PCLK_UART2 167
+#define PCLK_UART3 168
+#define PCLK_UART4 169
+#define PCLK_UART5 170
+#define PCLK_UART6 171
+#define PCLK_UART7 172
+#define PCLK_UART8 173
+#define PCLK_UART9 174
+#define CLK_UART1_SRC 175
+#define CLK_UART1_FRAC 176
+#define CLK_UART1 177
+#define SCLK_UART1 178
+#define CLK_UART2_SRC 179
+#define CLK_UART2_FRAC 180
+#define CLK_UART2 181
+#define SCLK_UART2 182
+#define CLK_UART3_SRC 183
+#define CLK_UART3_FRAC 184
+#define CLK_UART3 185
+#define SCLK_UART3 186
+#define CLK_UART4_SRC 187
+#define CLK_UART4_FRAC 188
+#define CLK_UART4 189
+#define SCLK_UART4 190
+#define CLK_UART5_SRC 191
+#define CLK_UART5_FRAC 192
+#define CLK_UART5 193
+#define SCLK_UART5 194
+#define CLK_UART6_SRC 195
+#define CLK_UART6_FRAC 196
+#define CLK_UART6 197
+#define SCLK_UART6 198
+#define CLK_UART7_SRC 199
+#define CLK_UART7_FRAC 200
+#define CLK_UART7 201
+#define SCLK_UART7 202
+#define CLK_UART8_SRC 203
+#define CLK_UART8_FRAC 204
+#define CLK_UART8 205
+#define SCLK_UART8 206
+#define CLK_UART9_SRC 207
+#define CLK_UART9_FRAC 208
+#define CLK_UART9 209
+#define SCLK_UART9 210
+#define PCLK_PWM1_PERI 211
+#define CLK_PWM1_PERI 212
+#define CLK_CAPTURE_PWM1_PERI 213
+#define PCLK_PWM2_PERI 214
+#define CLK_PWM2_PERI 215
+#define CLK_CAPTURE_PWM2_PERI 216
+#define PCLK_PWM3_PERI 217
+#define CLK_PWM3_PERI 218
+#define CLK_CAPTURE_PWM3_PERI 219
+#define PCLK_CAN0 220
+#define CLK_CAN0 221
+#define PCLK_CAN1 222
+#define CLK_CAN1 223
+#define ACLK_CRYPTO 224
+#define HCLK_CRYPTO 225
+#define PCLK_CRYPTO 226
+#define CLK_CORE_CRYPTO 227
+#define CLK_PKA_CRYPTO 228
+#define HCLK_KLAD 229
+#define PCLK_KEY_READER 230
+#define HCLK_RK_RNG_NS 231
+#define HCLK_RK_RNG_S 232
+#define HCLK_TRNG_NS 233
+#define HCLK_TRNG_S 234
+#define HCLK_CRYPTO_S 235
+#define PCLK_PERI_WDT 236
+#define TCLK_PERI_WDT 237
+#define ACLK_SYSMEM 238
+#define HCLK_BOOTROM 239
+#define PCLK_PERI_GRF 240
+#define ACLK_DMAC 241
+#define ACLK_RKDMAC 242
+#define PCLK_OTPC_NS 243
+#define CLK_SBPI_OTPC_NS 244
+#define CLK_USER_OTPC_NS 245
+#define PCLK_OTPC_S 246
+#define CLK_SBPI_OTPC_S 247
+#define CLK_USER_OTPC_S 248
+#define CLK_OTPC_ARB 249
+#define PCLK_OTPPHY 250
+#define PCLK_USB2PHY 251
+#define PCLK_PIPEPHY 252
+#define PCLK_SARADC 253
+#define CLK_SARADC 254
+#define PCLK_IOC_VCCIO234 255
+#define PCLK_PERI_GPIO1 256
+#define PCLK_PERI_GPIO2 257
+#define DCLK_PERI_GPIO 258
+#define DCLK_PERI_GPIO1 259
+#define DCLK_PERI_GPIO2 260
+#define ACLK_PHP 261
+#define PCLK_PHP 262
+#define ACLK_PCIE20_MST 263
+#define ACLK_PCIE20_SLV 264
+#define ACLK_PCIE20_DBI 265
+#define PCLK_PCIE20 266
+#define CLK_PCIE20_AUX 267
+#define ACLK_USB3OTG 268
+#define CLK_USB3OTG_SUSPEND 269
+#define CLK_USB3OTG_REF 270
+#define CLK_PIPEPHY_REF_FUNC 271
+#define CLK_200M_PMU 272
+#define CLK_RTC_32K 273
+#define CLK_RTC32K_FRAC 274
+#define BUSCLK_PDPMU0 275
+#define PCLK_PMU0_CRU 276
+#define PCLK_PMU0_PMU 277
+#define CLK_PMU0_PMU 278
+#define PCLK_PMU0_HP_TIMER 279
+#define CLK_PMU0_HP_TIMER 280
+#define CLK_PMU0_32K_HP_TIMER 281
+#define PCLK_PMU0_PVTM 282
+#define CLK_PMU0_PVTM 283
+#define PCLK_IOC_PMUIO 284
+#define PCLK_PMU0_GPIO0 285
+#define DBCLK_PMU0_GPIO0 286
+#define PCLK_PMU0_GRF 287
+#define PCLK_PMU0_SGRF 288
+#define CLK_DDR_FAIL_SAFE 289
+#define PCLK_PMU0_SCRKEYGEN 290
+#define PCLK_PMU1_CRU 291
+#define HCLK_PMU1_MEM 292
+#define PCLK_PMU0_I2C0 293
+#define CLK_PMU0_I2C0 294
+#define PCLK_PMU1_UART0 295
+#define CLK_PMU1_UART0_SRC 296
+#define CLK_PMU1_UART0_FRAC 297
+#define CLK_PMU1_UART0 298
+#define SCLK_PMU1_UART0 299
+#define PCLK_PMU1_SPI0 300
+#define CLK_PMU1_SPI0 301
+#define SCLK_IN_PMU1_SPI0 302
+#define PCLK_PMU1_PWM0 303
+#define CLK_PMU1_PWM0 304
+#define CLK_CAPTURE_PMU1_PWM0 305
+#define CLK_PMU1_WIFI 306
+#define FCLK_PMU1_CM0_CORE 307
+#define CLK_PMU1_CM0_RTC 308
+#define PCLK_PMU1_WDTNS 309
+#define CLK_PMU1_WDTNS 310
+#define PCLK_PMU1_MAILBOX 311
+#define CLK_PIPEPHY_DIV 312
+#define CLK_PIPEPHY_XIN24M 313
+#define CLK_PIPEPHY_REF 314
+#define CLK_24M_SSCSRC 315
+#define CLK_USB2PHY_XIN24M 316
+#define CLK_USB2PHY_REF 317
+#define CLK_MIPIDSIPHY_XIN24M 318
+#define CLK_MIPIDSIPHY_REF 319
+#define ACLK_RGA_PRE 320
+#define HCLK_RGA_PRE 321
+#define ACLK_RGA 322
+#define HCLK_RGA 323
+#define CLK_RGA_CORE 324
+#define ACLK_JDEC 325
+#define HCLK_JDEC 326
+#define ACLK_VDPU_PRE 327
+#define CLK_RKVDEC_HEVC_CA 328
+#define HCLK_VDPU_PRE 329
+#define ACLK_RKVDEC 330
+#define HCLK_RKVDEC 331
+#define CLK_RKVENC_CORE 332
+#define ACLK_VEPU_PRE 333
+#define HCLK_VEPU_PRE 334
+#define ACLK_RKVENC 335
+#define HCLK_RKVENC 336
+#define ACLK_VI 337
+#define HCLK_VI 338
+#define PCLK_VI 339
+#define ACLK_ISP 340
+#define HCLK_ISP 341
+#define CLK_ISP 342
+#define ACLK_VICAP 343
+#define HCLK_VICAP 344
+#define DCLK_VICAP 345
+#define CSIRX0_CLK_DATA 346
+#define CSIRX1_CLK_DATA 347
+#define CSIRX2_CLK_DATA 348
+#define CSIRX3_CLK_DATA 349
+#define PCLK_CSIHOST0 350
+#define PCLK_CSIHOST1 351
+#define PCLK_CSIHOST2 352
+#define PCLK_CSIHOST3 353
+#define PCLK_CSIPHY0 354
+#define PCLK_CSIPHY1 355
+#define ACLK_VO_PRE 356
+#define HCLK_VO_PRE 357
+#define ACLK_VOP 358
+#define HCLK_VOP 359
+#define DCLK_VOP 360
+#define DCLK_VOP1 361
+#define ACLK_CRYPTO_S 362
+#define PCLK_CRYPTO_S 363
+#define CLK_CORE_CRYPTO_S 364
+#define CLK_PKA_CRYPTO_S 365
+
+#endif
diff --git a/include/dt-bindings/reset/rockchip,rk3528-cru.h b/include/dt-bindings/reset/rockchip,rk3528-cru.h
new file mode 100644
index 000000000000..6b024c5f2e1c
--- /dev/null
+++ b/include/dt-bindings/reset/rockchip,rk3528-cru.h
@@ -0,0 +1,241 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
+ * Author: Joseph Chen <chenjh@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
+#define _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
+
+#define SRST_CORE0_PO 0
+#define SRST_CORE1_PO 1
+#define SRST_CORE2_PO 2
+#define SRST_CORE3_PO 3
+#define SRST_CORE0 4
+#define SRST_CORE1 5
+#define SRST_CORE2 6
+#define SRST_CORE3 7
+#define SRST_NL2 8
+#define SRST_CORE_BIU 9
+#define SRST_CORE_CRYPTO 10
+#define SRST_P_DBG 11
+#define SRST_POT_DBG 12
+#define SRST_NT_DBG 13
+#define SRST_P_CORE_GRF 14
+#define SRST_P_DAPLITE_BIU 15
+#define SRST_P_CPU_BIU 16
+#define SRST_REF_PVTPLL_CORE 17
+#define SRST_A_BUS_VOPGL_BIU 18
+#define SRST_A_BUS_H_BIU 19
+#define SRST_A_SYSMEM_BIU 20
+#define SRST_A_BUS_BIU 21
+#define SRST_H_BUS_BIU 22
+#define SRST_P_BUS_BIU 23
+#define SRST_P_DFT2APB 24
+#define SRST_P_BUS_GRF 25
+#define SRST_A_BUS_M_BIU 26
+#define SRST_A_GIC 27
+#define SRST_A_SPINLOCK 28
+#define SRST_A_DMAC 29
+#define SRST_P_TIMER 30
+#define SRST_TIMER0 31
+#define SRST_TIMER1 32
+#define SRST_TIMER2 33
+#define SRST_TIMER3 34
+#define SRST_TIMER4 35
+#define SRST_TIMER5 36
+#define SRST_P_JDBCK_DAP 37
+#define SRST_JDBCK_DAP 38
+#define SRST_P_WDT_NS 39
+#define SRST_T_WDT_NS 40
+#define SRST_H_TRNG_NS 41
+#define SRST_P_UART0 42
+#define SRST_S_UART0 43
+#define SRST_PKA_CRYPTO 44
+#define SRST_A_CRYPTO 45
+#define SRST_H_CRYPTO 46
+#define SRST_P_DMA2DDR 47
+#define SRST_A_DMA2DDR 48
+#define SRST_P_PWM0 49
+#define SRST_PWM0 50
+#define SRST_P_PWM1 51
+#define SRST_PWM1 52
+#define SRST_P_SCR 53
+#define SRST_A_DCF 54
+#define SRST_P_INTMUX 55
+#define SRST_A_VPU_BIU 56
+#define SRST_H_VPU_BIU 57
+#define SRST_P_VPU_BIU 58
+#define SRST_A_VPU 59
+#define SRST_H_VPU 60
+#define SRST_P_CRU_PCIE 61
+#define SRST_P_VPU_GRF 62
+#define SRST_H_SFC 63
+#define SRST_S_SFC 64
+#define SRST_C_EMMC 65
+#define SRST_H_EMMC 66
+#define SRST_A_EMMC 67
+#define SRST_B_EMMC 68
+#define SRST_T_EMMC 69
+#define SRST_P_GPIO1 70
+#define SRST_DB_GPIO1 71
+#define SRST_A_VPU_L_BIU 72
+#define SRST_P_VPU_IOC 73
+#define SRST_H_SAI_I2S0 74
+#define SRST_M_SAI_I2S0 75
+#define SRST_H_SAI_I2S2 76
+#define SRST_M_SAI_I2S2 77
+#define SRST_P_ACODEC 78
+#define SRST_P_GPIO3 79
+#define SRST_DB_GPIO3 80
+#define SRST_P_SPI1 81
+#define SRST_SPI1 82
+#define SRST_P_UART2 83
+#define SRST_S_UART2 84
+#define SRST_P_UART5 85
+#define SRST_S_UART5 86
+#define SRST_P_UART6 87
+#define SRST_S_UART6 88
+#define SRST_P_UART7 89
+#define SRST_S_UART7 90
+#define SRST_P_I2C3 91
+#define SRST_I2C3 92
+#define SRST_P_I2C5 93
+#define SRST_I2C5 94
+#define SRST_P_I2C6 95
+#define SRST_I2C6 96
+#define SRST_A_MAC 97
+#define SRST_P_PCIE 98
+#define SRST_PCIE_PIPE_PHY 99
+#define SRST_PCIE_POWER_UP 100
+#define SRST_P_PCIE_PHY 101
+#define SRST_P_PIPE_GRF 102
+#define SRST_H_SDIO0 103
+#define SRST_H_SDIO1 104
+#define SRST_TS_0 105
+#define SRST_TS_1 106
+#define SRST_P_CAN2 107
+#define SRST_CAN2 108
+#define SRST_P_CAN3 109
+#define SRST_CAN3 110
+#define SRST_P_SARADC 111
+#define SRST_SARADC 112
+#define SRST_SARADC_PHY 113
+#define SRST_P_TSADC 114
+#define SRST_TSADC 115
+#define SRST_A_USB3OTG 116
+#define SRST_A_GPU_BIU 117
+#define SRST_P_GPU_BIU 118
+#define SRST_A_GPU 119
+#define SRST_REF_PVTPLL_GPU 120
+#define SRST_H_RKVENC_BIU 121
+#define SRST_A_RKVENC_BIU 122
+#define SRST_P_RKVENC_BIU 123
+#define SRST_H_RKVENC 124
+#define SRST_A_RKVENC 125
+#define SRST_CORE_RKVENC 126
+#define SRST_H_SAI_I2S1 127
+#define SRST_M_SAI_I2S1 128
+#define SRST_P_I2C1 129
+#define SRST_I2C1 130
+#define SRST_P_I2C0 131
+#define SRST_I2C0 132
+#define SRST_P_SPI0 133
+#define SRST_SPI0 134
+#define SRST_P_GPIO4 135
+#define SRST_DB_GPIO4 136
+#define SRST_P_RKVENC_IOC 137
+#define SRST_H_SPDIF 138
+#define SRST_M_SPDIF 139
+#define SRST_H_PDM 140
+#define SRST_M_PDM 141
+#define SRST_P_UART1 142
+#define SRST_S_UART1 143
+#define SRST_P_UART3 144
+#define SRST_S_UART3 145
+#define SRST_P_RKVENC_GRF 146
+#define SRST_P_CAN0 147
+#define SRST_CAN0 148
+#define SRST_P_CAN1 149
+#define SRST_CAN1 150
+#define SRST_A_VO_BIU 151
+#define SRST_H_VO_BIU 152
+#define SRST_P_VO_BIU 153
+#define SRST_H_RGA2E 154
+#define SRST_A_RGA2E 155
+#define SRST_CORE_RGA2E 156
+#define SRST_H_VDPP 157
+#define SRST_A_VDPP 158
+#define SRST_CORE_VDPP 159
+#define SRST_P_VO_GRF 160
+#define SRST_P_CRU 161
+#define SRST_A_VOP_BIU 162
+#define SRST_H_VOP 163
+#define SRST_D_VOP0 164
+#define SRST_D_VOP1 165
+#define SRST_A_VOP 166
+#define SRST_P_HDMI 167
+#define SRST_HDMI 168
+#define SRST_P_HDMIPHY 169
+#define SRST_H_HDCP_KEY 170
+#define SRST_A_HDCP 171
+#define SRST_H_HDCP 172
+#define SRST_P_HDCP 173
+#define SRST_H_CVBS 174
+#define SRST_D_CVBS_VOP 175
+#define SRST_D_4X_CVBS_VOP 176
+#define SRST_A_JPEG_DECODER 177
+#define SRST_H_JPEG_DECODER 178
+#define SRST_A_VO_L_BIU 179
+#define SRST_A_MAC_VO 180
+#define SRST_A_JPEG_BIU 181
+#define SRST_H_SAI_I2S3 182
+#define SRST_M_SAI_I2S3 183
+#define SRST_MACPHY 184
+#define SRST_P_VCDCPHY 185
+#define SRST_P_GPIO2 186
+#define SRST_DB_GPIO2 187
+#define SRST_P_VO_IOC 188
+#define SRST_H_SDMMC0 189
+#define SRST_P_OTPC_NS 190
+#define SRST_SBPI_OTPC_NS 191
+#define SRST_USER_OTPC_NS 192
+#define SRST_HDMIHDP0 193
+#define SRST_H_USBHOST 194
+#define SRST_H_USBHOST_ARB 195
+#define SRST_HOST_UTMI 196
+#define SRST_P_UART4 197
+#define SRST_S_UART4 198
+#define SRST_P_I2C4 199
+#define SRST_I2C4 200
+#define SRST_P_I2C7 201
+#define SRST_I2C7 202
+#define SRST_P_USBPHY 203
+#define SRST_USBPHY_POR 204
+#define SRST_USBPHY_OTG 205
+#define SRST_USBPHY_HOST 206
+#define SRST_P_DDRPHY_CRU 207
+#define SRST_H_RKVDEC_BIU 208
+#define SRST_A_RKVDEC_BIU 209
+#define SRST_A_RKVDEC 210
+#define SRST_H_RKVDEC 211
+#define SRST_HEVC_CA_RKVDEC 212
+#define SRST_REF_PVTPLL_RKVDEC 213
+#define SRST_P_DDR_BIU 214
+#define SRST_P_DDRC 215
+#define SRST_P_DDRMON 216
+#define SRST_TIMER_DDRMON 217
+#define SRST_P_MSCH_BIU 218
+#define SRST_P_DDR_GRF 219
+#define SRST_P_DDR_HWLP 220
+#define SRST_P_DDRPHY 221
+#define SRST_MSCH_BIU 222
+#define SRST_A_DDR_UPCTL 223
+#define SRST_DDR_UPCTL 224
+#define SRST_DDRMON 225
+#define SRST_A_DDR_SCRAMBLE 226
+#define SRST_A_SPLIT 227
+#define SRST_DDR_PHY 228
+
+#endif // _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
diff --git a/include/dt-bindings/reset/rockchip,rk3562-cru.h b/include/dt-bindings/reset/rockchip,rk3562-cru.h
new file mode 100644
index 000000000000..a74471d7d2a9
--- /dev/null
+++ b/include/dt-bindings/reset/rockchip,rk3562-cru.h
@@ -0,0 +1,358 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024-2025 Rockchip Electronics Co. Ltd.
+ *
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3562_H
+#define _DT_BINDINGS_RESET_ROCKCHIP_RK3562_H
+
+/********Name=SOFTRST_CON01,Offset=0x404********/
+#define SRST_A_TOP_BIU 0
+#define SRST_A_TOP_VIO_BIU 1
+#define SRST_REF_PVTPLL_LOGIC 2
+/********Name=SOFTRST_CON03,Offset=0x40C********/
+#define SRST_NCOREPORESET0 3
+#define SRST_NCOREPORESET1 4
+#define SRST_NCOREPORESET2 5
+#define SRST_NCOREPORESET3 6
+#define SRST_NCORESET0 7
+#define SRST_NCORESET1 8
+#define SRST_NCORESET2 9
+#define SRST_NCORESET3 10
+#define SRST_NL2RESET 11
+/********Name=SOFTRST_CON04,Offset=0x410********/
+#define SRST_DAP 12
+#define SRST_P_DBG_DAPLITE 13
+#define SRST_REF_PVTPLL_CORE 14
+/********Name=SOFTRST_CON05,Offset=0x414********/
+#define SRST_A_CORE_BIU 15
+#define SRST_P_CORE_BIU 16
+#define SRST_H_CORE_BIU 17
+/********Name=SOFTRST_CON06,Offset=0x418********/
+#define SRST_A_NPU_BIU 18
+#define SRST_H_NPU_BIU 19
+#define SRST_A_RKNN 20
+#define SRST_H_RKNN 21
+#define SRST_REF_PVTPLL_NPU 22
+/********Name=SOFTRST_CON08,Offset=0x420********/
+#define SRST_A_GPU_BIU 23
+#define SRST_GPU 24
+#define SRST_REF_PVTPLL_GPU 25
+#define SRST_GPU_BRG_BIU 26
+/********Name=SOFTRST_CON09,Offset=0x424********/
+#define SRST_RKVENC_CORE 27
+#define SRST_A_VEPU_BIU 28
+#define SRST_H_VEPU_BIU 29
+#define SRST_A_RKVENC 30
+#define SRST_H_RKVENC 31
+/********Name=SOFTRST_CON10,Offset=0x428********/
+#define SRST_RKVDEC_HEVC_CA 32
+#define SRST_A_VDPU_BIU 33
+#define SRST_H_VDPU_BIU 34
+#define SRST_A_RKVDEC 35
+#define SRST_H_RKVDEC 36
+/********Name=SOFTRST_CON11,Offset=0x42C********/
+#define SRST_A_VI_BIU 37
+#define SRST_H_VI_BIU 38
+#define SRST_P_VI_BIU 39
+#define SRST_ISP 40
+#define SRST_A_VICAP 41
+#define SRST_H_VICAP 42
+#define SRST_D_VICAP 43
+#define SRST_I0_VICAP 44
+#define SRST_I1_VICAP 45
+#define SRST_I2_VICAP 46
+#define SRST_I3_VICAP 47
+/********Name=SOFTRST_CON12,Offset=0x430********/
+#define SRST_P_CSIHOST0 48
+#define SRST_P_CSIHOST1 49
+#define SRST_P_CSIHOST2 50
+#define SRST_P_CSIHOST3 51
+#define SRST_P_CSIPHY0 52
+#define SRST_P_CSIPHY1 53
+/********Name=SOFTRST_CON13,Offset=0x434********/
+#define SRST_A_VO_BIU 54
+#define SRST_H_VO_BIU 55
+#define SRST_A_VOP 56
+#define SRST_H_VOP 57
+#define SRST_D_VOP 58
+#define SRST_D_VOP1 59
+/********Name=SOFTRST_CON14,Offset=0x438********/
+#define SRST_A_RGA_BIU 60
+#define SRST_H_RGA_BIU 61
+#define SRST_A_RGA 62
+#define SRST_H_RGA 63
+#define SRST_RGA_CORE 64
+#define SRST_A_JDEC 65
+#define SRST_H_JDEC 66
+/********Name=SOFTRST_CON15,Offset=0x43C********/
+#define SRST_B_EBK_BIU 67
+#define SRST_P_EBK_BIU 68
+#define SRST_AHB2AXI_EBC 69
+#define SRST_H_EBC 70
+#define SRST_D_EBC 71
+#define SRST_H_EINK 72
+#define SRST_P_EINK 73
+/********Name=SOFTRST_CON16,Offset=0x440********/
+#define SRST_P_PHP_BIU 74
+#define SRST_A_PHP_BIU 75
+#define SRST_P_PCIE20 76
+#define SRST_PCIE20_POWERUP 77
+#define SRST_USB3OTG 78
+/********Name=SOFTRST_CON17,Offset=0x444********/
+#define SRST_PIPEPHY 79
+/********Name=SOFTRST_CON18,Offset=0x448********/
+#define SRST_A_BUS_BIU 80
+#define SRST_H_BUS_BIU 81
+#define SRST_P_BUS_BIU 82
+/********Name=SOFTRST_CON19,Offset=0x44C********/
+#define SRST_P_I2C1 83
+#define SRST_P_I2C2 84
+#define SRST_P_I2C3 85
+#define SRST_P_I2C4 86
+#define SRST_P_I2C5 87
+#define SRST_I2C1 88
+#define SRST_I2C2 89
+#define SRST_I2C3 90
+#define SRST_I2C4 91
+#define SRST_I2C5 92
+/********Name=SOFTRST_CON20,Offset=0x450********/
+#define SRST_BUS_GPIO3 93
+#define SRST_BUS_GPIO4 94
+/********Name=SOFTRST_CON21,Offset=0x454********/
+#define SRST_P_TIMER 95
+#define SRST_TIMER0 96
+#define SRST_TIMER1 97
+#define SRST_TIMER2 98
+#define SRST_TIMER3 99
+#define SRST_TIMER4 100
+#define SRST_TIMER5 101
+#define SRST_P_STIMER 102
+#define SRST_STIMER0 103
+#define SRST_STIMER1 104
+/********Name=SOFTRST_CON22,Offset=0x458********/
+#define SRST_P_WDTNS 105
+#define SRST_WDTNS 106
+#define SRST_P_GRF 107
+#define SRST_P_SGRF 108
+#define SRST_P_MAILBOX 109
+#define SRST_P_INTC 110
+#define SRST_A_BUS_GIC400 111
+#define SRST_A_BUS_GIC400_DEBUG 112
+/********Name=SOFTRST_CON23,Offset=0x45C********/
+#define SRST_A_BUS_SPINLOCK 113
+#define SRST_A_DCF 114
+#define SRST_P_DCF 115
+#define SRST_F_BUS_CM0_CORE 116
+#define SRST_T_BUS_CM0_JTAG 117
+#define SRST_H_ICACHE 118
+#define SRST_H_DCACHE 119
+/********Name=SOFTRST_CON24,Offset=0x460********/
+#define SRST_P_TSADC 120
+#define SRST_TSADC 121
+#define SRST_TSADCPHY 122
+#define SRST_P_DFT2APB 123
+/********Name=SOFTRST_CON25,Offset=0x464********/
+#define SRST_A_GMAC 124
+#define SRST_P_APB2ASB_VCCIO156 125
+#define SRST_P_DSIPHY 126
+#define SRST_P_DSITX 127
+#define SRST_P_CPU_EMA_DET 128
+#define SRST_P_HASH 129
+#define SRST_P_TOPCRU 130
+/********Name=SOFTRST_CON26,Offset=0x468********/
+#define SRST_P_ASB2APB_VCCIO156 131
+#define SRST_P_IOC_VCCIO156 132
+#define SRST_P_GPIO3_VCCIO156 133
+#define SRST_P_GPIO4_VCCIO156 134
+#define SRST_P_SARADC_VCCIO156 135
+#define SRST_SARADC_VCCIO156 136
+#define SRST_SARADC_VCCIO156_PHY 137
+/********Name=SOFTRST_CON27,Offset=0x46c********/
+#define SRST_A_MAC100 138
+
+/********Name=PMU0SOFTRST_CON00,Offset=0x10200********/
+#define SRST_P_PMU0_CRU 139
+#define SRST_P_PMU0_PMU 140
+#define SRST_PMU0_PMU 141
+#define SRST_P_PMU0_HP_TIMER 142
+#define SRST_PMU0_HP_TIMER 143
+#define SRST_PMU0_32K_HP_TIMER 144
+#define SRST_P_PMU0_PVTM 145
+#define SRST_PMU0_PVTM 146
+#define SRST_P_IOC_PMUIO 147
+#define SRST_P_PMU0_GPIO0 148
+#define SRST_PMU0_GPIO0 149
+#define SRST_P_PMU0_GRF 150
+#define SRST_P_PMU0_SGRF 151
+/********Name=PMU0SOFTRST_CON01,Offset=0x10204********/
+#define SRST_DDR_FAIL_SAFE 152
+#define SRST_P_PMU0_SCRKEYGEN 153
+/********Name=PMU0SOFTRST_CON02,Offset=0x10208********/
+#define SRST_P_PMU0_I2C0 154
+#define SRST_PMU0_I2C0 155
+
+/********Name=PMU1SOFTRST_CON00,Offset=0x18200********/
+#define SRST_P_PMU1_CRU 156
+#define SRST_H_PMU1_MEM 157
+#define SRST_H_PMU1_BIU 158
+#define SRST_P_PMU1_BIU 159
+#define SRST_P_PMU1_UART0 160
+#define SRST_S_PMU1_UART0 161
+/********Name=PMU1SOFTRST_CON01,Offset=0x18204********/
+#define SRST_P_PMU1_SPI0 162
+#define SRST_PMU1_SPI0 163
+#define SRST_P_PMU1_PWM0 164
+#define SRST_PMU1_PWM0 165
+/********Name=PMU1SOFTRST_CON02,Offset=0x18208********/
+#define SRST_F_PMU1_CM0_CORE 166
+#define SRST_T_PMU1_CM0_JTAG 167
+#define SRST_P_PMU1_WDTNS 168
+#define SRST_PMU1_WDTNS 169
+#define SRST_PMU1_MAILBOX 170
+
+/********Name=DDRSOFTRST_CON00,Offset=0x20200********/
+#define SRST_MSCH_BRG_BIU 171
+#define SRST_P_MSCH_BIU 172
+#define SRST_P_DDR_HWLP 173
+#define SRST_P_DDR_PHY 173
+#define SRST_P_DDR_DFICTL 174
+#define SRST_P_DDR_DMA2DDR 175
+/********Name=DDRSOFTRST_CON01,Offset=0x20204********/
+#define SRST_P_DDR_MON 176
+#define SRST_TM_DDR_MON 177
+#define SRST_P_DDR_GRF 178
+#define SRST_P_DDR_CRU 179
+#define SRST_P_SUBDDR_CRU 180
+
+/********Name=SUBDDRSOFTRST_CON00,Offset=0x28200********/
+#define SRST_MSCH_BIU 181
+#define SRST_DDR_PHY 182
+#define SRST_DDR_DFICTL 183
+#define SRST_DDR_SCRAMBLE 184
+#define SRST_DDR_MON 185
+#define SRST_A_DDR_SPLIT 186
+#define SRST_DDR_DMA2DDR 187
+
+/********Name=PERISOFTRST_CON01,Offset=0x30404********/
+#define SRST_A_PERI_BIU 188
+#define SRST_H_PERI_BIU 189
+#define SRST_P_PERI_BIU 190
+#define SRST_P_PERICRU 191
+/********Name=PERISOFTRST_CON02,Offset=0x30408********/
+#define SRST_H_SAI0_8CH 192
+#define SRST_M_SAI0_8CH 193
+#define SRST_H_SAI1_8CH 194
+#define SRST_M_SAI1_8CH 195
+#define SRST_H_SAI2_2CH 196
+#define SRST_M_SAI2_2CH 197
+/********Name=PERISOFTRST_CON03,Offset=0x3040C********/
+#define SRST_H_DSM 198
+#define SRST_DSM 199
+#define SRST_H_PDM 200
+#define SRST_M_PDM 201
+#define SRST_H_SPDIF 202
+#define SRST_M_SPDIF 203
+/********Name=PERISOFTRST_CON04,Offset=0x30410********/
+#define SRST_H_SDMMC0 204
+#define SRST_H_SDMMC1 205
+#define SRST_H_EMMC 206
+#define SRST_A_EMMC 207
+#define SRST_C_EMMC 208
+#define SRST_B_EMMC 209
+#define SRST_T_EMMC 210
+#define SRST_S_SFC 211
+#define SRST_H_SFC 212
+/********Name=PERISOFTRST_CON05,Offset=0x30414********/
+#define SRST_H_USB2HOST 213
+#define SRST_H_USB2HOST_ARB 214
+#define SRST_USB2HOST_UTMI 215
+/********Name=PERISOFTRST_CON06,Offset=0x30418********/
+#define SRST_P_SPI1 216
+#define SRST_SPI1 217
+#define SRST_P_SPI2 218
+#define SRST_SPI2 219
+/********Name=PERISOFTRST_CON07,Offset=0x3041C********/
+#define SRST_P_UART1 220
+#define SRST_P_UART2 221
+#define SRST_P_UART3 222
+#define SRST_P_UART4 223
+#define SRST_P_UART5 224
+#define SRST_P_UART6 225
+#define SRST_P_UART7 226
+#define SRST_P_UART8 227
+#define SRST_P_UART9 228
+#define SRST_S_UART1 229
+#define SRST_S_UART2 230
+/********Name=PERISOFTRST_CON08,Offset=0x30420********/
+#define SRST_S_UART3 231
+#define SRST_S_UART4 232
+#define SRST_S_UART5 233
+#define SRST_S_UART6 234
+#define SRST_S_UART7 235
+/********Name=PERISOFTRST_CON09,Offset=0x30424********/
+#define SRST_S_UART8 236
+#define SRST_S_UART9 237
+/********Name=PERISOFTRST_CON10,Offset=0x30428********/
+#define SRST_P_PWM1_PERI 238
+#define SRST_PWM1_PERI 239
+#define SRST_P_PWM2_PERI 240
+#define SRST_PWM2_PERI 241
+#define SRST_P_PWM3_PERI 242
+#define SRST_PWM3_PERI 243
+/********Name=PERISOFTRST_CON11,Offset=0x3042C********/
+#define SRST_P_CAN0 244
+#define SRST_CAN0 245
+#define SRST_P_CAN1 246
+#define SRST_CAN1 247
+/********Name=PERISOFTRST_CON12,Offset=0x30430********/
+#define SRST_A_CRYPTO 248
+#define SRST_H_CRYPTO 249
+#define SRST_P_CRYPTO 250
+#define SRST_CORE_CRYPTO 251
+#define SRST_PKA_CRYPTO 252
+#define SRST_H_KLAD 253
+#define SRST_P_KEY_READER 254
+#define SRST_H_RK_RNG_NS 255
+#define SRST_H_RK_RNG_S 256
+#define SRST_H_TRNG_NS 257
+#define SRST_H_TRNG_S 258
+#define SRST_H_CRYPTO_S 259
+/********Name=PERISOFTRST_CON13,Offset=0x30434********/
+#define SRST_P_PERI_WDT 260
+#define SRST_T_PERI_WDT 261
+#define SRST_A_SYSMEM 262
+#define SRST_H_BOOTROM 263
+#define SRST_P_PERI_GRF 264
+#define SRST_A_DMAC 265
+#define SRST_A_RKDMAC 267
+/********Name=PERISOFTRST_CON14,Offset=0x30438********/
+#define SRST_P_OTPC_NS 268
+#define SRST_SBPI_OTPC_NS 269
+#define SRST_USER_OTPC_NS 270
+#define SRST_P_OTPC_S 271
+#define SRST_SBPI_OTPC_S 272
+#define SRST_USER_OTPC_S 273
+#define SRST_OTPC_ARB 274
+#define SRST_P_OTPPHY 275
+#define SRST_OTP_NPOR 276
+/********Name=PERISOFTRST_CON15,Offset=0x3043C********/
+#define SRST_P_USB2PHY 277
+#define SRST_USB2PHY_POR 278
+#define SRST_USB2PHY_OTG 279
+#define SRST_USB2PHY_HOST 280
+#define SRST_P_PIPEPHY 281
+/********Name=PERISOFTRST_CON16,Offset=0x30440********/
+#define SRST_P_SARADC 282
+#define SRST_SARADC 283
+#define SRST_SARADC_PHY 284
+#define SRST_P_IOC_VCCIO234 285
+/********Name=PERISOFTRST_CON17,Offset=0x30444********/
+#define SRST_P_PERI_GPIO1 286
+#define SRST_P_PERI_GPIO2 287
+#define SRST_PERI_GPIO1 288
+#define SRST_PERI_GPIO2 289
+
+#endif
generated by cgit v1.2.3 (git 2.46.0) at 2025-08-01 08:57:43 +0000