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-rw-r--r--Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml5
-rw-r--r--Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-common.yaml7
-rw-r--r--Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-g12a-aobus.yaml3
-rw-r--r--Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-g12a-periphs.yaml3
-rw-r--r--Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-aobus.yaml4
-rw-r--r--Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml4
-rw-r--r--Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml52
-rw-r--r--Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml56
-rw-r--r--Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml120
-rw-r--r--Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt461
-rw-r--r--Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.yaml259
-rw-r--r--Documentation/devicetree/bindings/pinctrl/cypress,cy8c95x0.yaml4
-rw-r--r--Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml4
-rw-r--r--Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml2
-rw-r--r--Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.yaml2
-rw-r--r--Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml2
-rw-r--r--Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.yaml2
-rw-r--r--Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml2
-rw-r--r--Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.yaml2
-rw-r--r--Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt56
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt262
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml207
-rw-r--r--Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml8
-rw-r--r--Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml5
-rw-r--r--Documentation/devicetree/bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml135
-rw-r--r--Documentation/devicetree/bindings/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml143
-rw-r--r--Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml4
-rw-r--r--Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml4
-rw-r--r--Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml61
-rw-r--r--Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml4
-rw-r--r--Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml4
-rw-r--r--Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml4
-rw-r--r--Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml2
-rw-r--r--Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt13
-rw-r--r--Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml4
35 files changed, 927 insertions, 983 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml
index 99080c9eaac3..4e7a456ea4cc 100644
--- a/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml
@@ -15,6 +15,7 @@ allOf:
properties:
compatible:
enum:
+ - amlogic,c3-periphs-pinctrl
- amlogic,meson-a1-periphs-pinctrl
- amlogic,meson-s4-periphs-pinctrl
@@ -36,6 +37,10 @@ patternProperties:
- const: mux
- const: gpio
+ gpio-line-names:
+ minItems: 62 # A1
+ maxItems: 82 # S4
+
unevaluatedProperties:
type: object
$ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins
diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-common.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-common.yaml
index a7b29ef0bab6..e707c222a07f 100644
--- a/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-common.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-common.yaml
@@ -41,6 +41,13 @@ $defs:
gpio-ranges:
maxItems: 1
+ patternProperties:
+ "^.+-hog(-[0-9]+)?$":
+ type: object
+
+ required:
+ - gpio-hog
+
required:
- reg
- reg-names
diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-g12a-aobus.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-g12a-aobus.yaml
index 7c9c94ec5b7b..0942ea60c6cd 100644
--- a/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-g12a-aobus.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-g12a-aobus.yaml
@@ -36,6 +36,9 @@ patternProperties:
- const: ds
- const: gpio
+ gpio-line-names:
+ maxItems: 15
+
unevaluatedProperties:
type: object
$ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins
diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-g12a-periphs.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-g12a-periphs.yaml
index 4bcb8b60420f..e3c8bde30559 100644
--- a/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-g12a-periphs.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-g12a-periphs.yaml
@@ -38,6 +38,9 @@ patternProperties:
- const: mux
- const: ds
+ gpio-line-names:
+ maxItems: 85
+
unevaluatedProperties:
type: object
$ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins
diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-aobus.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-aobus.yaml
index 32d99c9b6afc..c1b03147e8ec 100644
--- a/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-aobus.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-aobus.yaml
@@ -44,6 +44,10 @@ patternProperties:
- const: pull
- const: gpio
+ gpio-line-names:
+ minItems: 11 # GXL
+ maxItems: 16 # Meson8
+
unevaluatedProperties:
type: object
$ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins
diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml
index d0441051f34a..4ec85b8248fa 100644
--- a/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml
@@ -45,6 +45,10 @@ patternProperties:
- const: pull-enable
- const: gpio
+ gpio-line-names:
+ minItems: 86 # AXG
+ maxItems: 120 # Meson8
+
unevaluatedProperties:
type: object
$ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins
diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml
index bef85c25cdef..37c0a74c7c01 100644
--- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml
@@ -25,30 +25,32 @@ properties:
reg:
maxItems: 2
-patternProperties:
- '^.*$':
- if:
- type: object
- then:
- patternProperties:
- "^function|groups$":
- $ref: /schemas/types.yaml#/definitions/string
- enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
- ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT,
- EXTRST, FLACK, FLBUSY, FLWP, GPID, GPID0, GPID2, GPID4, GPID6, GPIE0,
- GPIE2, GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4,
- I2C5, I2C6, I2C7, I2C8, I2C9, LPCPD, LPCPME, LPCRST, LPCSMI, MAC1LINK,
- MAC2LINK, MDIO1, MDIO2, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2,
- NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4,
- NDTS4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, OSCCLK, PWM0,
- PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1,
- RMII2, ROM16, ROM8, ROMCS1, ROMCS2, ROMCS3, ROMCS4, RXD1, RXD2, RXD3,
- RXD4, SALT1, SALT2, SALT3, SALT4, SD1, SD2, SGPMCK, SGPMI, SGPMLD,
- SGPMO, SGPSCK, SGPSI0, SGPSI1, SGPSLD, SIOONCTRL, SIOPBI, SIOPBO,
- SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1DEBUG, SPI1PASSTHRU,
- SPICS1, TIMER3, TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, TXD2,
- TXD3, TXD4, UART6, USB11D1, USB11H2, USB2D1, USB2H1, USBCKI, VGABIOS_ROM,
- VGAHS, VGAVS, VPI18, VPI24, VPI30, VPO12, VPO24, WDTRST1, WDTRST2]
+additionalProperties:
+ $ref: pinmux-node.yaml#
+ additionalProperties: false
+
+ properties:
+ pins: true
+ bias-disable: true
+
+ patternProperties:
+ "^function|groups$":
+ enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
+ ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT,
+ EXTRST, FLACK, FLBUSY, FLWP, GPID, GPID0, GPID2, GPID4, GPID6, GPIE0,
+ GPIE2, GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4,
+ I2C5, I2C6, I2C7, I2C8, I2C9, LPCPD, LPCPME, LPCRST, LPCSMI, MAC1LINK,
+ MAC2LINK, MDIO1, MDIO2, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2,
+ NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4,
+ NDTS4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, OSCCLK, PWM0,
+ PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1,
+ RMII2, ROM16, ROM8, ROMCS1, ROMCS2, ROMCS3, ROMCS4, RXD1, RXD2, RXD3,
+ RXD4, SALT1, SALT2, SALT3, SALT4, SD1, SD2, SGPMCK, SGPMI, SGPMLD,
+ SGPMO, SGPSCK, SGPSI0, SGPSI1, SGPSLD, SIOONCTRL, SIOPBI, SIOPBO,
+ SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1DEBUG, SPI1PASSTHRU,
+ SPICS1, TIMER3, TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, TXD2,
+ TXD3, TXD4, UART6, USB11D1, USB11H2, USB2D1, USB2H1, USBCKI, VGABIOS_ROM,
+ VGAHS, VGAVS, VPI18, VPI24, VPI30, VPO12, VPO24, WDTRST1, WDTRST2]
allOf:
- $ref: pinctrl.yaml#
@@ -56,8 +58,6 @@ allOf:
required:
- compatible
-additionalProperties: false
-
examples:
- |
syscon: scu@1e6e2000 {
diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml
index 14c391f16899..863da5d80826 100644
--- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml
@@ -37,32 +37,34 @@ properties:
0: compatible with "aspeed,ast2500-gfx", "syscon"
1: compatible with "aspeed,ast2500-lhc", "syscon"
-patternProperties:
- '^.*$':
- if:
- type: object
- then:
- patternProperties:
- "^function|groups$":
- $ref: /schemas/types.yaml#/definitions/string
- enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
- ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT,
- ESPI, FWSPICS1, FWSPICS2, GPID0, GPID2, GPID4, GPID6, GPIE0, GPIE2,
- GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4, I2C5,
- I2C6, I2C7, I2C8, I2C9, LAD0, LAD1, LAD2, LAD3, LCLK, LFRAME, LPCHC,
- LPCPD, LPCPLUS, LPCPME, LPCRST, LPCSMI, LSIRQ, MAC1LINK, MAC2LINK,
- MDIO1, MDIO2, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4,
- NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2,
- NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PNOR, PWM0,
- PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1,
- RMII2, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13,
- SALT14, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, SALT9, SCL1,
- SCL2, SD1, SD2, SDA1, SDA2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, SIOPBO,
- SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1CS1, SPI1DEBUG,
- SPI1PASSTHRU, SPI2CK, SPI2CS0, SPI2CS1, SPI2MISO, SPI2MOSI, TIMER3,
- TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, TXD2, TXD3, TXD4, UART6,
- USB11BHID, USB2AD, USB2AH, USB2BD, USB2BH, USBCKI, VGABIOSROM, VGAHS,
- VGAVS, VPI24, VPO, WDTRST1, WDTRST2]
+additionalProperties:
+ $ref: pinmux-node.yaml#
+ additionalProperties: false
+
+ properties:
+ pins: true
+ bias-disable: true
+
+ patternProperties:
+ "^function|groups$":
+ enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15,
+ ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT,
+ ESPI, FWSPICS1, FWSPICS2, GPID0, GPID2, GPID4, GPID6, GPIE0, GPIE2,
+ GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4, I2C5,
+ I2C6, I2C7, I2C8, I2C9, LAD0, LAD1, LAD2, LAD3, LCLK, LFRAME, LPCHC,
+ LPCPD, LPCPLUS, LPCPME, LPCRST, LPCSMI, LSIRQ, MAC1LINK, MAC2LINK,
+ MDIO1, MDIO2, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4,
+ NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2,
+ NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PNOR, PWM0,
+ PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1,
+ RMII2, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13,
+ SALT14, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, SALT9, SCL1,
+ SCL2, SD1, SD2, SDA1, SDA2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, SIOPBO,
+ SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1CS1, SPI1DEBUG,
+ SPI1PASSTHRU, SPI2CK, SPI2CS0, SPI2CS1, SPI2MISO, SPI2MOSI, TIMER3,
+ TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, TXD2, TXD3, TXD4, UART6,
+ USB11BHID, USB2AD, USB2AH, USB2BD, USB2BH, USBCKI, VGABIOSROM, VGAHS,
+ VGAVS, VPI24, VPO, WDTRST1, WDTRST2]
allOf:
- $ref: pinctrl.yaml#
@@ -71,8 +73,6 @@ required:
- compatible
- aspeed,external-nodes
-additionalProperties: false
-
examples:
- |
#include <dt-bindings/clock/aspeed-clock.h>
diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
index 859a1889dc1e..612464aef98b 100644
--- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
@@ -23,65 +23,65 @@ properties:
compatible:
const: aspeed,ast2600-pinctrl
-patternProperties:
- '^.*$':
- if:
- type: object
- then:
- properties:
- function:
- $ref: /schemas/types.yaml#/definitions/string
- enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2,
- ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMC, ESPI, ESPIALT,
- FSI1, FSI2, FWQSPI, FWSPIABR, FWSPID, FWSPIWP, GPIT0, GPIT1, GPIT2, GPIT3,
- GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, GPIU2, GPIU3, GPIU4, GPIU5,
- GPIU6, GPIU7, I2C1, I2C10, I2C11, I2C12, I2C13, I2C14, I2C15, I2C16,
- I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5,
- I3C6, JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ,
- MACLINK1, MACLINK2, MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4,
- NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2,
- NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4,
- NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PWM0, PWM1, PWM10, PWM11,
- PWM12, PWM13, PWM14, PWM15, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, PWM8,
- PWM9, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4,
- RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13, SALT14,
- SALT15, SALT16, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8,
- SALT9, SD1, SD2, SGPM1, SGPM2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, SIOPBO,
- SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1WP, SPI2,
- SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, TACH12, TACH13, TACH14,
- TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0,
- THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12,
- UART13, UART6, UART7, UART8, UART9, USBAD, USBADP, USB2AH, USB2AHP,
- USB2BD, USB2BH, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4 ]
-
- groups:
- $ref: /schemas/types.yaml#/definitions/string
- enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2,
- ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMCG1, EMMCG4,
- EMMCG8, ESPI, ESPIALT, FSI1, FSI2, FWQSPI, FWSPIABR, FWSPID, FWSPIWP,
- GPIT0, GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1,
- GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, HVI3C3, HVI3C4, I2C1, I2C10,
- I2C11, I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5,
- I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ,
- LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2, MACLINK3,
- MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2, NCTS3, NCTS4,
- NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2,
- NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4,
- OSCCLK, PEWAKE, PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1, PWM12G0,
- PWM12G1, PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0, PWM15G1, PWM2,
- PWM3, PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1, PWM9G0, PWM9G1, QSPI1,
- QSPI2, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4,
- RXD1, RXD2, RXD3, RXD4, SALT1, SALT10G0, SALT10G1, SALT11G0, SALT11G1,
- SALT12G0, SALT12G1, SALT13G0, SALT13G1, SALT14G0, SALT14G1, SALT15G0,
- SALT15G1, SALT16G0, SALT16G1, SALT2, SALT3, SALT4, SALT5, SALT6,
- SALT7, SALT8, SALT9G0, SALT9G1, SD1, SD2, SD3, SGPM1, SGPM2, SGPS1, SGPS2,
- SIOONCTRL, SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1,
- SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11,
- TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6,
- TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3,
- TXD4, UART10, UART11, UART12G0, UART12G1, UART13G0, UART13G1, UART6,
- UART7, UART8, UART9, USBA, USBB, VB, VGAHS, VGAVS, WDTRST1, WDTRST2,
- WDTRST3, WDTRST4]
+additionalProperties:
+ $ref: pinmux-node.yaml#
+ additionalProperties: false
+
+ properties:
+ function:
+ enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2,
+ ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMC, ESPI, ESPIALT,
+ FSI1, FSI2, FWQSPI, FWSPIABR, FWSPID, FWSPIWP, GPIT0, GPIT1, GPIT2, GPIT3,
+ GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, GPIU2, GPIU3, GPIU4, GPIU5,
+ GPIU6, GPIU7, I2C1, I2C10, I2C11, I2C12, I2C13, I2C14, I2C15, I2C16,
+ I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5,
+ I3C6, JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ,
+ MACLINK1, MACLINK2, MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4,
+ NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2,
+ NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4,
+ NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PWM0, PWM1, PWM10, PWM11,
+ PWM12, PWM13, PWM14, PWM15, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, PWM8,
+ PWM9, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4,
+ RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13, SALT14,
+ SALT15, SALT16, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8,
+ SALT9, SD1, SD2, SGPM1, SGPM2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, SIOPBO,
+ SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1WP, SPI2,
+ SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, TACH12, TACH13, TACH14,
+ TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0,
+ THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12,
+ UART13, UART6, UART7, UART8, UART9, USBAD, USBADP, USB2AH, USB2AHP,
+ USB2BD, USB2BH, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, WDTRST4 ]
+
+ groups:
+ enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, ADC2,
+ ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, EMMCG1, EMMCG4,
+ EMMCG8, ESPI, ESPIALT, FSI1, FSI2, FWQSPI, FWSPIABR, FWSPID, FWSPIWP,
+ GPIT0, GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1,
+ GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, HVI3C3, HVI3C4, I2C1, I2C10,
+ I2C11, I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5,
+ I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ,
+ LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2, MACLINK3,
+ MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2, NCTS3, NCTS4,
+ NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2,
+ NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4,
+ OSCCLK, PEWAKE, PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1, PWM12G0,
+ PWM12G1, PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0, PWM15G1, PWM2,
+ PWM3, PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1, PWM9G0, PWM9G1, QSPI1,
+ QSPI2, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4,
+ RXD1, RXD2, RXD3, RXD4, SALT1, SALT10G0, SALT10G1, SALT11G0, SALT11G1,
+ SALT12G0, SALT12G1, SALT13G0, SALT13G1, SALT14G0, SALT14G1, SALT15G0,
+ SALT15G1, SALT16G0, SALT16G1, SALT2, SALT3, SALT4, SALT5, SALT6,
+ SALT7, SALT8, SALT9G0, SALT9G1, SD1, SD2, SD3, SGPM1, SGPM2, SGPS1, SGPS2,
+ SIOONCTRL, SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1,
+ SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11,
+ TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6,
+ TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3,
+ TXD4, UART10, UART11, UART12G0, UART12G1, UART13G0, UART13G1, UART6,
+ UART7, UART8, UART9, USBA, USBB, VB, VGAHS, VGAVS, WDTRST1, WDTRST2,
+ WDTRST3, WDTRST4]
+
+ pins: true
+ bias-disable: true
allOf:
- $ref: pinctrl.yaml#
@@ -89,8 +89,6 @@ allOf:
required:
- compatible
-additionalProperties: false
-
examples:
- |
syscon: scu@1e6e2000 {
diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt
deleted file mode 100644
index e047a198db38..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt
+++ /dev/null
@@ -1,461 +0,0 @@
-Broadcom BCM281xx Pin Controller
-
-This is a pin controller for the Broadcom BCM281xx SoC family, which includes
-BCM11130, BCM11140, BCM11351, BCM28145, and BCM28155 SoCs.
-
-=== Pin Controller Node ===
-
-Required Properties:
-
-- compatible: Must be "brcm,bcm11351-pinctrl"
-- reg: Base address of the PAD Controller register block and the size
- of the block.
-
-For example, the following is the bare minimum node:
-
- pinctrl@35004800 {
- compatible = "brcm,bcm11351-pinctrl";
- reg = <0x35004800 0x430>;
- };
-
-As a pin controller device, in addition to the required properties, this node
-should also contain the pin configuration nodes that client devices reference,
-if any.
-
-=== Pin Configuration Node ===
-
-Each pin configuration node is a sub-node of the pin controller node and is a
-container of an arbitrary number of subnodes, called pin group nodes in this
-document.
-
-Please refer to the pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices, including the definition of a
-"pin configuration node".
-
-=== Pin Group Node ===
-
-A pin group node specifies the desired pin mux and/or pin configuration for an
-arbitrary number of pins. The name of the pin group node is optional and not
-used.
-
-A pin group node only affects the properties specified in the node, and has no
-effect on any properties that are omitted.
-
-The pin group node accepts a subset of the generic pin config properties. For
-details generic pin config properties, please refer to pinctrl-bindings.txt
-and <include/linux/pinctrl/pinconfig-generic.h>.
-
-Each pin controlled by this pin controller belong to one of three types:
-Standard, I2C, and HDMI. Each type accepts a different set of pin config
-properties. A list of pins and their types is provided below.
-
-Required Properties (applicable to all pins):
-
-- pins: Multiple strings. Specifies the name(s) of one or more pins to
- be configured by this node.
-
-Optional Properties (for standard pins):
-
-- function: String. Specifies the pin mux selection. Values
- must be one of: "alt1", "alt2", "alt3", "alt4"
-- input-schmitt-enable: No arguments. Enable schmitt-trigger mode.
-- input-schmitt-disable: No arguments. Disable schmitt-trigger mode.
-- bias-pull-up: No arguments. Pull up on pin.
-- bias-pull-down: No arguments. Pull down on pin.
-- bias-disable: No arguments. Disable pin bias.
-- slew-rate: Integer. Meaning depends on configured pin mux:
- *_SCL or *_SDA:
- 0: Standard(100kbps)& Fast(400kbps) mode
- 1: Highspeed (3.4Mbps) mode
- IC_DM or IC_DP:
- 0: normal slew rate
- 1: fast slew rate
- Otherwise:
- 0: fast slew rate
- 1: normal slew rate
-- input-enable: No arguments. Enable input (does not affect
- output.)
-- input-disable: No arguments. Disable input (does not affect
- output.)
-- drive-strength: Integer. Drive strength in mA. Valid values are
- 2, 4, 6, 8, 10, 12, 14, 16 mA.
-
-Optional Properties (for I2C pins):
-
-- function: String. Specifies the pin mux selection. Values
- must be one of: "alt1", "alt2", "alt3", "alt4"
-- bias-pull-up: Integer. Pull up strength in Ohm. There are 3
- pull-up resistors (1.2k, 1.8k, 2.7k) available
- in parallel for I2C pins, so the valid values
- are: 568, 720, 831, 1080, 1200, 1800, 2700 Ohm.
-- bias-disable: No arguments. Disable pin bias.
-- slew-rate: Integer. Meaning depends on configured pin mux:
- *_SCL or *_SDA:
- 0: Standard(100kbps)& Fast(400kbps) mode
- 1: Highspeed (3.4Mbps) mode
- IC_DM or IC_DP:
- 0: normal slew rate
- 1: fast slew rate
- Otherwise:
- 0: fast slew rate
- 1: normal slew rate
-- input-enable: No arguments. Enable input (does not affect
- output.)
-- input-disable: No arguments. Disable input (does not affect
- output.)
-
-Optional Properties (for HDMI pins):
-
-- function: String. Specifies the pin mux selection. Values
- must be one of: "alt1", "alt2", "alt3", "alt4"
-- slew-rate: Integer. Controls slew rate.
- 0: Standard(100kbps)& Fast(400kbps) mode
- 1: Highspeed (3.4Mbps) mode
-- input-enable: No arguments. Enable input (does not affect
- output.)
-- input-disable: No arguments. Disable input (does not affect
- output.)
-
-Example:
-// pin controller node
-pinctrl@35004800 {
- compatible = "brcm,bcm11351-pinctrl";
- reg = <0x35004800 0x430>;
-
- // pin configuration node
- dev_a_default: dev_a_active {
- //group node defining 1 standard pin
- grp_1 {
- pins = "std_pin1";
- function = "alt1";
- input-schmitt-enable;
- bias-disable;
- slew-rate = <1>;
- drive-strength = <4>;
- };
-
- // group node defining 2 I2C pins
- grp_2 {
- pins = "i2c_pin1", "i2c_pin2";
- function = "alt2";
- bias-pull-up = <720>;
- input-enable;
- };
-
- // group node defining 2 HDMI pins
- grp_3 {
- pins = "hdmi_pin1", "hdmi_pin2";
- function = "alt3";
- slew-rate = <1>;
- };
-
- // other pin group nodes
- ...
- };
-
- // other pin configuration nodes
- ...
-};
-
-In the example above, "dev_a_active" is a pin configuration node with a number
-of sub-nodes. In the pin group node "grp_1", one pin, "std_pin1", is defined in
-the "pins" property. Thus, the remaining properties in the "grp_1" node applies
-only to this pin, including the following settings:
- - setting pinmux to "alt1"
- - enabling schmitt-trigger (hystersis) mode
- - disabling pin bias
- - setting the slew-rate to 1
- - setting the drive strength to 4 mA
-Note that neither "input-enable" nor "input-disable" was specified - the pinctrl
-subsystem will therefore leave this property unchanged from whatever state it
-was in before applying these changes.
-
-The "pins" property in the pin group node "grp_2" specifies two pins -
-"i2c_pin1" and "i2c_pin2"; the remaining properties in this pin group node,
-therefore, applies to both of these pins. The properties include:
- - setting pinmux to "alt2"
- - setting pull-up resistance to 720 Ohm (ie. enabling 1.2k and 1.8k resistors
- in parallel)
- - enabling both pins' input
-"slew-rate" is not specified in this pin group node, so the slew-rate for these
-pins are left as-is.
-
-Finally, "grp_3" defines two HDMI pins. The following properties are applied to
-both pins:
- - setting pinmux to "alt3"
- - setting slew-rate to 1; for HDMI pins, this corresponds to the 3.4 Mbps
- Highspeed mode
-The input is neither enabled or disabled, and is left untouched.
-
-=== Pin Names and Type ===
-
-The following are valid pin names and their pin types:
-
- "adcsync", Standard
- "bat_rm", Standard
- "bsc1_scl", I2C
- "bsc1_sda", I2C
- "bsc2_scl", I2C
- "bsc2_sda", I2C
- "classgpwr", Standard
- "clk_cx8", Standard
- "clkout_0", Standard
- "clkout_1", Standard
- "clkout_2", Standard
- "clkout_3", Standard
- "clkreq_in_0", Standard
- "clkreq_in_1", Standard
- "cws_sys_req1", Standard
- "cws_sys_req2", Standard
- "cws_sys_req3", Standard
- "digmic1_clk", Standard
- "digmic1_dq", Standard
- "digmic2_clk", Standard
- "digmic2_dq", Standard
- "gpen13", Standard
- "gpen14", Standard
- "gpen15", Standard
- "gpio00", Standard
- "gpio01", Standard
- "gpio02", Standard
- "gpio03", Standard
- "gpio04", Standard
- "gpio05", Standard
- "gpio06", Standard
- "gpio07", Standard
- "gpio08", Standard
- "gpio09", Standard
- "gpio10", Standard
- "gpio11", Standard
- "gpio12", Standard
- "gpio13", Standard
- "gpio14", Standard
- "gps_pablank", Standard
- "gps_tmark", Standard
- "hdmi_scl", HDMI
- "hdmi_sda", HDMI
- "ic_dm", Standard
- "ic_dp", Standard
- "kp_col_ip_0", Standard
- "kp_col_ip_1", Standard
- "kp_col_ip_2", Standard
- "kp_col_ip_3", Standard
- "kp_row_op_0", Standard
- "kp_row_op_1", Standard
- "kp_row_op_2", Standard
- "kp_row_op_3", Standard
- "lcd_b_0", Standard
- "lcd_b_1", Standard
- "lcd_b_2", Standard
- "lcd_b_3", Standard
- "lcd_b_4", Standard
- "lcd_b_5", Standard
- "lcd_b_6", Standard
- "lcd_b_7", Standard
- "lcd_g_0", Standard
- "lcd_g_1", Standard
- "lcd_g_2", Standard
- "lcd_g_3", Standard
- "lcd_g_4", Standard
- "lcd_g_5", Standard
- "lcd_g_6", Standard
- "lcd_g_7", Standard
- "lcd_hsync", Standard
- "lcd_oe", Standard
- "lcd_pclk", Standard
- "lcd_r_0", Standard
- "lcd_r_1", Standard
- "lcd_r_2", Standard
- "lcd_r_3", Standard
- "lcd_r_4", Standard
- "lcd_r_5", Standard
- "lcd_r_6", Standard
- "lcd_r_7", Standard
- "lcd_vsync", Standard
- "mdmgpio0", Standard
- "mdmgpio1", Standard
- "mdmgpio2", Standard
- "mdmgpio3", Standard
- "mdmgpio4", Standard
- "mdmgpio5", Standard
- "mdmgpio6", Standard
- "mdmgpio7", Standard
- "mdmgpio8", Standard
- "mphi_data_0", Standard
- "mphi_data_1", Standard
- "mphi_data_2", Standard
- "mphi_data_3", Standard
- "mphi_data_4", Standard
- "mphi_data_5", Standard
- "mphi_data_6", Standard
- "mphi_data_7", Standard
- "mphi_data_8", Standard
- "mphi_data_9", Standard
- "mphi_data_10", Standard
- "mphi_data_11", Standard
- "mphi_data_12", Standard
- "mphi_data_13", Standard
- "mphi_data_14", Standard
- "mphi_data_15", Standard
- "mphi_ha0", Standard
- "mphi_hat0", Standard
- "mphi_hat1", Standard
- "mphi_hce0_n", Standard
- "mphi_hce1_n", Standard
- "mphi_hrd_n", Standard
- "mphi_hwr_n", Standard
- "mphi_run0", Standard
- "mphi_run1", Standard
- "mtx_scan_clk", Standard
- "mtx_scan_data", Standard
- "nand_ad_0", Standard
- "nand_ad_1", Standard
- "nand_ad_2", Standard
- "nand_ad_3", Standard
- "nand_ad_4", Standard
- "nand_ad_5", Standard
- "nand_ad_6", Standard
- "nand_ad_7", Standard
- "nand_ale", Standard
- "nand_cen_0", Standard
- "nand_cen_1", Standard
- "nand_cle", Standard
- "nand_oen", Standard
- "nand_rdy_0", Standard
- "nand_rdy_1", Standard
- "nand_wen", Standard
- "nand_wp", Standard
- "pc1", Standard
- "pc2", Standard
- "pmu_int", Standard
- "pmu_scl", I2C
- "pmu_sda", I2C
- "rfst2g_mtsloten3g", Standard
- "rgmii_0_rx_ctl", Standard
- "rgmii_0_rxc", Standard
- "rgmii_0_rxd_0", Standard
- "rgmii_0_rxd_1", Standard
- "rgmii_0_rxd_2", Standard
- "rgmii_0_rxd_3", Standard
- "rgmii_0_tx_ctl", Standard
- "rgmii_0_txc", Standard
- "rgmii_0_txd_0", Standard
- "rgmii_0_txd_1", Standard
- "rgmii_0_txd_2", Standard
- "rgmii_0_txd_3", Standard
- "rgmii_1_rx_ctl", Standard
- "rgmii_1_rxc", Standard
- "rgmii_1_rxd_0", Standard
- "rgmii_1_rxd_1", Standard
- "rgmii_1_rxd_2", Standard
- "rgmii_1_rxd_3", Standard
- "rgmii_1_tx_ctl", Standard
- "rgmii_1_txc", Standard
- "rgmii_1_txd_0", Standard
- "rgmii_1_txd_1", Standard
- "rgmii_1_txd_2", Standard
- "rgmii_1_txd_3", Standard
- "rgmii_gpio_0", Standard
- "rgmii_gpio_1", Standard
- "rgmii_gpio_2", Standard
- "rgmii_gpio_3", Standard
- "rtxdata2g_txdata3g1", Standard
- "rtxen2g_txdata3g2", Standard
- "rxdata3g0", Standard
- "rxdata3g1", Standard
- "rxdata3g2", Standard
- "sdio1_clk", Standard
- "sdio1_cmd", Standard
- "sdio1_data_0", Standard
- "sdio1_data_1", Standard
- "sdio1_data_2", Standard
- "sdio1_data_3", Standard
- "sdio4_clk", Standard
- "sdio4_cmd", Standard
- "sdio4_data_0", Standard
- "sdio4_data_1", Standard
- "sdio4_data_2", Standard
- "sdio4_data_3", Standard
- "sim_clk", Standard
- "sim_data", Standard
- "sim_det", Standard
- "sim_resetn", Standard
- "sim2_clk", Standard
- "sim2_data", Standard
- "sim2_det", Standard
- "sim2_resetn", Standard
- "sri_c", Standard
- "sri_d", Standard
- "sri_e", Standard
- "ssp_extclk", Standard
- "ssp0_clk", Standard
- "ssp0_fs", Standard
- "ssp0_rxd", Standard
- "ssp0_txd", Standard
- "ssp2_clk", Standard
- "ssp2_fs_0", Standard
- "ssp2_fs_1", Standard
- "ssp2_fs_2", Standard
- "ssp2_fs_3", Standard
- "ssp2_rxd_0", Standard
- "ssp2_rxd_1", Standard
- "ssp2_txd_0", Standard
- "ssp2_txd_1", Standard
- "ssp3_clk", Standard
- "ssp3_fs", Standard
- "ssp3_rxd", Standard
- "ssp3_txd", Standard
- "ssp4_clk", Standard
- "ssp4_fs", Standard
- "ssp4_rxd", Standard
- "ssp4_txd", Standard
- "ssp5_clk", Standard
- "ssp5_fs", Standard
- "ssp5_rxd", Standard
- "ssp5_txd", Standard
- "ssp6_clk", Standard
- "ssp6_fs", Standard
- "ssp6_rxd", Standard
- "ssp6_txd", Standard
- "stat_1", Standard
- "stat_2", Standard
- "sysclken", Standard
- "traceclk", Standard
- "tracedt00", Standard
- "tracedt01", Standard
- "tracedt02", Standard
- "tracedt03", Standard
- "tracedt04", Standard
- "tracedt05", Standard
- "tracedt06", Standard
- "tracedt07", Standard
- "tracedt08", Standard
- "tracedt09", Standard
- "tracedt10", Standard
- "tracedt11", Standard
- "tracedt12", Standard
- "tracedt13", Standard
- "tracedt14", Standard
- "tracedt15", Standard
- "txdata3g0", Standard
- "txpwrind", Standard
- "uartb1_ucts", Standard
- "uartb1_urts", Standard
- "uartb1_urxd", Standard
- "uartb1_utxd", Standard
- "uartb2_urxd", Standard
- "uartb2_utxd", Standard
- "uartb3_ucts", Standard
- "uartb3_urts", Standard
- "uartb3_urxd", Standard
- "uartb3_utxd", Standard
- "uartb4_ucts", Standard
- "uartb4_urts", Standard
- "uartb4_urxd", Standard
- "uartb4_utxd", Standard
- "vc_cam1_scl", I2C
- "vc_cam1_sda", I2C
- "vc_cam2_scl", I2C
- "vc_cam2_sda", I2C
- "vc_cam3_scl", I2C
- "vc_cam3_sda", I2C
diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.yaml
new file mode 100644
index 000000000000..90c275295199
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.yaml
@@ -0,0 +1,259 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/brcm,bcm11351-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM281xx pin controller
+
+maintainers:
+ - Florian Fainelli <florian.fainelli@broadcom.com>
+ - Ray Jui <rjui@broadcom.com>
+ - Scott Branden <sbranden@broadcom.com>
+
+allOf:
+ - $ref: pinctrl.yaml#
+
+properties:
+ compatible:
+ const: brcm,bcm11351-pinctrl
+
+ reg:
+ maxItems: 1
+
+patternProperties:
+ '-pins$':
+ type: object
+ additionalProperties: false
+
+ patternProperties:
+ '-grp[0-9]$':
+ type: object
+ unevaluatedProperties: false
+
+ properties:
+ pins:
+ description:
+ Specifies the name(s) of one or more pins to be configured by
+ this node.
+ items:
+ enum: [ adcsync, bat_rm, bsc1_scl, bsc1_sda, bsc2_scl, bsc2_sda,
+ classgpwr, clk_cx8, clkout_0, clkout_1, clkout_2,
+ clkout_3, clkreq_in_0, clkreq_in_1, cws_sys_req1,
+ cws_sys_req2, cws_sys_req3, digmic1_clk, digmic1_dq,
+ digmic2_clk, digmic2_dq, gpen13, gpen14, gpen15, gpio00,
+ gpio01, gpio02, gpio03, gpio04, gpio05, gpio06, gpio07,
+ gpio08, gpio09, gpio10, gpio11, gpio12, gpio13, gpio14,
+ gps_pablank, gps_tmark, hdmi_scl, hdmi_sda, ic_dm, ic_dp,
+ kp_col_ip_0, kp_col_ip_1, kp_col_ip_2, kp_col_ip_3,
+ kp_row_op_0, kp_row_op_1, kp_row_op_2, kp_row_op_3,
+ lcd_b_0, lcd_b_1, lcd_b_2, lcd_b_3, lcd_b_4, lcd_b_5,
+ lcd_b_6, lcd_b_7, lcd_g_0, lcd_g_1, lcd_g_2, lcd_g_3,
+ lcd_g_4, lcd_g_5, lcd_g_6, lcd_g_7, lcd_hsync, lcd_oe,
+ lcd_pclk, lcd_r_0, lcd_r_1, lcd_r_2, lcd_r_3, lcd_r_4,
+ lcd_r_5, lcd_r_6, lcd_r_7, lcd_vsync, mdmgpio0, mdmgpio1,
+ mdmgpio2, mdmgpio3, mdmgpio4, mdmgpio5, mdmgpio6,
+ mdmgpio7, mdmgpio8, mphi_data_0, mphi_data_1, mphi_data_2,
+ mphi_data_3, mphi_data_4, mphi_data_5, mphi_data_6,
+ mphi_data_7, mphi_data_8, mphi_data_9, mphi_data_10,
+ mphi_data_11, mphi_data_12, mphi_data_13, mphi_data_14,
+ mphi_data_15, mphi_ha0, mphi_hat0, mphi_hat1, mphi_hce0_n,
+ mphi_hce1_n, mphi_hrd_n, mphi_hwr_n, mphi_run0, mphi_run1,
+ mtx_scan_clk, mtx_scan_data, nand_ad_0, nand_ad_1,
+ nand_ad_2, nand_ad_3, nand_ad_4, nand_ad_5, nand_ad_6,
+ nand_ad_7, nand_ale, nand_cen_0, nand_cen_1, nand_cle,
+ nand_oen, nand_rdy_0, nand_rdy_1, nand_wen, nand_wp, pc1,
+ pc2, pmu_int, pmu_scl, pmu_sda, rfst2g_mtsloten3g,
+ rgmii_0_rx_ctl, rgmii_0_rxc, rgmii_0_rxd_0, rgmii_0_rxd_1,
+ rgmii_0_rxd_2, rgmii_0_rxd_3, rgmii_0_tx_ctl, rgmii_0_txc,
+ rgmii_0_txd_0, rgmii_0_txd_1, rgmii_0_txd_2,
+ rgmii_0_txd_3, rgmii_1_rx_ctl, rgmii_1_rxc, rgmii_1_rxd_0,
+ rgmii_1_rxd_1, rgmii_1_rxd_2, rgmii_1_rxd_3,
+ rgmii_1_tx_ctl, rgmii_1_txc, rgmii_1_txd_0, rgmii_1_txd_1,
+ rgmii_1_txd_2, rgmii_1_txd_3, rgmii_gpio_0, rgmii_gpio_1,
+ rgmii_gpio_2, rgmii_gpio_3, rtxdata2g_txdata3g1,
+ rtxen2g_txdata3g2, rxdata3g0, rxdata3g1, rxdata3g2,
+ sdio1_clk, sdio1_cmd, sdio1_data_0, sdio1_data_1,
+ sdio1_data_2, sdio1_data_3, sdio4_clk, sdio4_cmd,
+ sdio4_data_0, sdio4_data_1, sdio4_data_2, sdio4_data_3,
+ sim_clk, sim_data, sim_det, sim_resetn, sim2_clk,
+ sim2_data, sim2_det, sim2_resetn, sri_c, sri_d, sri_e,
+ ssp_extclk, ssp0_clk, ssp0_fs, ssp0_rxd, ssp0_txd,
+ ssp2_clk, ssp2_fs_0, ssp2_fs_1, ssp2_fs_2, ssp2_fs_3,
+ ssp2_rxd_0, ssp2_rxd_1, ssp2_txd_0, ssp2_txd_1, ssp3_clk,
+ ssp3_fs, ssp3_rxd, ssp3_txd, ssp4_clk, ssp4_fs, ssp4_rxd,
+ ssp4_txd, ssp5_clk, ssp5_fs, ssp5_rxd, ssp5_txd, ssp6_clk,
+ ssp6_fs, ssp6_rxd, ssp6_txd, stat_1, stat_2, sysclken,
+ traceclk, tracedt00, tracedt01, tracedt02, tracedt03,
+ tracedt04, tracedt05, tracedt06, tracedt07, tracedt08
+ tracedt09, tracedt10, tracedt11, tracedt12, tracedt13
+ tracedt14, tracedt15, txdata3g0, txpwrind, uartb1_ucts,
+ uartb1_urts, uartb1_urxd, uartb1_utxd, uartb2_urxd,
+ uartb2_utxd, uartb3_ucts, uartb3_urts, uartb3_urxd,
+ uartb3_utxd, uartb4_ucts, uartb4_urts, uartb4_urxd,
+ uartb4_utxd, vc_cam1_scl, vc_cam1_sda, vc_cam2_scl,
+ vc_cam2_sda, vc_cam3_scl, vc_cam3_sda ]
+
+ function:
+ description:
+ Specifies the pin mux selection.
+ enum: [ alt1, alt2, alt3, alt4 ]
+
+ slew-rate:
+ description: |
+ Meaning depends on configured pin mux:
+ *_scl or *_sda:
+ 0: Standard (100 kbps) & Fast (400 kbps) mode
+ 1: Highspeed (3.4 Mbps) mode
+ ic_dm or ic_dp:
+ 0: normal slew rate
+ 1: fast slew rate
+ Otherwise:
+ 0: fast slew rate
+ 1: normal slew rate
+
+ bias-disable: true
+ input-disable: true
+ input-enable: true
+
+ required:
+ - pins
+
+ allOf:
+ - $ref: pincfg-node.yaml#
+
+ # Optional properties for standard pins
+ - if:
+ properties:
+ pins:
+ contains:
+ enum: [ adcsync, bat_rm, classgpwr, clk_cx8, clkout_0,
+ clkout_1, clkout_2, clkout_3, clkreq_in_0,
+ clkreq_in_1, cws_sys_req1, cws_sys_req2,
+ cws_sys_req3, digmic1_clk, digmic1_dq, digmic2_clk,
+ digmic2_dq, gpen13, gpen14, gpen15, gpio00, gpio01,
+ gpio02, gpio03, gpio04, gpio05, gpio06, gpio07,
+ gpio08, gpio09, gpio10, gpio11, gpio12, gpio13,
+ gpio14, gps_pablank, gps_tmark, ic_dm, ic_dp,
+ kp_col_ip_0, kp_col_ip_1, kp_col_ip_2, kp_col_ip_3,
+ kp_row_op_0, kp_row_op_1, kp_row_op_2, kp_row_op_3,
+ lcd_b_0, lcd_b_1, lcd_b_2, lcd_b_3, lcd_b_4, lcd_b_5,
+ lcd_b_6, lcd_b_7, lcd_g_0, lcd_g_1, lcd_g_2, lcd_g_3,
+ lcd_g_4, lcd_g_5, lcd_g_6, lcd_g_7, lcd_hsync,
+ lcd_oe, lcd_pclk, lcd_r_0, lcd_r_1, lcd_r_2,
+ lcd_r_3, lcd_r_4, lcd_r_5, lcd_r_6, lcd_r_7,
+ lcd_vsync, mdmgpio0, mdmgpio1, mdmgpio2, mdmgpio3,
+ mdmgpio4, mdmgpio5, mdmgpio6, mdmgpio7, mdmgpio8,
+ mphi_data_0, mphi_data_1, mphi_data_2, mphi_data_3,
+ mphi_data_4, mphi_data_5, mphi_data_6, mphi_data_7,
+ mphi_data_8, mphi_data_9, mphi_data_10,
+ mphi_data_11, mphi_data_12, mphi_data_13,
+ mphi_data_14, mphi_data_15, mphi_ha0, mphi_hat0,
+ mphi_hat1, mphi_hce0_n, mphi_hce1_n, mphi_hrd_n,
+ mphi_hwr_n, mphi_run0, mphi_run1, mtx_scan_clk,
+ mtx_scan_data, nand_ad_0, nand_ad_1, nand_ad_2,
+ nand_ad_3, nand_ad_4, nand_ad_5, nand_ad_6,
+ nand_ad_7, nand_ale, nand_cen_0, nand_cen_1,
+ nand_cle, nand_oen, nand_rdy_0, nand_rdy_1,
+ nand_wen, nand_wp, pc1, pc2, pmu_int,
+ rfst2g_mtsloten3g, rgmii_0_rx_ctl, rgmii_0_rxc,
+ rgmii_0_rxd_0, rgmii_0_rxd_1, rgmii_0_rxd_2,
+ rgmii_0_rxd_3, rgmii_0_tx_ctl, rgmii_0_txc,
+ rgmii_0_txd_0, rgmii_0_txd_1, rgmii_0_txd_2,
+ rgmii_0_txd_3, rgmii_1_rx_ctl, rgmii_1_rxc,
+ rgmii_1_rxd_0, rgmii_1_rxd_1, rgmii_1_rxd_2,
+ rgmii_1_rxd_3, rgmii_1_tx_ctl, rgmii_1_txc,
+ rgmii_1_txd_0, rgmii_1_txd_1, rgmii_1_txd_2,
+ rgmii_1_txd_3, rgmii_gpio_0, rgmii_gpio_1,
+ rgmii_gpio_2, rgmii_gpio_3, rtxdata2g_txdata3g1,
+ rtxen2g_txdata3g2, rxdata3g0, rxdata3g1, rxdata3g2,
+ sdio1_clk, sdio1_cmd, sdio1_data_0, sdio1_data_1,
+ sdio1_data_2, sdio1_data_3, sdio4_clk, sdio4_cmd,
+ sdio4_data_0, sdio4_data_1, sdio4_data_2,
+ sdio4_data_3, sim_clk, sim_data, sim_det,
+ sim_resetn, sim2_clk, sim2_data, sim2_det,
+ sim2_resetn, sri_c, sri_d, sri_e, ssp_extclk,
+ ssp0_clk, ssp0_fs, ssp0_rxd, ssp0_txd, ssp2_clk,
+ ssp2_fs_0, ssp2_fs_1, ssp2_fs_2, ssp2_fs_3,
+ ssp2_rxd_0, ssp2_rxd_1, ssp2_txd_0, ssp2_txd_1,
+ ssp3_clk, ssp3_fs, ssp3_rxd, ssp3_txd, ssp4_clk,
+ ssp4_fs, ssp4_rxd, ssp4_txd, ssp5_clk, ssp5_fs,
+ ssp5_rxd, ssp5_txd, ssp6_clk, ssp6_fs, ssp6_rxd,
+ ssp6_txd, stat_1, stat_2, sysclken, traceclk,
+ tracedt00, tracedt01, tracedt02, tracedt03,
+ tracedt04, tracedt05, tracedt06, tracedt07,
+ tracedt08, tracedt09, tracedt10, tracedt11,
+ tracedt12, tracedt13, tracedt14, tracedt15,
+ txdata3g0, txpwrind, uartb1_ucts, uartb1_urts,
+ uartb1_urxd, uartb1_utxd, uartb2_urxd, uartb2_utxd,
+ uartb3_ucts, uartb3_urts, uartb3_urxd, uartb3_utxd,
+ uartb4_ucts, uartb4_urts, uartb4_urxd, uartb4_utxd ]
+ then:
+ properties:
+ drive-strength:
+ enum: [ 2, 4, 6, 8, 10, 12, 14, 16 ]
+
+ bias-disable: true
+ bias-pull-up: true
+ bias-pull-down: true
+ input-schmitt-enable: true
+ input-schmitt-disable: true
+
+ # Optional properties for I2C pins
+ - if:
+ properties:
+ pins:
+ contains:
+ enum: [ bsc1_scl, bsc1_sda, bsc2_scl, bsc2_sda, pmu_scl,
+ pmu_sda, vc_cam1_scl, vc_cam1_sda, vc_cam2_scl,
+ vc_cam2_sda, vc_cam3_scl, vc_cam3_sda ]
+ then:
+ properties:
+ bias-pull-up:
+ description:
+ There are 3 pull-up resistors (1.2k, 1.8k, 2.7k) available
+ in parallel for I2C pins.
+ enum: [ 568, 720, 831, 1080, 1200, 1800, 2700 ]
+
+ bias-disable: true
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ pinctrl@35004800 {
+ compatible = "brcm,bcm11351-pinctrl";
+ reg = <0x35004800 0x430>;
+
+ dev-a-active-pins {
+ /* group node defining 1 standard pin */
+ std-grp0 {
+ pins = "gpio00";
+ function = "alt1";
+ input-schmitt-enable;
+ bias-disable;
+ slew-rate = <1>;
+ drive-strength = <4>;
+ };
+
+ /* group node defining 2 I2C pins */
+ i2c-grp0 {
+ pins = "bsc1_scl", "bsc1_sda";
+ function = "alt2";
+ bias-pull-up = <720>;
+ input-enable;
+ };
+
+ /* group node defining 2 HDMI pins */
+ hdmi-grp0 {
+ pins = "hdmi_scl", "hdmi_sda";
+ function = "alt3";
+ slew-rate = <1>;
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/pinctrl/cypress,cy8c95x0.yaml b/Documentation/devicetree/bindings/pinctrl/cypress,cy8c95x0.yaml
index 222d57541b65..7f30ec2f1e54 100644
--- a/Documentation/devicetree/bindings/pinctrl/cypress,cy8c95x0.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/cypress,cy8c95x0.yaml
@@ -51,6 +51,10 @@ properties:
description:
Optional power supply.
+ reset-gpios:
+ description: GPIO connected to the XRES pin
+ maxItems: 1
+
patternProperties:
'-pins$':
type: object
diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
index 35723966b70a..890961826c6f 100644
--- a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
@@ -135,7 +135,6 @@ additionalProperties:
- $ref: pinmux-node.yaml#
properties:
- phandle: true
function: true
groups: true
pins: true
@@ -147,8 +146,6 @@ additionalProperties:
additionalProperties: false
- type: object
- properties:
- phandle: true
additionalProperties:
type: object
allOf:
@@ -156,7 +153,6 @@ additionalProperties:
- $ref: pinmux-node.yaml#
properties:
- phandle: true
function: true
groups: true
pins: true
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml
index 065dedb3573a..1690c0ef553a 100644
--- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml
@@ -22,8 +22,6 @@ properties:
patternProperties:
"^pinmux(-[a-z0-9-_]+)?$":
type: object
- properties:
- phandle: true
# pin groups
additionalProperties:
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.yaml
index f924652bef0d..9b7368bd3862 100644
--- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.yaml
@@ -32,8 +32,6 @@ properties:
patternProperties:
"^pinmux(-[a-z0-9-_]+)?$":
type: object
- properties:
- phandle: true
# pin groups
additionalProperties:
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml
index 60a4bdf01bf2..87b6f4f42f25 100644
--- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml
@@ -23,8 +23,6 @@ properties:
patternProperties:
"^pinmux(-[a-z0-9-_]+)?$":
type: object
- properties:
- phandle: true
# pin groups
additionalProperties:
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.yaml
index 432ea40209a8..63cd743a30e0 100644
--- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.yaml
@@ -24,8 +24,6 @@ properties:
patternProperties:
"^pinmux(-[a-z0-9-_]+)?$":
type: object
- properties:
- phandle: true
# pin groups
additionalProperties:
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml
index 28ae2e6d0cbc..e99387a6da5e 100644
--- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml
@@ -22,8 +22,6 @@ properties:
patternProperties:
"^pinmux(-[a-z0-9-_]+)?$":
type: object
- properties:
- phandle: true
# pin groups
additionalProperties:
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.yaml
index c0eda7848767..36c8f3301a8f 100644
--- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.yaml
@@ -22,8 +22,6 @@ properties:
patternProperties:
"^pinmux(-[a-z0-9-_]+)?$":
type: object
- properties:
- phandle: true
# pin groups
additionalProperties:
diff --git a/Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt
deleted file mode 100644
index b1159434f593..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/oxnas,pinctrl.txt
+++ /dev/null
@@ -1,56 +0,0 @@
-* Oxford Semiconductor OXNAS SoC Family Pin Controller
-
-Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
-../interrupt-controller/interrupts.txt for generic information regarding
-pin controller, GPIO, and interrupt bindings.
-
-OXNAS 'pin configuration node' is a node of a group of pins which can be
-used for a specific device or function. This node represents configurations of
-pins, optional function, and optional mux related configuration.
-
-Required properties for pin controller node:
- - compatible: "oxsemi,ox810se-pinctrl" or "oxsemi,ox820-pinctrl"
- - oxsemi,sys-ctrl: a phandle to the system controller syscon node
-
-Required properties for pin configuration sub-nodes:
- - pins: List of pins to which the configuration applies.
-
-Optional properties for pin configuration sub-nodes:
-----------------------------------------------------
- - function: Mux function for the specified pins.
- - bias-pull-up: Enable weak pull-up.
-
-Example:
-
-pinctrl: pinctrl {
- compatible = "oxsemi,ox810se-pinctrl";
-
- /* Regmap for sys registers */
- oxsemi,sys-ctrl = <&sys>;
-
- pinctrl_uart2: pinctrl_uart2 {
- uart2a {
- pins = "gpio31";
- function = "fct3";
- };
- uart2b {
- pins = "gpio32";
- function = "fct3";
- };
- };
-};
-
-uart2: serial@900000 {
- compatible = "ns16550a";
- reg = <0x900000 0x100000>;
- clocks = <&sysclk>;
- interrupts = <29>;
- reg-shift = <0>;
- fifo-size = <16>;
- reg-io-width = <1>;
- current-speed = <115200>;
- no-loopback-test;
- resets = <&reset 22>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
-};
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
deleted file mode 100644
index bfd222b05495..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
+++ /dev/null
@@ -1,262 +0,0 @@
-One-register-per-pin type device tree based pinctrl driver
-
-Required properties:
-- compatible : "pinctrl-single" or "pinconf-single".
- "pinctrl-single" means that pinconf isn't supported.
- "pinconf-single" means that generic pinconf is supported.
-
-- reg : offset and length of the register set for the mux registers
-
-- #pinctrl-cells : number of cells in addition to the index, set to 1
- or 2 for pinctrl-single,pins and set to 2 for pinctrl-single,bits
-
-- pinctrl-single,register-width : pinmux register access width in bits
-
-- pinctrl-single,function-mask : mask of allowed pinmux function bits
- in the pinmux register
-
-Optional properties:
-- pinctrl-single,function-off : function off mode for disabled state if
- available and same for all registers; if not specified, disabling of
- pin functions is ignored
-
-- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
- more than one pin, for which "pinctrl-single,function-mask" property specifies
- position mask of pin.
-
-- pinctrl-single,drive-strength : array of value that are used to configure
- drive strength in the pinmux register. They're value of drive strength
- current and drive strength mask.
-
- /* drive strength current, mask */
- pinctrl-single,power-source = <0x30 0xf0>;
-
-- pinctrl-single,bias-pullup : array of value that are used to configure the
- input bias pullup in the pinmux register.
-
- /* input, enabled pullup bits, disabled pullup bits, mask */
- pinctrl-single,bias-pullup = <0 1 0 1>;
-
-- pinctrl-single,bias-pulldown : array of value that are used to configure the
- input bias pulldown in the pinmux register.
-
- /* input, enabled pulldown bits, disabled pulldown bits, mask */
- pinctrl-single,bias-pulldown = <2 2 0 2>;
-
- * Two bits to control input bias pullup and pulldown: User should use
- pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. One bit means
- pullup, and the other one bit means pulldown.
- * Three bits to control input bias enable, pullup and pulldown. User should
- use pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. Input bias
- enable bit should be included in pullup or pulldown bits.
- * Although driver could set PIN_CONFIG_BIAS_DISABLE, there's no property as
- pinctrl-single,bias-disable. Because pinctrl single driver could implement
- it by calling pulldown, pullup disabled.
-
-- pinctrl-single,input-schmitt : array of value that are used to configure
- input schmitt in the pinmux register. In some silicons, there're two input
- schmitt value (rising-edge & falling-edge) in the pinmux register.
-
- /* input schmitt value, mask */
- pinctrl-single,input-schmitt = <0x30 0x70>;
-
-- pinctrl-single,input-schmitt-enable : array of value that are used to
- configure input schmitt enable or disable in the pinmux register.
-
- /* input, enable bits, disable bits, mask */
- pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>;
-
-- pinctrl-single,low-power-mode : array of value that are used to configure
- low power mode of this pin. For some silicons, the low power mode will
- control the output of the pin when the pad including the pin enter low
- power mode.
- /* low power mode value, mask */
- pinctrl-single,low-power-mode = <0x288 0x388>;
-
-- pinctrl-single,gpio-range : list of value that are used to configure a GPIO
- range. They're value of subnode phandle, pin base in pinctrl device, pin
- number in this range, GPIO function value of this GPIO range.
- The number of parameters is depend on #pinctrl-single,gpio-range-cells
- property.
-
- /* pin base, nr pins & gpio function */
- pinctrl-single,gpio-range = <&range 0 3 0>, <&range 3 9 1>;
-
-- interrupt-controller : standard interrupt controller binding if using
- interrupts for wake-up events for example. In this case pinctrl-single
- is set up as a chained interrupt controller and the wake-up interrupts
- can be requested by the drivers using request_irq().
-
-- #interrupt-cells : standard interrupt binding if using interrupts
-
-This driver assumes that there is only one register for each pin (unless the
-pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
-specified in the pinctrl-bindings.txt document in this directory.
-
-The pin configuration nodes for pinctrl-single are specified as pinctrl
-register offset and values using pinctrl-single,pins. Only the bits specified
-in pinctrl-single,function-mask are updated.
-
-When #pinctrl-cells = 1, then setting a pin for a device could be done with:
-
- pinctrl-single,pins = <0xdc 0x118>;
-
-Where 0xdc is the offset from the pinctrl register base address for the device
-pinctrl register, and 0x118 contains the desired value of the pinctrl register.
-
-When #pinctrl-cells = 2, then setting a pin for a device could be done with:
-
- pinctrl-single,pins = <0xdc 0x30 0x07>;
-
-Where 0x30 is the pin configuration value and 0x07 is the pin mux mode value.
-These two values are OR'd together to produce the value stored at offset 0xdc.
-See the device example and static board pins example below for more information.
-
-In case when one register changes more than one pin's mux the
-pinctrl-single,bits need to be used which takes three parameters:
-
- pinctrl-single,bits = <0xdc 0x18 0xff>;
-
-Where 0xdc is the offset from the pinctrl register base address for the
-device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
-be used when applying this change to the register.
-
-
-Optional sub-node: In case some pins could be configured as GPIO in the pinmux
-register, those pins could be defined as a GPIO range. This sub-node is required
-by pinctrl-single,gpio-range property.
-
-Required properties in sub-node:
-- #pinctrl-single,gpio-range-cells : the number of parameters after phandle in
- pinctrl-single,gpio-range property.
-
- range: gpio-range {
- #pinctrl-single,gpio-range-cells = <3>;
- };
-
-
-Example:
-
-/* SoC common file */
-
-/* first controller instance for pins in core domain */
-pmx_core: pinmux@4a100040 {
- compatible = "pinctrl-single";
- reg = <0x4a100040 0x0196>;
- #address-cells = <1>;
- #size-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-controller;
- pinctrl-single,register-width = <16>;
- pinctrl-single,function-mask = <0xffff>;
-};
-
-/* second controller instance for pins in wkup domain */
-pmx_wkup: pinmux@4a31e040 {
- compatible = "pinctrl-single";
- reg = <0x4a31e040 0x0038>;
- #address-cells = <1>;
- #size-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-controller;
- pinctrl-single,register-width = <16>;
- pinctrl-single,function-mask = <0xffff>;
-};
-
-control_devconf0: pinmux@48002274 {
- compatible = "pinctrl-single";
- reg = <0x48002274 4>; /* Single register */
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-single,bit-per-mux;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x5F>;
-};
-
-/* third controller instance for pins in gpio domain */
-pmx_gpio: pinmux@d401e000 {
- compatible = "pinconf-single";
- reg = <0xd401e000 0x0330>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <7>;
-
- /* sparse GPIO range could be supported */
- pinctrl-single,gpio-range = <&range 0 3 0>, <&range 3 9 1>,
- <&range 12 1 0>, <&range 13 29 1>,
- <&range 43 1 0>, <&range 44 49 1>,
- <&range 94 1 1>, <&range 96 2 1>;
-
- range: gpio-range {
- #pinctrl-single,gpio-range-cells = <3>;
- };
-};
-
-
-/* board specific .dts file */
-
-&pmx_core {
-
- /*
- * map all board specific static pins enabled by the pinctrl driver
- * itself during the boot (or just set them up in the bootloader)
- */
- pinctrl-names = "default";
- pinctrl-0 = <&board_pins>;
-
- board_pins: pinmux_board_pins {
- pinctrl-single,pins = <
- 0x6c 0xf
- 0x6e 0xf
- 0x70 0xf
- 0x72 0xf
- >;
- };
-
- uart0_pins: pinmux_uart0_pins {
- pinctrl-single,pins = <
- 0x208 0 /* UART0_RXD (IOCFG138) */
- 0x20c 0 /* UART0_TXD (IOCFG139) */
- >;
- pinctrl-single,bias-pulldown = <0 2 2>;
- pinctrl-single,bias-pullup = <0 1 1>;
- };
-
- /* map uart2 pins */
- uart2_pins: pinmux_uart2_pins {
- pinctrl-single,pins = <
- 0xd8 0x118
- 0xda 0
- 0xdc 0x118
- 0xde 0
- >;
- };
-};
-
-&control_devconf0 {
- mcbsp1_pins: pinmux_mcbsp1_pins {
- pinctrl-single,bits = <
- 0x00 0x18 0x18 /* FSR/CLKR signal from FSX/CLKX pin */
- >;
- };
-
- mcbsp2_clks_pins: pinmux_mcbsp2_clks_pins {
- pinctrl-single,bits = <
- 0x00 0x40 0x40 /* McBSP2 CLKS from McBSP_CLKS pin */
- >;
- };
-
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>;
-};
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml
new file mode 100644
index 000000000000..45a307d3ce16
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml
@@ -0,0 +1,207 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic Pin Controller with a Single Register for One or More Pins
+
+maintainers:
+ - Tony Lindgren <tony@atomide.com>
+
+description:
+ Some pin controller devices use a single register for one or more pins. The
+ range of pin control registers can vary from one to many for each controller
+ instance. Some SoCs from Altera, Broadcom, HiSilicon, Ralink, and TI have this
+ kind of pin controller instances.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - pinctrl-single
+ - pinconf-single
+ - items:
+ - enum:
+ - ti,am437-padconf
+ - ti,am654-padconf
+ - ti,dra7-padconf
+ - ti,omap2420-padconf
+ - ti,omap2430-padconf
+ - ti,omap3-padconf
+ - ti,omap4-padconf
+ - ti,omap5-padconf
+ - const: pinctrl-single
+
+ reg:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ '#pinctrl-cells':
+ description:
+ Number of cells. Usually 2, consisting of register offset, pin configuration
+ value, and pinmux mode. Some controllers may use 1 for just offset and value.
+ enum: [ 1, 2 ]
+
+ pinctrl-single,bit-per-mux:
+ description: Optional flag to indicate register controls more than one pin
+ type: boolean
+
+ pinctrl-single,function-mask:
+ description: Mask of the allowed register bits
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ pinctrl-single,function-off:
+ description: Optional function off mode for disabled state
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ pinctrl-single,register-width:
+ description: Width of pin specific bits in the register
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 8, 16, 32 ]
+
+ pinctrl-single,gpio-range:
+ description: Optional list of pin base, nr pins & gpio function
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle of a gpio-range node
+ - description: pin base
+ - description: number of pins
+ - description: gpio function
+
+ '#gpio-range-cells':
+ description: No longer needed, may exist in older files for gpio-ranges
+ deprecated: true
+ const: 3
+
+ gpio-range:
+ description: Optional node for gpio range cells
+ type: object
+ additionalProperties: false
+ properties:
+ '#pinctrl-single,gpio-range-cells':
+ description: Number of gpio range cells
+ const: 3
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+patternProperties:
+ '-pins(-[0-9]+)?$|-pin$':
+ description:
+ Pin group node name using naming ending in -pins followed by an optional
+ instance number
+ type: object
+ additionalProperties: false
+
+ properties:
+ pinctrl-single,pins:
+ description:
+ Array of pins as described in pinmux-node.yaml for pinctrl-pin-array
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+
+ pinctrl-single,bits:
+ description: Register bit configuration for pinctrl-single,bit-per-mux
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - description: register offset
+ - description: value
+ - description: pin bitmask in the register
+
+ pinctrl-single,bias-pullup:
+ description: Optional bias pull up configuration
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - description: input
+ - description: enabled pull up bits
+ - description: disabled pull up bits
+ - description: bias pull up mask
+
+ pinctrl-single,bias-pulldown:
+ description: Optional bias pull down configuration
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - description: input
+ - description: enabled pull down bits
+ - description: disabled pull down bits
+ - description: bias pull down mask
+
+ pinctrl-single,drive-strength:
+ description: Optional drive strength configuration
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - description: drive strength current
+ - description: drive strength mask
+
+ pinctrl-single,input-schmitt:
+ description: Optional input schmitt configuration
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - description: input
+ - description: enable bits
+ - description: disable bits
+ - description: input schmitt mask
+
+ pinctrl-single,low-power-mode:
+ description: Optional low power mode configuration
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - description: low power mode value
+ - description: low power mode mask
+
+ pinctrl-single,slew-rate:
+ description: Optional slew rate configuration
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - description: slew rate
+ - description: slew rate mask
+
+allOf:
+ - $ref: pinctrl.yaml#
+
+required:
+ - compatible
+ - reg
+ - pinctrl-single,register-width
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pinmux@4a100040 {
+ compatible = "pinctrl-single";
+ reg = <0x4a100040 0x0196>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #pinctrl-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ pinctrl-single,register-width = <16>;
+ pinctrl-single,function-mask = <0xffff>;
+ pinctrl-single,gpio-range = <&range 0 3 0>;
+ range: gpio-range {
+ #pinctrl-single,gpio-range-cells = <3>;
+ };
+
+ uart2-pins {
+ pinctrl-single,pins =
+ <0xd8 0x118>,
+ <0xda 0>,
+ <0xdc 0x118>,
+ <0xde 0>;
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml
index 8aaf50181cef..3f8ad07c7cfd 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml
@@ -26,6 +26,7 @@ properties:
- qcom,pm6350-gpio
- qcom,pm7250b-gpio
- qcom,pm7325-gpio
+ - qcom,pm7550ba-gpio
- qcom,pm8005-gpio
- qcom,pm8008-gpio
- qcom,pm8018-gpio
@@ -53,6 +54,8 @@ properties:
- qcom,pm8994-gpio
- qcom,pm8998-gpio
- qcom,pma8084-gpio
+ - qcom,pmc8180-gpio
+ - qcom,pmc8180c-gpio
- qcom,pmi632-gpio
- qcom,pmi8950-gpio
- qcom,pmi8994-gpio
@@ -68,6 +71,7 @@ properties:
- qcom,pms405-gpio
- qcom,pmx55-gpio
- qcom,pmx65-gpio
+ - qcom,pmx75-gpio
- enum:
- qcom,spmi-gpio
@@ -172,6 +176,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,pm7550ba-gpio
- qcom,pm8226-gpio
- qcom,pm8350b-gpio
- qcom,pm8550ve-gpio
@@ -301,6 +306,7 @@ allOf:
contains:
enum:
- qcom,pmx65-gpio
+ - qcom,pmx75-gpio
then:
properties:
gpio-line-names:
@@ -413,6 +419,7 @@ $defs:
- gpio1-gpio9 for pm6350
- gpio1-gpio12 for pm7250b
- gpio1-gpio10 for pm7325
+ - gpio1-gpio8 for pm7550ba
- gpio1-gpio4 for pm8005
- gpio1-gpio2 for pm8008
- gpio1-gpio6 for pm8018
@@ -456,6 +463,7 @@ $defs:
- gpio1-gpio11 for pmx55 (holes on gpio3, gpio7, gpio10
and gpio11)
- gpio1-gpio16 for pmx65
+ - gpio1-gpio16 for pmx75
items:
pattern: "^gpio([0-9]+)$"
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
index fa51fa9536f7..00c5a00e35fc 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml
@@ -17,11 +17,6 @@ properties:
compatible:
const: qcom,sc7280-lpass-lpi-pinctrl
- qcom,adsp-bypass-mode:
- description:
- Tells ADSP is in bypass mode.
- type: boolean
-
reg:
maxItems: 2
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml
new file mode 100644
index 000000000000..abac3311fc55
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml
@@ -0,0 +1,135 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6115 SoC LPASS LPI TLMM
+
+maintainers:
+ - Konrad Dybcio <konradybcio@kernel.org>
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description:
+ Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
+ (LPASS) Low Power Island (LPI) of Qualcomm SM6115 SoC.
+
+properties:
+ compatible:
+ const: qcom,sm6115-lpass-lpi-pinctrl
+
+ reg:
+ items:
+ - description: LPASS LPI TLMM Control and Status registers
+ - description: LPASS LPI MCC registers
+
+ clocks:
+ items:
+ - description: LPASS Audio voting clock
+
+ clock-names:
+ items:
+ - const: audio
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ description: Specifying the pin number and flags, as defined in
+ include/dt-bindings/gpio/gpio.h
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+patternProperties:
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-sm6115-lpass-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-sm6115-lpass-state"
+ additionalProperties: false
+
+$defs:
+ qcom-sm6115-lpass-state:
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: /schemas/pinctrl/pincfg-node.yaml
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ pattern: "^gpio([0-9]|1[0-8])$"
+
+ function:
+ enum: [ dmic01_clk, dmic01_data, dmic23_clk, dmic23_data, gpio, i2s1_clk,
+ i2s1_data, i2s1_ws, i2s2_clk, i2s2_data, i2s2_ws, i2s3_clk,
+ i2s3_data, i2s3_ws, qua_mi2s_data, qua_mi2s_sclk, qua_mi2s_ws,
+ swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_data, wsa_mclk ]
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ drive-strength:
+ enum: [2, 4, 6, 8, 10, 12, 14, 16]
+ default: 2
+ description:
+ Selects the drive strength for the specified pins, in mA.
+
+ slew-rate:
+ enum: [0, 1, 2, 3]
+ default: 0
+ description: |
+ 0: No adjustments
+ 1: Higher Slew rate (faster edges)
+ 2: Lower Slew rate (slower edges)
+ 3: Reserved (No adjustments)
+
+ bias-bus-hold: true
+ bias-pull-down: true
+ bias-pull-up: true
+ bias-disable: true
+ input-enable: true
+ output-high: true
+ output-low: true
+
+ required:
+ - pins
+ - function
+
+ additionalProperties: false
+
+allOf:
+ - $ref: pinctrl.yaml#
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - gpio-controller
+ - "#gpio-cells"
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/sound/qcom,q6afe.h>
+
+ lpass_tlmm: pinctrl@a7c0000 {
+ compatible = "qcom,sm6115-lpass-lpi-pinctrl";
+ reg = <0x0a7c0000 0x20000>,
+ <0x0a950000 0x10000>;
+ clocks = <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "audio";
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&lpass_tlmm 0 0 19>;
+ };
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml
new file mode 100644
index 000000000000..2e65ae08dd21
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml
@@ -0,0 +1,143 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM8350 SoC LPASS LPI TLMM
+
+maintainers:
+ - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description:
+ Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
+ (LPASS) Low Power Island (LPI) of Qualcomm SM8350 SoC.
+
+properties:
+ compatible:
+ const: qcom,sm8350-lpass-lpi-pinctrl
+
+ reg:
+ items:
+ - description: LPASS LPI TLMM Control and Status registers
+ - description: LPASS LPI MCC registers
+
+ clocks:
+ items:
+ - description: LPASS Core voting clock
+ - description: LPASS Audio voting clock
+
+ clock-names:
+ items:
+ - const: core
+ - const: audio
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ description: Specifying the pin number and flags, as defined in
+ include/dt-bindings/gpio/gpio.h
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+patternProperties:
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-sm8350-lpass-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-sm8350-lpass-state"
+ additionalProperties: false
+
+$defs:
+ qcom-sm8350-lpass-state:
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: /schemas/pinctrl/pincfg-node.yaml
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ pattern: "^gpio([0-9]|1[0-9]|2[0-2])$"
+
+ function:
+ enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk,
+ dmic3_data, dmic4_clk, dmic4_data, ext_mclk1_a, ext_mclk1_b,
+ ext_mclk1_c, ext_mclk1_d, ext_mclk1_e, gpio, i2s0_clk,
+ i2s0_data, i2s0_ws, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk,
+ i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, i2s4_clk,
+ i2s4_data, i2s4_ws, slimbus_clk, slimbus_data, swr_rx_clk,
+ swr_rx_data, swr_tx_clk, swr_tx_data, wsa_swr_clk,
+ wsa_swr_data, wsa2_swr_clk, wsa2_swr_data ]
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ drive-strength:
+ enum: [2, 4, 6, 8, 10, 12, 14, 16]
+ default: 2
+ description:
+ Selects the drive strength for the specified pins, in mA.
+
+ slew-rate:
+ enum: [0, 1, 2, 3]
+ default: 0
+ description: |
+ 0: No adjustments
+ 1: Higher Slew rate (faster edges)
+ 2: Lower Slew rate (slower edges)
+ 3: Reserved (No adjustments)
+
+ bias-bus-hold: true
+ bias-pull-down: true
+ bias-pull-up: true
+ bias-disable: true
+ input-enable: true
+ output-high: true
+ output-low: true
+
+ required:
+ - pins
+ - function
+
+ additionalProperties: false
+
+allOf:
+ - $ref: pinctrl.yaml#
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - gpio-controller
+ - "#gpio-cells"
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/sound/qcom,q6afe.h>
+
+ lpass_tlmm: pinctrl@33c0000 {
+ compatible = "qcom,sm8350-lpass-lpi-pinctrl";
+ reg = <0x033c0000 0x20000>,
+ <0x03550000 0x10000>;
+
+ clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "core", "audio";
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&lpass_tlmm 0 0 15>;
+ };
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml
index 0fc3c0f52c19..181cd1676c0a 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml
@@ -107,7 +107,6 @@ additionalProperties:
Client device subnodes use below standard properties.
properties:
- phandle: true
function: true
groups: true
pins: true
@@ -127,9 +126,6 @@ additionalProperties:
additionalProperties: false
- type: object
- properties:
- phandle: true
-
additionalProperties:
$ref: "#/additionalProperties/anyOf/0"
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml
index 83800fcf0ce4..2bd7d47d0fdb 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml
@@ -108,7 +108,6 @@ additionalProperties:
Integers values in "pinmux" argument list are assembled as:
((PORT * 16 + PIN) | MUX_FUNC << 16)
- phandle: true
input-enable: true
output-enable: true
@@ -118,9 +117,6 @@ additionalProperties:
additionalProperties: false
- type: object
- properties:
- phandle: true
-
additionalProperties:
$ref: "#/additionalProperties/anyOf/0"
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml
index 37173a64fed2..8271e7b2c162 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml
@@ -37,40 +37,37 @@ properties:
gpio-ranges:
maxItems: 1
-patternProperties:
- "^.*$":
- if:
- type: object
- then:
- allOf:
- - $ref: pincfg-node.yaml#
- - $ref: pinmux-node.yaml#
+additionalProperties:
+ type: object
+
+ allOf:
+ - $ref: pincfg-node.yaml#
+ - $ref: pinmux-node.yaml#
+
+ description:
+ The child nodes of the pin controller designate pins to be used for
+ specific peripheral functions or as GPIO.
+
+ A pin multiplexing sub-node describes how to configure a set of
+ (or a single) pin in some desired alternate function mode.
+ The values for the pinmux properties are a combination of port name,
+ pin number and the desired function index. Use the RZA2_PINMUX macro
+ located in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily
+ define these.
+ For assigning GPIO pins, use the macro RZA2_PIN also in
+ to express the desired port pin.
+
+ properties:
+ pinmux:
description:
- The child nodes of the pin controller designate pins to be used for
- specific peripheral functions or as GPIO.
+ Values are constructed from GPIO port number, pin number, and
+ alternate function configuration number using the RZA2_PINMUX()
+ helper macro in r7s9210-pinctrl.h.
- A pin multiplexing sub-node describes how to configure a set of
- (or a single) pin in some desired alternate function mode.
- The values for the pinmux properties are a combination of port name,
- pin number and the desired function index. Use the RZA2_PINMUX macro
- located in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily
- define these.
- For assigning GPIO pins, use the macro RZA2_PIN also in
- to express the desired port pin.
+ required:
+ - pinmux
- properties:
- phandle: true
-
- pinmux:
- description:
- Values are constructed from GPIO port number, pin number, and
- alternate function configuration number using the RZA2_PINMUX()
- helper macro in r7s9210-pinctrl.h.
-
- required:
- - pinmux
-
- additionalProperties: false
+ additionalProperties: false
allOf:
- $ref: pinctrl.yaml#
@@ -82,8 +79,6 @@ required:
- '#gpio-cells'
- gpio-ranges
-additionalProperties: false
-
examples:
- |
#include <dt-bindings/pinctrl/r7s9210-pinctrl.h>
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index 9ce1a07fc015..145c5442f268 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -83,7 +83,6 @@ additionalProperties:
Client device subnodes use below standard properties.
properties:
- phandle: true
pinmux:
description:
Values are constructed from GPIO port number, pin number, and
@@ -106,9 +105,6 @@ additionalProperties:
line-name: true
- type: object
- properties:
- phandle: true
-
additionalProperties:
$ref: "#/additionalProperties/anyOf/0"
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml
index 19d4d2facfb4..816688580e33 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml
@@ -74,7 +74,6 @@ additionalProperties:
offset by 10. Additional identifiers are provided to specify the
MDIO source peripheral.
- phandle: true
bias-disable: true
bias-pull-up:
description: Pull up the pin with 50 kOhm
@@ -91,9 +90,6 @@ additionalProperties:
$ref: "#/additionalProperties/anyOf/0"
- type: object
- properties:
- phandle: true
-
additionalProperties:
$ref: "#/additionalProperties/anyOf/0"
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml
index c87161f2954f..cb81a17bd0b1 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml
@@ -63,7 +63,6 @@ additionalProperties:
Client device subnodes use below standard properties.
properties:
- phandle: true
pinmux:
description:
Values are constructed from GPIO port number, pin number, and
@@ -87,9 +86,6 @@ additionalProperties:
line-name: true
- type: object
- properties:
- phandle: true
-
additionalProperties:
$ref: "#/additionalProperties/anyOf/0"
diff --git a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml
index a6f34df82e90..880da721a927 100644
--- a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml
@@ -32,7 +32,6 @@ additionalProperties:
- $ref: pinmux-node.yaml#
properties:
- phandle: true
function: true
groups: true
pins: true
@@ -49,7 +48,6 @@ additionalProperties:
- $ref: pinmux-node.yaml#
properties:
- phandle: true
function: true
groups: true
pins: true
diff --git a/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt
deleted file mode 100644
index 88c80273da91..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-OMAP Pinctrl definitions
-
-Required properties:
-- compatible : Should be one of:
- "ti,omap2420-padconf" - OMAP2420 compatible pinctrl
- "ti,omap2430-padconf" - OMAP2430 compatible pinctrl
- "ti,omap3-padconf" - OMAP3 compatible pinctrl
- "ti,omap4-padconf" - OMAP4 compatible pinctrl
- "ti,omap5-padconf" - OMAP5 compatible pinctrl
- "ti,dra7-padconf" - DRA7 compatible pinctrl
- "ti,am437-padconf" - AM437x compatible pinctrl
-
-See Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt for further details.
diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml
index 24ad0614e61b..01b6f2b57843 100644
--- a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml
@@ -273,6 +273,10 @@ patternProperties:
slew-rate:
enum: [0, 1]
+ output-enable:
+ description:
+ This will internally disable the tri-state for MIO pins.
+
drive-strength:
description:
Selects the drive strength for MIO pins, in mA.