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path: root/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h11
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
index 915a20461c77..7bdc146f7cb5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
@@ -205,6 +205,11 @@
type PHYDSYMCLK_GATE_DISABLE; \
type PHYESYMCLK_GATE_DISABLE;
+#define DCCG314_REG_FIELD_LIST(type) \
+ type DSCCLK3_DTO_PHASE;\
+ type DSCCLK3_DTO_MODULO;\
+ type DSCCLK3_DTO_ENABLE;
+
#define DCCG32_REG_FIELD_LIST(type) \
type DPSTREAMCLK0_EN;\
type DPSTREAMCLK1_EN;\
@@ -230,12 +235,14 @@
type DTBCLK_P2_SRC_SEL;\
type DTBCLK_P2_EN;\
type DTBCLK_P3_SRC_SEL;\
- type DTBCLK_P3_EN;
+ type DTBCLK_P3_EN;\
+ type DENTIST_DISPCLK_CHG_DONE;
struct dccg_shift {
DCCG_REG_FIELD_LIST(uint8_t)
DCCG3_REG_FIELD_LIST(uint8_t)
DCCG31_REG_FIELD_LIST(uint8_t)
+ DCCG314_REG_FIELD_LIST(uint8_t)
DCCG32_REG_FIELD_LIST(uint8_t)
};
@@ -243,6 +250,7 @@ struct dccg_mask {
DCCG_REG_FIELD_LIST(uint32_t)
DCCG3_REG_FIELD_LIST(uint32_t)
DCCG31_REG_FIELD_LIST(uint32_t)
+ DCCG314_REG_FIELD_LIST(uint32_t)
DCCG32_REG_FIELD_LIST(uint32_t)
};
@@ -272,6 +280,7 @@ struct dccg_registers {
uint32_t DSCCLK0_DTO_PARAM;
uint32_t DSCCLK1_DTO_PARAM;
uint32_t DSCCLK2_DTO_PARAM;
+ uint32_t DSCCLK3_DTO_PARAM;
uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE;
uint32_t DPSTREAMCLK_GATE_DISABLE;
uint32_t DCCG_GATE_DISABLE_CNTL;