diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c index 962a2c02b422..467509a65fa7 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c @@ -296,12 +296,14 @@ static void enc314_stream_encoder_dp_unblank( uint32_t n_vid = 0x8000; uint32_t m_vid; uint32_t n_multiply = 0; + uint32_t pix_per_cycle = 0; uint64_t m_vid_l = n_vid; /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */ if (is_two_pixels_per_containter(¶m->timing) || param->opp_cnt > 1) { /*this logic should be the same in get_pixel_clock_parameters() */ n_multiply = 1; + pix_per_cycle = 1; } /* M / N = Fstream / Flink * m_vid / n_vid = pixel rate / link rate @@ -329,6 +331,10 @@ static void enc314_stream_encoder_dp_unblank( REG_UPDATE_2(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1, DP_VID_N_MUL, n_multiply); + + REG_UPDATE(DP_PIXEL_FORMAT, + DP_PIXEL_PER_CYCLE_PROCESSING_MODE, + pix_per_cycle); } /* make sure stream is disabled before resetting steer fifo */ @@ -366,7 +372,7 @@ static void enc314_stream_encoder_dp_unblank( */ enc314_enable_fifo(enc); - link_dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM); + link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM); } /* Set DSC-related configuration. |