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path: root/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h31
1 files changed, 26 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
index c7021915bac8..c2d116cce119 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
@@ -45,9 +45,10 @@ enum physymclk_clock_source {
PHYSYMCLK_FORCE_SRC_PHYD32CLK, // Select phyd32clk as the source of clock which is output to PHY through DCIO.
};
-enum hdmistreamclk_source {
+enum streamclk_source {
REFCLK, // Selects REFCLK as source for hdmistreamclk.
DTBCLK0, // Selects DTBCLK0 as source for hdmistreamclk.
+ DPREFCLK, // Selects DPREFCLK as source for hdmistreamclk
};
enum dentist_dispclk_change_mode {
@@ -55,6 +56,13 @@ enum dentist_dispclk_change_mode {
DISPCLK_CHANGE_MODE_RAMPING,
};
+enum pixel_rate_div {
+ PIXEL_RATE_DIV_BY_1 = 0,
+ PIXEL_RATE_DIV_BY_2 = 1,
+ PIXEL_RATE_DIV_BY_4 = 3,
+ PIXEL_RATE_DIV_NA = 0xF
+};
+
struct dccg {
struct dc_context *ctx;
const struct dccg_funcs *funcs;
@@ -62,7 +70,7 @@ struct dccg {
int ref_dppclk;
//int dtbclk_khz[MAX_PIPES];/* TODO needs to be removed */
//int audio_dtbclk_khz;/* TODO needs to be removed */
- int ref_dtbclk_khz;/* TODO needs to be removed */
+ //int ref_dtbclk_khz;/* TODO needs to be removed */
};
struct dtbclk_dto_params {
@@ -72,6 +80,7 @@ struct dtbclk_dto_params {
int req_audio_dtbclk_khz;
int num_odm_segments;
int ref_dtbclk_khz;
+ bool is_hdmi;
};
struct dccg_funcs {
@@ -91,7 +100,7 @@ struct dccg_funcs {
void (*set_dpstreamclk)(
struct dccg *dccg,
- enum hdmistreamclk_source src,
+ enum streamclk_source src,
int otg_inst);
void (*enable_symclk32_se)(
@@ -120,11 +129,11 @@ struct dccg_funcs {
void (*set_dtbclk_dto)(
struct dccg *dccg,
- struct dtbclk_dto_params *dto_params);
+ const struct dtbclk_dto_params *params);
void (*set_audio_dtbclk_dto)(
struct dccg *dccg,
- uint32_t req_audio_dtbclk_khz);
+ const struct dtbclk_dto_params *params);
void (*set_dispclk_change_mode)(
struct dccg *dccg,
@@ -138,6 +147,18 @@ struct dccg_funcs {
struct dccg *dccg,
int inst);
+void (*set_pixel_rate_div)(
+ struct dccg *dccg,
+ uint32_t otg_inst,
+ enum pixel_rate_div k1,
+ enum pixel_rate_div k2);
+
+void (*set_valid_pixel_rate)(
+ struct dccg *dccg,
+ int ref_dtbclk_khz,
+ int otg_inst,
+ int pixclk_khz);
+
};
#endif //__DAL_DCCG_H__