diff options
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_offset.h')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_offset.h | 10002 |
1 files changed, 10002 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_offset.h new file mode 100644 index 000000000000..033f2796c1e3 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_offset.h @@ -0,0 +1,10002 @@ +/* + * Copyright 2022 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _nbio_7_9_0_OFFSET_HEADER +#define _nbio_7_9_0_OFFSET_HEADER + + + +// addressBlock: aid_nbio_nbif0_bif_bx_SYSDEC +// base address: 0x0 +#define regBIF_BX0_PCIE_INDEX 0x000c +#define regBIF_BX0_PCIE_INDEX_BASE_IDX 0 +#define regBIF_BX0_PCIE_DATA 0x000d +#define regBIF_BX0_PCIE_DATA_BASE_IDX 0 +#define regBIF_BX0_PCIE_INDEX2 0x000e +#define regBIF_BX0_PCIE_INDEX2_BASE_IDX 0 +#define regBIF_BX0_PCIE_DATA2 0x000f +#define regBIF_BX0_PCIE_DATA2_BASE_IDX 0 +#define regBIF_BX0_PCIE_INDEX_HI 0x0010 +#define regBIF_BX0_PCIE_INDEX_HI_BASE_IDX 0 +#define regBIF_BX0_PCIE_INDEX2_HI 0x0011 +#define regBIF_BX0_PCIE_INDEX2_HI_BASE_IDX 0 +#define regBIF_BX0_SBIOS_SCRATCH_0 0x0034 +#define regBIF_BX0_SBIOS_SCRATCH_0_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_1 0x0035 +#define regBIF_BX0_SBIOS_SCRATCH_1_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_2 0x0036 +#define regBIF_BX0_SBIOS_SCRATCH_2_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_3 0x0037 +#define regBIF_BX0_SBIOS_SCRATCH_3_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_0 0x0038 +#define regBIF_BX0_BIOS_SCRATCH_0_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_1 0x0039 +#define regBIF_BX0_BIOS_SCRATCH_1_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_2 0x003a +#define regBIF_BX0_BIOS_SCRATCH_2_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_3 0x003b +#define regBIF_BX0_BIOS_SCRATCH_3_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_4 0x003c +#define regBIF_BX0_BIOS_SCRATCH_4_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_5 0x003d +#define regBIF_BX0_BIOS_SCRATCH_5_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_6 0x003e +#define regBIF_BX0_BIOS_SCRATCH_6_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_7 0x003f +#define regBIF_BX0_BIOS_SCRATCH_7_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_8 0x0040 +#define regBIF_BX0_BIOS_SCRATCH_8_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_9 0x0041 +#define regBIF_BX0_BIOS_SCRATCH_9_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_10 0x0042 +#define regBIF_BX0_BIOS_SCRATCH_10_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_11 0x0043 +#define regBIF_BX0_BIOS_SCRATCH_11_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_12 0x0044 +#define regBIF_BX0_BIOS_SCRATCH_12_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_13 0x0045 +#define regBIF_BX0_BIOS_SCRATCH_13_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_14 0x0046 +#define regBIF_BX0_BIOS_SCRATCH_14_BASE_IDX 1 +#define regBIF_BX0_BIOS_SCRATCH_15 0x0047 +#define regBIF_BX0_BIOS_SCRATCH_15_BASE_IDX 1 +#define regBIF_BX0_BIF_RLC_INTR_CNTL 0x004c +#define regBIF_BX0_BIF_RLC_INTR_CNTL_BASE_IDX 1 +#define regBIF_BX0_BIF_VCE_INTR_CNTL 0x004d +#define regBIF_BX0_BIF_VCE_INTR_CNTL_BASE_IDX 1 +#define regBIF_BX0_BIF_UVD_INTR_CNTL 0x004e +#define regBIF_BX0_BIF_UVD_INTR_CNTL_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0 0x006c +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0 0x006d +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1 0x006e +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1 0x006f +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2 0x0070 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2 0x0071 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3 0x0072 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3 0x0073 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4 0x0074 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4 0x0075 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5 0x0076 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5 0x0077 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6 0x0078 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6 0x0079 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7 0x007a +#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7 0x007b +#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_CNTL 0x007c +#define regBIF_BX0_GFX_MMIOREG_CAM_CNTL_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL 0x007d +#define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL 0x007e +#define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 1 +#define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x007f +#define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_0 0x0080 +#define regBIF_BX0_DRIVER_SCRATCH_0_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_1 0x0081 +#define regBIF_BX0_DRIVER_SCRATCH_1_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_2 0x0082 +#define regBIF_BX0_DRIVER_SCRATCH_2_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_3 0x0083 +#define regBIF_BX0_DRIVER_SCRATCH_3_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_4 0x0084 +#define regBIF_BX0_DRIVER_SCRATCH_4_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_5 0x0085 +#define regBIF_BX0_DRIVER_SCRATCH_5_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_6 0x0086 +#define regBIF_BX0_DRIVER_SCRATCH_6_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_7 0x0087 +#define regBIF_BX0_DRIVER_SCRATCH_7_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_8 0x0088 +#define regBIF_BX0_DRIVER_SCRATCH_8_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_9 0x0089 +#define regBIF_BX0_DRIVER_SCRATCH_9_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_10 0x008a +#define regBIF_BX0_DRIVER_SCRATCH_10_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_11 0x008b +#define regBIF_BX0_DRIVER_SCRATCH_11_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_12 0x008c +#define regBIF_BX0_DRIVER_SCRATCH_12_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_13 0x008d +#define regBIF_BX0_DRIVER_SCRATCH_13_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_14 0x008e +#define regBIF_BX0_DRIVER_SCRATCH_14_BASE_IDX 1 +#define regBIF_BX0_DRIVER_SCRATCH_15 0x008f +#define regBIF_BX0_DRIVER_SCRATCH_15_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_0 0x0090 +#define regBIF_BX0_FW_SCRATCH_0_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_1 0x0091 +#define regBIF_BX0_FW_SCRATCH_1_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_2 0x0092 +#define regBIF_BX0_FW_SCRATCH_2_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_3 0x0093 +#define regBIF_BX0_FW_SCRATCH_3_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_4 0x0094 +#define regBIF_BX0_FW_SCRATCH_4_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_5 0x0095 +#define regBIF_BX0_FW_SCRATCH_5_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_6 0x0096 +#define regBIF_BX0_FW_SCRATCH_6_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_7 0x0097 +#define regBIF_BX0_FW_SCRATCH_7_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_8 0x0098 +#define regBIF_BX0_FW_SCRATCH_8_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_9 0x0099 +#define regBIF_BX0_FW_SCRATCH_9_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_10 0x009a +#define regBIF_BX0_FW_SCRATCH_10_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_11 0x009b +#define regBIF_BX0_FW_SCRATCH_11_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_12 0x009c +#define regBIF_BX0_FW_SCRATCH_12_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_13 0x009d +#define regBIF_BX0_FW_SCRATCH_13_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_14 0x009e +#define regBIF_BX0_FW_SCRATCH_14_BASE_IDX 1 +#define regBIF_BX0_FW_SCRATCH_15 0x009f +#define regBIF_BX0_FW_SCRATCH_15_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_4 0x00a0 +#define regBIF_BX0_SBIOS_SCRATCH_4_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_5 0x00a1 +#define regBIF_BX0_SBIOS_SCRATCH_5_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_6 0x00a2 +#define regBIF_BX0_SBIOS_SCRATCH_6_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_7 0x00a3 +#define regBIF_BX0_SBIOS_SCRATCH_7_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_8 0x00a4 +#define regBIF_BX0_SBIOS_SCRATCH_8_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_9 0x00a5 +#define regBIF_BX0_SBIOS_SCRATCH_9_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_10 0x00a6 +#define regBIF_BX0_SBIOS_SCRATCH_10_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_11 0x00a7 +#define regBIF_BX0_SBIOS_SCRATCH_11_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_12 0x00a8 +#define regBIF_BX0_SBIOS_SCRATCH_12_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_13 0x00a9 +#define regBIF_BX0_SBIOS_SCRATCH_13_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_14 0x00aa +#define regBIF_BX0_SBIOS_SCRATCH_14_BASE_IDX 1 +#define regBIF_BX0_SBIOS_SCRATCH_15 0x00ab +#define regBIF_BX0_SBIOS_SCRATCH_15_BASE_IDX 1 + + +// addressBlock: aid_nbio_nbif0_rcc_dwn_dev0_BIFDEC1 +// base address: 0x0 +#define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED 0x0060 +#define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH 0x0061 +#define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_CNTL 0x0063 +#define regRCC_DWN_DEV0_0_DN_PCIE_CNTL_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL 0x0064 +#define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2 0x0065 +#define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL 0x0066 +#define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL 0x0067 +#define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0 0x0068 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC 0x0069 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC_BASE_IDX 2 +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2 0x006a +#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 +// base address: 0x0 +#define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL 0x006c +#define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL 0x006d +#define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL 0x006e +#define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2 0x006f +#define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC 0x0070 +#define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC_BASE_IDX 2 +#define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP 0x0071 +#define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_ep_dev0_BIFDEC1 +// base address: 0x0 +#define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH 0x0040 +#define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_CNTL 0x0042 +#define regRCC_EP_DEV0_0_EP_PCIE_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL 0x0043 +#define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS 0x0044 +#define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2 0x0045 +#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL 0x0046 +#define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL 0x0047 +#define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0x0049 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x004a +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x004a +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x004a +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x004a +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x004b +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x004b +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x004b +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x004b +#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC 0x004c +#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2 0x004d +#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP 0x004f +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0050 +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL 0x0050 +#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0050 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0051 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0051 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0051 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0051 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0052 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0052 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0052 +#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL 0x0052 +#define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED 0x0053 +#define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL 0x0055 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID 0x0056 +#define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL 0x0057 +#define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL 0x0058 +#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL_BASE_IDX 2 +#define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL 0x0059 +#define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_pf_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_PF0_MM_INDEX 0x0000 +#define regBIF_BX_PF0_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_PF0_MM_DATA 0x0001 +#define regBIF_BX_PF0_MM_DATA_BASE_IDX 0 +#define regBIF_BX_PF0_MM_INDEX_HI 0x0006 +#define regBIF_BX_PF0_MM_INDEX_HI_BASE_IDX 0 +#define regBIF_BX_PF0_RSMU_INDEX 0x0000 +#define regBIF_BX_PF0_RSMU_INDEX_BASE_IDX 1 +#define regBIF_BX_PF0_RSMU_DATA 0x0001 +#define regBIF_BX_PF0_RSMU_DATA_BASE_IDX 1 +#define regBIF_BX_PF0_RSMU_INDEX_HI 0x0002 +#define regBIF_BX_PF0_RSMU_INDEX_HI_BASE_IDX 1 + + +// addressBlock: aid_nbio_nbif0_bif_bx_BIFDEC1 +// base address: 0x0 +#define regBIF_BX0_CC_BIF_BX_STRAP0 0x00e2 +#define regBIF_BX0_CC_BIF_BX_STRAP0_BASE_IDX 2 +#define regBIF_BX0_CC_BIF_BX_PINSTRAP0 0x00e4 +#define regBIF_BX0_CC_BIF_BX_PINSTRAP0_BASE_IDX 2 +#define regBIF_BX0_BIF_MM_INDACCESS_CNTL 0x00e6 +#define regBIF_BX0_BIF_MM_INDACCESS_CNTL_BASE_IDX 2 +#define regBIF_BX0_BUS_CNTL 0x00e7 +#define regBIF_BX0_BUS_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_SCRATCH0 0x00e8 +#define regBIF_BX0_BIF_SCRATCH0_BASE_IDX 2 +#define regBIF_BX0_BIF_SCRATCH1 0x00e9 +#define regBIF_BX0_BIF_SCRATCH1_BASE_IDX 2 +#define regBIF_BX0_BX_RESET_EN 0x00ed +#define regBIF_BX0_BX_RESET_EN_BASE_IDX 2 +#define regBIF_BX0_MM_CFGREGS_CNTL 0x00ee +#define regBIF_BX0_MM_CFGREGS_CNTL_BASE_IDX 2 +#define regBIF_BX0_BX_RESET_CNTL 0x00f0 +#define regBIF_BX0_BX_RESET_CNTL_BASE_IDX 2 +#define regBIF_BX0_INTERRUPT_CNTL 0x00f1 +#define regBIF_BX0_INTERRUPT_CNTL_BASE_IDX 2 +#define regBIF_BX0_INTERRUPT_CNTL2 0x00f2 +#define regBIF_BX0_INTERRUPT_CNTL2_BASE_IDX 2 +#define regBIF_BX0_CLKREQB_PAD_CNTL 0x00f8 +#define regBIF_BX0_CLKREQB_PAD_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_FEATURES_CONTROL_MISC 0x00fb +#define regBIF_BX0_BIF_FEATURES_CONTROL_MISC_BASE_IDX 2 +#define regBIF_BX0_HDP_ATOMIC_CONTROL_MISC 0x00fc +#define regBIF_BX0_HDP_ATOMIC_CONTROL_MISC_BASE_IDX 2 +#define regBIF_BX0_BIF_DOORBELL_CNTL 0x00fd +#define regBIF_BX0_BIF_DOORBELL_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_DOORBELL_INT_CNTL 0x00fe +#define regBIF_BX0_BIF_DOORBELL_INT_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_FB_EN 0x0100 +#define regBIF_BX0_BIF_FB_EN_BASE_IDX 2 +#define regBIF_BX0_BIF_INTR_CNTL 0x0101 +#define regBIF_BX0_BIF_INTR_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_MST_TRANS_PENDING_VF 0x0109 +#define regBIF_BX0_BIF_MST_TRANS_PENDING_VF_BASE_IDX 2 +#define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF 0x010a +#define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF_BASE_IDX 2 +#define regBIF_BX0_BACO_CNTL 0x010b +#define regBIF_BX0_BACO_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_BACO_EXIT_TIME0 0x010c +#define regBIF_BX0_BIF_BACO_EXIT_TIME0_BASE_IDX 2 +#define regBIF_BX0_BIF_BACO_EXIT_TIMER1 0x010d +#define regBIF_BX0_BIF_BACO_EXIT_TIMER1_BASE_IDX 2 +#define regBIF_BX0_BIF_BACO_EXIT_TIMER2 0x010e +#define regBIF_BX0_BIF_BACO_EXIT_TIMER2_BASE_IDX 2 +#define regBIF_BX0_BIF_BACO_EXIT_TIMER3 0x010f +#define regBIF_BX0_BIF_BACO_EXIT_TIMER3_BASE_IDX 2 +#define regBIF_BX0_BIF_BACO_EXIT_TIMER4 0x0110 +#define regBIF_BX0_BIF_BACO_EXIT_TIMER4_BASE_IDX 2 +#define regBIF_BX0_MEM_TYPE_CNTL 0x0111 +#define regBIF_BX0_MEM_TYPE_CNTL_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL 0x0113 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_0 0x0114 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_0_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_1 0x0115 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_1_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_2 0x0116 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_2_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_3 0x0117 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_3_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_4 0x0118 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_4_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_5 0x0119 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_5_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_6 0x011a +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_6_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_7 0x011b +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_7_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_8 0x011c +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_8_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_9 0x011d +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_9_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_10 0x011e +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_10_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_11 0x011f +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_11_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_12 0x0120 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_12_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_13 0x0121 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_13_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_14 0x0122 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_14_BASE_IDX 2 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_15 0x0123 +#define regBIF_BX0_NBIF_GFX_ADDR_LUT_15_BASE_IDX 2 +#define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL 0x012d +#define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL 0x012e +#define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_CNTL 0x012f +#define regBIF_BX0_BIF_RB_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_BASE 0x0130 +#define regBIF_BX0_BIF_RB_BASE_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_RPTR 0x0131 +#define regBIF_BX0_BIF_RB_RPTR_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_WPTR 0x0132 +#define regBIF_BX0_BIF_RB_WPTR_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_WPTR_ADDR_HI 0x0133 +#define regBIF_BX0_BIF_RB_WPTR_ADDR_HI_BASE_IDX 2 +#define regBIF_BX0_BIF_RB_WPTR_ADDR_LO 0x0134 +#define regBIF_BX0_BIF_RB_WPTR_ADDR_LO_BASE_IDX 2 +#define regBIF_BX0_MAILBOX_INDEX 0x0135 +#define regBIF_BX0_MAILBOX_INDEX_BASE_IDX 2 +#define regBIF_BX0_BIF_MP1_INTR_CTRL 0x0142 +#define regBIF_BX0_BIF_MP1_INTR_CTRL_BASE_IDX 2 +#define regBIF_BX0_BIF_PERSTB_PAD_CNTL 0x0146 +#define regBIF_BX0_BIF_PERSTB_PAD_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_PX_EN_PAD_CNTL 0x0147 +#define regBIF_BX0_BIF_PX_EN_PAD_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_REFPADKIN_PAD_CNTL 0x0148 +#define regBIF_BX0_BIF_REFPADKIN_PAD_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_CLKREQB_PAD_CNTL 0x0149 +#define regBIF_BX0_BIF_CLKREQB_PAD_CNTL_BASE_IDX 2 +#define regBIF_BX0_BIF_PWRBRK_PAD_CNTL 0x014a +#define regBIF_BX0_BIF_PWRBRK_PAD_CNTL_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_BIFDEC1 +// base address: 0x0 +#define regRCC_DEV0_0_RCC_ERR_INT_CNTL 0x0086 +#define regRCC_DEV0_0_RCC_ERR_INT_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BACO_CNTL_MISC 0x0087 +#define regRCC_DEV0_0_RCC_BACO_CNTL_MISC_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_RESET_EN 0x0088 +#define regRCC_DEV0_0_RCC_RESET_EN_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_VDM_SUPPORT 0x0089 +#define regRCC_DEV0_0_RCC_VDM_SUPPORT_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0 0x008a +#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1 0x008b +#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_GPUIOV_REGION 0x008c +#define regRCC_DEV0_0_RCC_GPUIOV_REGION_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN 0x008d +#define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL 0x008e +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0x008f +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE 0x008f +#define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER_REG_RANGE0 0x00be +#define regRCC_DEV0_0_RCC_PEER_REG_RANGE0_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER_REG_RANGE1 0x00bf +#define regRCC_DEV0_0_RCC_PEER_REG_RANGE1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUS_CNTL 0x00c1 +#define regRCC_DEV0_0_RCC_BUS_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONFIG_CNTL 0x00c2 +#define regRCC_DEV0_0_RCC_CONFIG_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONFIG_F0_BASE 0x00c6 +#define regRCC_DEV0_0_RCC_CONFIG_F0_BASE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE 0x00c7 +#define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE 0x00c8 +#define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_XDMA_LO 0x00c9 +#define regRCC_DEV0_0_RCC_XDMA_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_XDMA_HI 0x00ca +#define regRCC_DEV0_0_RCC_XDMA_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC 0x00cb +#define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUSNUM_CNTL1 0x00cc +#define regRCC_DEV0_0_RCC_BUSNUM_CNTL1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUSNUM_LIST0 0x00cd +#define regRCC_DEV0_0_RCC_BUSNUM_LIST0_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUSNUM_LIST1 0x00ce +#define regRCC_DEV0_0_RCC_BUSNUM_LIST1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_BUSNUM_CNTL2 0x00cf +#define regRCC_DEV0_0_RCC_BUSNUM_CNTL2_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM 0x00d0 +#define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_HOST_BUSNUM 0x00d1 +#define regRCC_DEV0_0_RCC_HOST_BUSNUM_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI 0x00d2 +#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO 0x00d3 +#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI 0x00d4 +#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO 0x00d5 +#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI 0x00d6 +#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO 0x00d7 +#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI 0x00d8 +#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO 0x00d9 +#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0 0x00da +#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1 0x00db +#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL 0x00dd +#define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_CMN_LINK_CNTL 0x00de +#define regRCC_DEV0_0_RCC_CMN_LINK_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE 0x00df +#define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL 0x00e0 +#define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL_BASE_IDX 2 +#define regRCC_DEV0_0_RCC_MH_ARB_CNTL 0x00e1 +#define regRCC_DEV0_0_RCC_MH_ARB_CNTL_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_GFXMSIX_PBA_BASE_IDX 4 + + +// addressBlock: aid_nbio_nbif0_rcc_strap_BIFDEC1 +// base address: 0x0 +#define regRCC_STRAP0_RCC_BIF_STRAP0 0x0000 +#define regRCC_STRAP0_RCC_BIF_STRAP0_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP1 0x0001 +#define regRCC_STRAP0_RCC_BIF_STRAP1_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP2 0x0002 +#define regRCC_STRAP0_RCC_BIF_STRAP2_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP3 0x0003 +#define regRCC_STRAP0_RCC_BIF_STRAP3_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP4 0x0004 +#define regRCC_STRAP0_RCC_BIF_STRAP4_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP5 0x0005 +#define regRCC_STRAP0_RCC_BIF_STRAP5_BASE_IDX 2 +#define regRCC_STRAP0_RCC_BIF_STRAP6 0x0006 +#define regRCC_STRAP0_RCC_BIF_STRAP6_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0 0x0007 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1 0x0008 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP10 0x0009 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP10_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP11 0x000a +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP11_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP12 0x000b +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP12_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP13 0x000c +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP13_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP14 0x000d +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP14_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2 0x000e +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3 0x000f +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4 0x0010 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5 0x0011 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6 0x0012 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7 0x0013 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8 0x0014 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9 0x0015 +#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0 0x0016 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1 0x0017 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13 0x0018 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14 0x0019 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15 0x001a +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16 0x001b +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17 0x001c +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18 0x001d +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2 0x001e +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP26 0x001f +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP26_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3 0x0020 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4 0x0021 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5 0x0022 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8 0x0024 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9 0x0025 +#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0 0x0026 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2 0x0032 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20 0x0033 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21 0x0034 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP22 0x0035 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP22_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23 0x0036 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24 0x0037 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP25 0x0038 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP25_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3 0x0039 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4 0x003a +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5 0x003b +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6 0x003c +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6_BASE_IDX 2 +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7 0x003d +#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_PF0_BIF_BME_STATUS 0x00eb +#define regBIF_BX_PF0_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_PF0_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_PF0_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_CONTROL 0x013e +#define regBIF_BX_PF0_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_PF0_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_PF0_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_PF0_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_PF0_BIF_VMHV_MAILBOX_BASE_IDX 2 +#define regBIF_BX_PF0_PARTITION_COMPUTE_CAP 0x0161 +#define regBIF_BX_PF0_PARTITION_COMPUTE_CAP_BASE_IDX 2 +#define regBIF_BX_PF0_PARTITION_MEM_CAP 0x0162 +#define regBIF_BX_PF0_PARTITION_MEM_CAP_BASE_IDX 2 +#define regBIF_BX_PF0_PARTITION_COMPUTE_STATUS 0x0163 +#define regBIF_BX_PF0_PARTITION_COMPUTE_STATUS_BASE_IDX 2 +#define regBIF_BX_PF0_PARTITION_MEM_STATUS 0x0164 +#define regBIF_BX_PF0_PARTITION_MEM_STATUS_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975] +// base address: 0x3480 +#define regRCC_DEV0_EPF0_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_gdc_GDCDEC +// base address: 0x0 +#define regGDC0_A2S_CNTL_CL0 0x0000 +#define regGDC0_A2S_CNTL_CL0_BASE_IDX 3 +#define regGDC0_A2S_CNTL_CL1 0x0001 +#define regGDC0_A2S_CNTL_CL1_BASE_IDX 3 +#define regGDC0_A2S_CNTL3_CL0 0x0018 +#define regGDC0_A2S_CNTL3_CL0_BASE_IDX 3 +#define regGDC0_A2S_CNTL3_CL1 0x0019 +#define regGDC0_A2S_CNTL3_CL1_BASE_IDX 3 +#define regGDC0_A2S_CNTL_SW0 0x0030 +#define regGDC0_A2S_CNTL_SW0_BASE_IDX 3 +#define regGDC0_A2S_CNTL_SW1 0x0031 +#define regGDC0_A2S_CNTL_SW1_BASE_IDX 3 +#define regGDC0_A2S_CNTL_SW2 0x0032 +#define regGDC0_A2S_CNTL_SW2_BASE_IDX 3 +#define regGDC0_A2S_TAG_ALLOC_0 0x003d +#define regGDC0_A2S_TAG_ALLOC_0_BASE_IDX 3 +#define regGDC0_A2S_TAG_ALLOC_1 0x003e +#define regGDC0_A2S_TAG_ALLOC_1_BASE_IDX 3 +#define regGDC0_A2S_MISC_CNTL 0x0041 +#define regGDC0_A2S_MISC_CNTL_BASE_IDX 3 +#define regGDC0_SHUB_REGS_IF_CTL 0x0043 +#define regGDC0_SHUB_REGS_IF_CTL_BASE_IDX 3 +#define regGDC0_NGDC_MGCG_CTRL 0x004a +#define regGDC0_NGDC_MGCG_CTRL_BASE_IDX 3 +#define regGDC0_NGDC_RESERVED_0 0x004b +#define regGDC0_NGDC_RESERVED_0_BASE_IDX 3 +#define regGDC0_NGDC_RESERVED_1 0x004c +#define regGDC0_NGDC_RESERVED_1_BASE_IDX 3 +#define regGDC0_NBIF_GFX_DOORBELL_STATUS 0x004f +#define regGDC0_NBIF_GFX_DOORBELL_STATUS_BASE_IDX 3 +#define regGDC0_ATDMA_MISC_CNTL 0x005d +#define regGDC0_ATDMA_MISC_CNTL_BASE_IDX 3 +#define regGDC0_S2A_MISC_CNTL 0x005f +#define regGDC0_S2A_MISC_CNTL_BASE_IDX 3 +#define regGDC0_NGDC_PG_MISC_CTRL 0x0078 +#define regGDC0_NGDC_PG_MISC_CTRL_BASE_IDX 3 +#define regGDC0_NGDC_PGMST_CTRL 0x0079 +#define regGDC0_NGDC_PGMST_CTRL_BASE_IDX 3 +#define regGDC0_NGDC_PGSLV_CTRL 0x007a +#define regGDC0_NGDC_PGSLV_CTRL_BASE_IDX 3 + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST 0x0048 +#define cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID_W 0x004c +#define cfgBIF_CFG_DEV0_EPF0_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_EPF0_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST 0x0110 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1 0x0114 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2 0x0118 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL 0x011c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS 0x011e +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP 0x0120 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL 0x0124 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS 0x012a +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP 0x012c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL 0x0130 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS 0x0136 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST 0x0200 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP 0x0204 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL 0x0208 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP 0x020c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL 0x0210 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP 0x0214 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL 0x0218 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP 0x021c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL 0x0220 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP 0x0224 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL 0x0228 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP 0x022c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL 0x0230 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA 0x0248 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP 0x024c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST 0x0250 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP 0x0254 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR 0x0258 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS 0x025c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL 0x025e +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3 0x0274 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS 0x0278 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL 0x02b6 +#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 +#define cfgPCIE_PAGE_REQ_CNTL 0x02c4 +#define cfgPCIE_PAGE_REQ_STATUS 0x02c6 +#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 +#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST 0x02d0 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP 0x02d4 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL 0x02d6 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST 0x02f0 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_CAP 0x02f4 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_CNTL 0x02f6 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0 0x02f8 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1 0x02fc +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_RCV0 0x0300 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_RCV1 0x0304 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0 0x0308 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1 0x030c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST 0x0320 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x0324 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL 0x032e +#define cfgPCIE_SRIOV_ENH_CAP_LIST 0x0330 +#define cfgPCIE_SRIOV_CAP 0x0334 +#define cfgPCIE_SRIOV_CONTROL 0x0338 +#define cfgPCIE_SRIOV_STATUS 0x033a +#define cfgPCIE_SRIOV_INITIAL_VFS 0x033c +#define cfgPCIE_SRIOV_TOTAL_VFS 0x033e +#define cfgPCIE_SRIOV_NUM_VFS 0x0340 +#define cfgPCIE_SRIOV_FUNC_DEP_LINK 0x0342 +#define cfgPCIE_SRIOV_FIRST_VF_OFFSET 0x0344 +#define cfgPCIE_SRIOV_VF_STRIDE 0x0346 +#define cfgPCIE_SRIOV_VF_DEVICE_ID 0x034a +#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c +#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_0 0x0354 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_1 0x0358 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_2 0x035c +#define cfgPCIE_SRIOV_VF_BASE_ADDR_3 0x0360 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_4 0x0364 +#define cfgPCIE_SRIOV_VF_BASE_ADDR_5 0x0368 +#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c +#define cfgBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP 0x0404 +#define cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS 0x0408 +#define cfgBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP_16GT 0x0414 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT 0x0418 +#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT 0x041c +#define cfgBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 +#define cfgBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 +#define cfgBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 +#define cfgBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 +#define cfgBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 +#define cfgBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 +#define cfgBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 +#define cfgBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 +#define cfgBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 +#define cfgBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 +#define cfgBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 +#define cfgBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 +#define cfgBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 +#define cfgBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a +#define cfgBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b +#define cfgBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c +#define cfgBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d +#define cfgBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e +#define cfgBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f +#define cfgBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST 0x0450 +#define cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP 0x0454 +#define cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS 0x0456 +#define cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL 0x0458 +#define cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS 0x045a +#define cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL 0x045c +#define cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS 0x045e +#define cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL 0x0460 +#define cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS 0x0462 +#define cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL 0x0464 +#define cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS 0x0466 +#define cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL 0x0468 +#define cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS 0x046a +#define cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL 0x046c +#define cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS 0x046e +#define cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL 0x0470 +#define cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS 0x0472 +#define cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL 0x0474 +#define cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS 0x0476 +#define cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL 0x0478 +#define cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS 0x047a +#define cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL 0x047c +#define cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS 0x047e +#define cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL 0x0480 +#define cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS 0x0482 +#define cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL 0x0484 +#define cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS 0x0486 +#define cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL 0x0488 +#define cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS 0x048a +#define cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL 0x048c +#define cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS 0x048e +#define cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL 0x0490 +#define cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS 0x0492 +#define cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL 0x0494 +#define cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS 0x0496 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP_32GT 0x0504 +#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL_32GT 0x0508 +#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS_32GT 0x050c +#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0700 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0704 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0708 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x070c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0710 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0714 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0718 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x071c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0720 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0724 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0728 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0x0730 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0x0734 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0738 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x073c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0740 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x0744 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0748 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x074c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0750 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x0754 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0758 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x075c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0760 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x0764 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0768 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x076c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0770 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x0774 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0x0778 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0x077c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0x0780 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0x0784 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0x0788 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0x078c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0x0790 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0x0794 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0x0798 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0x079c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0x07a0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0x07a4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0x07a8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0x07ac +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0x07b0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x07c0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1 0x07c4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2 0x07c8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3 0x07cc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4 0x07d0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0 0x07f0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1 0x07f4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2 0x07f8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3 0x07fc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4 0x0800 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5 0x0804 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6 0x0808 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7 0x080c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8 0x0810 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0x0820 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0x0824 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0x0828 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0x082c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0x0830 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0x0834 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0x0838 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0x083c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0x0840 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0 0x0850 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1 0x0854 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2 0x0858 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3 0x085c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4 0x0860 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5 0x0864 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6 0x0868 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7 0x086c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8 0x0870 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0 0x0880 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1 0x0884 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2 0x0888 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3 0x088c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4 0x0890 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5 0x0894 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6 0x0898 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7 0x089c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8 0x08a0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0 0x08b0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1 0x08b4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2 0x08b8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3 0x08bc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4 0x08c0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5 0x08c4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6 0x08c8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7 0x08cc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8 0x08d0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0 0x08e0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1 0x08e4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2 0x08e8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3 0x08ec +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4 0x08f0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5 0x08f4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6 0x08f8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7 0x08fc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8 0x0900 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0 0x0910 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1 0x0914 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2 0x0918 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3 0x091c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4 0x0920 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5 0x0924 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6 0x0928 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7 0x092c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8 0x0930 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0 0x0940 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1 0x0944 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2 0x0948 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3 0x094c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4 0x0950 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5 0x0954 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6 0x0958 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7 0x095c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8 0x0960 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0 0x0970 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1 0x0974 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2 0x0978 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3 0x097c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4 0x0980 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5 0x0984 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6 0x0988 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7 0x098c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8 0x0990 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0 0x09a0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1 0x09a4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2 0x09a8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3 0x09ac +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4 0x09b0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5 0x09b4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6 0x09b8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7 0x09bc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8 0x09c0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0 0x09d0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1 0x09d4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2 0x09d8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3 0x09dc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4 0x09e0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5 0x09e4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6 0x09e8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7 0x09ec +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8 0x09f0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0 0x0a00 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1 0x0a04 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2 0x0a08 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3 0x0a0c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4 0x0a10 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5 0x0a14 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6 0x0a18 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7 0x0a1c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8 0x0a20 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0 0x0a30 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1 0x0a34 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2 0x0a38 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3 0x0a3c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4 0x0a40 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5 0x0a44 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6 0x0a48 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7 0x0a4c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8 0x0a50 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0 0x0a60 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1 0x0a64 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2 0x0a68 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3 0x0a6c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4 0x0a70 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5 0x0a74 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6 0x0a78 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7 0x0a7c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8 0x0a80 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0 0x0a90 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1 0x0a94 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2 0x0a98 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3 0x0a9c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4 0x0aa0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5 0x0aa4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6 0x0aa8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7 0x0aac +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8 0x0ab0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0 0x0ac0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1 0x0ac4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2 0x0ac8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3 0x0acc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4 0x0ad0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5 0x0ad4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6 0x0ad8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7 0x0adc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8 0x0ae0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0 0x0af0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1 0x0af4 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2 0x0af8 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3 0x0afc +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4 0x0b00 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5 0x0b04 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6 0x0b08 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7 0x0b0c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8 0x0b10 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0 0x0b20 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1 0x0b24 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2 0x0b28 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3 0x0b2c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4 0x0b30 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5 0x0b34 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6 0x0b38 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7 0x0b3c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8 0x0b40 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0 0x0b50 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1 0x0b54 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2 0x0b58 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3 0x0b5c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4 0x0b60 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5 0x0b64 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6 0x0b68 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7 0x0b6c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8 0x0b70 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0 0x0b80 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1 0x0b84 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2 0x0b88 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3 0x0b8c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4 0x0b90 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5 0x0b94 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6 0x0b98 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7 0x0b9c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8 0x0ba0 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE 0x0c00 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_ENABLE 0x0c04 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE 0x0c08 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE 0x0c0c +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS 0x0c10 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_STATUS 0x0c14 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS 0x0c18 +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS 0x0c1c + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF1_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF1_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF1_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF1_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF1_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST 0x0048 +#define cfgBIF_CFG_DEV0_EPF1_ADAPTER_ID_W 0x004c +#define cfgBIF_CFG_DEV0_EPF1_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_EPF1_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF1_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF1_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF1_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF1_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF1_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF1_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF1_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF1_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF1_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF1_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF1_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF1_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF1_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF1_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF1_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF1_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF1_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF1_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST 0x0200 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP 0x0204 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL 0x0208 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP 0x020c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL 0x0210 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP 0x0214 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL 0x0218 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP 0x021c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL 0x0220 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP 0x0224 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL 0x0228 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP 0x022c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL 0x0230 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA 0x0248 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP 0x024c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST 0x0250 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP 0x0254 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR 0x0258 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS 0x025c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL 0x025e +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST 0x02d0 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP 0x02d4 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL 0x02d6 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL 0x032e + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp +// base address: 0x10100000 +#define regBIF_CFG_DEV0_RC0_VENDOR_ID 0x0000 +#define regBIF_CFG_DEV0_RC0_VENDOR_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_DEVICE_ID 0x0000 +#define regBIF_CFG_DEV0_RC0_DEVICE_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_COMMAND 0x0001 +#define regBIF_CFG_DEV0_RC0_COMMAND_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_STATUS 0x0001 +#define regBIF_CFG_DEV0_RC0_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_REVISION_ID 0x0002 +#define regBIF_CFG_DEV0_RC0_REVISION_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PROG_INTERFACE 0x0002 +#define regBIF_CFG_DEV0_RC0_PROG_INTERFACE_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SUB_CLASS 0x0002 +#define regBIF_CFG_DEV0_RC0_SUB_CLASS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_BASE_CLASS 0x0002 +#define regBIF_CFG_DEV0_RC0_BASE_CLASS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_CACHE_LINE 0x0003 +#define regBIF_CFG_DEV0_RC0_CACHE_LINE_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LATENCY 0x0003 +#define regBIF_CFG_DEV0_RC0_LATENCY_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_HEADER 0x0003 +#define regBIF_CFG_DEV0_RC0_HEADER_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_BIST 0x0003 +#define regBIF_CFG_DEV0_RC0_BIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_BASE_ADDR_1 0x0004 +#define regBIF_CFG_DEV0_RC0_BASE_ADDR_1_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_BASE_ADDR_2 0x0005 +#define regBIF_CFG_DEV0_RC0_BASE_ADDR_2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY 0x0006 +#define regBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT 0x0007 +#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SECONDARY_STATUS 0x0007 +#define regBIF_CFG_DEV0_RC0_SECONDARY_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT 0x0008 +#define regBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT 0x0009 +#define regBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PREF_BASE_UPPER 0x000a +#define regBIF_CFG_DEV0_RC0_PREF_BASE_UPPER_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER 0x000b +#define regBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI 0x000c +#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_CAP_PTR 0x000d +#define regBIF_CFG_DEV0_RC0_CAP_PTR_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_ROM_BASE_ADDR 0x000e +#define regBIF_CFG_DEV0_RC0_ROM_BASE_ADDR_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_INTERRUPT_LINE 0x000f +#define regBIF_CFG_DEV0_RC0_INTERRUPT_LINE_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_INTERRUPT_PIN 0x000f +#define regBIF_CFG_DEV0_RC0_INTERRUPT_PIN_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL 0x000f +#define regBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL 0x0010 +#define regBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PMI_CAP_LIST 0x0014 +#define regBIF_CFG_DEV0_RC0_PMI_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PMI_CAP 0x0014 +#define regBIF_CFG_DEV0_RC0_PMI_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL 0x0015 +#define regBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_CAP_LIST 0x0016 +#define regBIF_CFG_DEV0_RC0_PCIE_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_CAP 0x0016 +#define regBIF_CFG_DEV0_RC0_PCIE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_DEVICE_CAP 0x0017 +#define regBIF_CFG_DEV0_RC0_DEVICE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL 0x0018 +#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS 0x0018 +#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_CAP 0x0019 +#define regBIF_CFG_DEV0_RC0_LINK_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL 0x001a +#define regBIF_CFG_DEV0_RC0_LINK_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS 0x001a +#define regBIF_CFG_DEV0_RC0_LINK_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SLOT_CAP 0x001b +#define regBIF_CFG_DEV0_RC0_SLOT_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SLOT_CNTL 0x001c +#define regBIF_CFG_DEV0_RC0_SLOT_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SLOT_STATUS 0x001c +#define regBIF_CFG_DEV0_RC0_SLOT_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_ROOT_CNTL 0x001d +#define regBIF_CFG_DEV0_RC0_ROOT_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_ROOT_CAP 0x001d +#define regBIF_CFG_DEV0_RC0_ROOT_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_ROOT_STATUS 0x001e +#define regBIF_CFG_DEV0_RC0_ROOT_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_DEVICE_CAP2 0x001f +#define regBIF_CFG_DEV0_RC0_DEVICE_CAP2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL2 0x0020 +#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS2 0x0020 +#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_CAP2 0x0021 +#define regBIF_CFG_DEV0_RC0_LINK_CAP2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL2 0x0022 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS2 0x0022 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SLOT_CAP2 0x0023 +#define regBIF_CFG_DEV0_RC0_SLOT_CAP2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SLOT_CNTL2 0x0024 +#define regBIF_CFG_DEV0_RC0_SLOT_CNTL2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SLOT_STATUS2 0x0024 +#define regBIF_CFG_DEV0_RC0_SLOT_STATUS2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MSI_CAP_LIST 0x0028 +#define regBIF_CFG_DEV0_RC0_MSI_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_CNTL 0x0028 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO 0x0029 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI 0x002a +#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA 0x002a +#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA 0x002a +#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64 0x002b +#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64 0x002b +#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SSID_CAP_LIST 0x0030 +#define regBIF_CFG_DEV0_RC0_SSID_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_SSID_CAP 0x0031 +#define regBIF_CFG_DEV0_RC0_SSID_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0040 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR 0x0041 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1 0x0042 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2 0x0043 +#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST 0x0044 +#define regBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1 0x0045 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2 0x0046 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL 0x0047 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS 0x0047 +#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP 0x0048 +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL 0x0049 +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS 0x004a +#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP 0x004b +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL 0x004c +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS 0x004d +#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0050 +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1 0x0051 +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2 0x0052 +#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0054 +#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS 0x0055 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK 0x0056 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY 0x0057 +#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS 0x0058 +#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK 0x0059 +#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL 0x005a +#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0 0x005b +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1 0x005c +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2 0x005d +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3 0x005e +#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD 0x005f +#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS 0x0060 +#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID 0x0061 +#define regBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0 0x0062 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1 0x0063 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2 0x0064 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3 0x0065 +#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST 0x009c +#define regBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3 0x009d +#define regBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS 0x009e +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL 0x009f +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL 0x009f +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL 0x00a0 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL 0x00a0 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL 0x00a1 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL 0x00a1 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL 0x00a2 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL 0x00a2 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL 0x00a3 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL 0x00a3 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL 0x00a4 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL 0x00a4 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL 0x00a5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL 0x00a5 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL 0x00a6 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL 0x00a6 +#define regBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST 0x00a8 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CAP 0x00a9 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL 0x00a9 +#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST 0x0100 +#define regBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP 0x0101 +#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS 0x0102 +#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST 0x0104 +#define regBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_CAP_16GT 0x0105 +#define regBIF_CFG_DEV0_RC0_LINK_CAP_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL_16GT 0x0106 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS_16GT 0x0107 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0108 +#define regBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0109 +#define regBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x010a +#define regBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT 0x010c +#define regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT 0x010c +#define regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT 0x010c +#define regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT 0x010c +#define regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT 0x010d +#define regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT 0x010d +#define regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT 0x010d +#define regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT 0x010d +#define regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT 0x010e +#define regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT 0x010e +#define regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT 0x010e +#define regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT 0x010e +#define regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT 0x010f +#define regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT 0x010f +#define regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT 0x010f +#define regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT 0x010f +#define regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST 0x0114 +#define regBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP 0x0115 +#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS 0x0115 +#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL 0x0116 +#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS 0x0116 +#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL 0x0117 +#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS 0x0117 +#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL 0x0118 +#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS 0x0118 +#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL 0x0119 +#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS 0x0119 +#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL 0x011a +#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS 0x011a +#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL 0x011b +#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS 0x011b +#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL 0x011c +#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS 0x011c +#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL 0x011d +#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS 0x011d +#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL 0x011e +#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS 0x011e +#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL 0x011f +#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS 0x011f +#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL 0x0120 +#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS 0x0120 +#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL 0x0121 +#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS 0x0121 +#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL 0x0122 +#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS 0x0122 +#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL 0x0123 +#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS 0x0123 +#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL 0x0124 +#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS 0x0124 +#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL 0x0125 +#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS 0x0125 +#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_CAP_32GT 0x0141 +#define regBIF_CFG_DEV0_RC0_LINK_CAP_32GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL_32GT 0x0142 +#define regBIF_CFG_DEV0_RC0_LINK_CNTL_32GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS_32GT 0x0143 +#define regBIF_CFG_DEV0_RC0_LINK_STATUS_32GT_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp +// base address: 0x10140000 +#define regBIF_CFG_DEV0_EPF0_0_VENDOR_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_0_VENDOR_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_ID 0x10000 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_COMMAND 0x10001 +#define regBIF_CFG_DEV0_EPF0_0_COMMAND_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_STATUS 0x10001 +#define regBIF_CFG_DEV0_EPF0_0_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_REVISION_ID 0x10002 +#define regBIF_CFG_DEV0_EPF0_0_REVISION_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE 0x10002 +#define regBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_SUB_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_0_SUB_CLASS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_BASE_CLASS 0x10002 +#define regBIF_CFG_DEV0_EPF0_0_BASE_CLASS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_CACHE_LINE 0x10003 +#define regBIF_CFG_DEV0_EPF0_0_CACHE_LINE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LATENCY 0x10003 +#define regBIF_CFG_DEV0_EPF0_0_LATENCY_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_HEADER 0x10003 +#define regBIF_CFG_DEV0_EPF0_0_HEADER_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_BIST 0x10003 +#define regBIF_CFG_DEV0_EPF0_0_BIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 0x10004 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 0x10005 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 0x10006 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 0x10007 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 0x10008 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 0x10009 +#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR 0x1000a +#define regBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID 0x1000b +#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR 0x1000c +#define regBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_CAP_PTR 0x1000d +#define regBIF_CFG_DEV0_EPF0_0_CAP_PTR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE 0x1000f +#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN 0x1000f +#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MIN_GRANT 0x1000f +#define regBIF_CFG_DEV0_EPF0_0_MIN_GRANT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MAX_LATENCY 0x1000f +#define regBIF_CFG_DEV0_EPF0_0_MAX_LATENCY_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST 0x10012 +#define regBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W 0x10013 +#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST 0x10014 +#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP 0x10014 +#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL 0x10015 +#define regBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST 0x10019 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP 0x10019 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP 0x1001a +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL 0x1001b +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS 0x1001b +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP 0x1001c +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL 0x1001d +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS 0x1001d +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 0x10022 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 0x10023 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 0x10023 +#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP2 0x10024 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL2 0x10025 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS2 0x10025 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST 0x10028 +#define regBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL 0x10028 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO 0x10029 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI 0x1002a +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA 0x1002a +#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK 0x1002b +#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64 0x1002b +#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_64 0x1002c +#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING 0x1002c +#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 0x1002d +#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST 0x10030 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL 0x10030 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_TABLE 0x10031 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_TABLE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_PBA 0x10032 +#define regBIF_CFG_DEV0_EPF0_0_MSIX_PBA_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10040 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x10041 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 0x10042 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 0x10043 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST 0x10044 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 0x10045 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 0x10046 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL 0x10047 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS 0x10047 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP 0x10048 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0x10049 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0x1004a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP 0x1004b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0x1004c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0x1004d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x10050 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 0x10051 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 0x10052 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10054 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS 0x10055 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK 0x10056 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0x10057 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS 0x10058 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK 0x10059 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0x1005a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 0x1005b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 0x1005c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 0x1005d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 0x1005e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 0x10062 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 0x10063 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 0x10064 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 0x10065 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0x10080 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP 0x10081 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL 0x10082 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP 0x10083 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL 0x10084 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP 0x10085 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL 0x10086 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP 0x10087 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL 0x10088 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP 0x10089 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL 0x1008a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP 0x1008b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL 0x1008c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10090 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0x10091 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA 0x10092 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP 0x10093 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0x10094 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP 0x10095 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0x10096 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS 0x10097 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL 0x10097 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10098 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10098 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10098 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10098 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10099 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10099 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10099 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10099 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x1009c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 0x1009d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS 0x1009e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x1009f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x1009f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x100a0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x100a0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x100a1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x100a1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x100a2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x100a2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x100a3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x100a3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x100a4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x100a4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x100a5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x100a5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x100a6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x100a6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0x100a8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP 0x100a9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL 0x100a9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST 0x100ac +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP 0x100ad +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL 0x100ad +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x100b0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL 0x100b1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS 0x100b1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x100b2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x100b3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST 0x100b4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP 0x100b5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL 0x100b5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST 0x100bc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP 0x100bd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL 0x100bd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0 0x100be +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1 0x100bf +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0 0x100c0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1 0x100c1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0 0x100c2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1 0x100c3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x100c4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x100c5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0x100c8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP 0x100c9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0x100ca +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP 0x100cb +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL 0x100cb +#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST 0x100cc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP 0x100cd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL 0x100ce +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS 0x100ce +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS 0x100cf +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS 0x100cf +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS 0x100d0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK 0x100d0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x100d1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE 0x100d1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID 0x100d2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x100d3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x100d4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x100d5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x100d6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x100d7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x100d8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x100d9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x100da +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x100db +#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST 0x10100 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP 0x10101 +#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS 0x10102 +#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST 0x10104 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT 0x10105 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT 0x10106 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT 0x10107 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x10108 +#define regBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x10109 +#define regBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x1010a +#define regBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT 0x1010c +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT 0x1010c +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT 0x1010c +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT 0x1010c +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT 0x1010d +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT 0x1010d +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT 0x1010d +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT 0x1010d +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT 0x1010e +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT 0x1010e +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT 0x1010e +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT 0x1010e +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT 0x1010f +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT 0x1010f +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT 0x1010f +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT 0x1010f +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST 0x10114 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP 0x10115 +#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS 0x10115 +#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL 0x10116 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS 0x10116 +#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL 0x10117 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS 0x10117 +#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL 0x10118 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS 0x10118 +#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL 0x10119 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS 0x10119 +#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL 0x1011a +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS 0x1011a +#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL 0x1011b +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS 0x1011b +#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL 0x1011c +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS 0x1011c +#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL 0x1011d +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS 0x1011d +#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL 0x1011e +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS 0x1011e +#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL 0x1011f +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS 0x1011f +#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL 0x10120 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS 0x10120 +#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL 0x10121 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS 0x10121 +#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL 0x10122 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS 0x10122 +#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL 0x10123 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS 0x10123 +#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL 0x10124 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS 0x10124 +#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL 0x10125 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS 0x10125 +#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT 0x10141 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT 0x10142 +#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT 0x10143 +#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x101c0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x101c1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x101c2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x101c3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x101c4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x101c5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x101c6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x101c7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x101c8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x101c9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x101ca +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0x101cc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE 0x101cd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x101ce +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x101cf +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x101d0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x101d1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x101d2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x101d3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x101d4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x101d5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x101d6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x101d7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x101d8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x101d9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x101da +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x101db +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x101dc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x101dd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0x101de +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0x101df +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0x101e0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0x101e1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0x101e2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0x101e3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0x101e4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0x101e5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0x101e6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0x101e7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0x101e8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0x101e9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0x101ea +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0x101eb +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0x101ec +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x101f0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1 0x101f1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2 0x101f2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3 0x101f3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4 0x101f4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0 0x101fc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1 0x101fd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2 0x101fe +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3 0x101ff +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4 0x10200 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5 0x10201 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6 0x10202 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7 0x10203 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8 0x10204 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD0SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0 0x10208 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1 0x10209 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2 0x1020a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3 0x1020b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4 0x1020c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5 0x1020d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6 0x1020e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7 0x1020f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8 0x10210 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD1SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0 0x10214 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1 0x10215 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2 0x10216 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3 0x10217 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4 0x10218 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5 0x10219 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6 0x1021a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7 0x1021b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8 0x1021c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD2SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0 0x10220 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1 0x10221 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2 0x10222 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3 0x10223 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4 0x10224 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5 0x10225 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6 0x10226 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7 0x10227 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8 0x10228 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD3SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0 0x1022c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1 0x1022d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2 0x1022e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3 0x1022f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4 0x10230 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5 0x10231 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6 0x10232 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7 0x10233 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8 0x10234 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD4SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0 0x10238 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1 0x10239 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2 0x1023a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3 0x1023b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4 0x1023c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5 0x1023d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6 0x1023e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7 0x1023f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8 0x10240 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD5SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0 0x10244 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1 0x10245 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2 0x10246 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3 0x10247 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4 0x10248 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5 0x10249 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6 0x1024a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7 0x1024b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8 0x1024c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD6SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0 0x10250 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1 0x10251 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2 0x10252 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3 0x10253 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4 0x10254 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5 0x10255 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6 0x10256 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7 0x10257 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8 0x10258 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD7SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0 0x1025c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1 0x1025d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2 0x1025e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3 0x1025f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4 0x10260 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5 0x10261 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6 0x10262 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7 0x10263 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8 0x10264 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD8SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0 0x10268 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1 0x10269 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2 0x1026a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3 0x1026b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4 0x1026c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5 0x1026d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6 0x1026e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7 0x1026f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8 0x10270 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD9SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0 0x10274 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1 0x10275 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2 0x10276 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3 0x10277 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4 0x10278 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5 0x10279 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6 0x1027a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7 0x1027b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8 0x1027c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD10SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0 0x10280 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1 0x10281 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2 0x10282 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3 0x10283 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4 0x10284 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5 0x10285 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6 0x10286 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7 0x10287 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8 0x10288 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVD11SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0 0x1028c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1 0x1028d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2 0x1028e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3 0x1028f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4 0x10290 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5 0x10291 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6 0x10292 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7 0x10293 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8 0x10294 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX0SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0 0x10298 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1 0x10299 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2 0x1029a +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3 0x1029b +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4 0x1029c +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5 0x1029d +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6 0x1029e +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7 0x1029f +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8 0x102a0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX1SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0 0x102a4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1 0x102a5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2 0x102a6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3 0x102a7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4 0x102a8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5 0x102a9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6 0x102aa +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7 0x102ab +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8 0x102ac +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX2SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0 0x102b0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1 0x102b1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2 0x102b2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3 0x102b3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4 0x102b4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5 0x102b5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6 0x102b6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7 0x102b7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8 0x102b8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX3SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0 0x102bc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1 0x102bd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2 0x102be +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3 0x102bf +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4 0x102c0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5 0x102c1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6 0x102c2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7 0x102c3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8 0x102c4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX4SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0 0x102c8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1 0x102c9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2 0x102ca +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3 0x102cb +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4 0x102cc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5 0x102cd +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6 0x102ce +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7 0x102cf +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8 0x102d0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX5SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0 0x102d4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1 0x102d5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2 0x102d6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3 0x102d7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4 0x102d8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5 0x102d9 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6 0x102da +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7 0x102db +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8 0x102dc +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX6SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0 0x102e0 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1 0x102e1 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2 0x102e2 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3 0x102e3 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4 0x102e4 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5 0x102e5 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6 0x102e6 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7 0x102e7 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8 0x102e8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFX7SCH_DW8_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE 0x10300 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_ENABLE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_ENABLE 0x10301 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_ENABLE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE 0x10302 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_ENABLE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE 0x10303 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_ENABLE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS 0x10304 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A0_7_INTR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_STATUS 0x10305 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGA_A8_15_INTR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS 0x10306 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B0_7_INTR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS 0x10307 +#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENGB_B8_15_INTR_STATUS_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp +// base address: 0x10141000 +#define regBIF_CFG_DEV0_EPF1_0_VENDOR_ID 0x10400 +#define regBIF_CFG_DEV0_EPF1_0_VENDOR_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_ID 0x10400 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_COMMAND 0x10401 +#define regBIF_CFG_DEV0_EPF1_0_COMMAND_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_STATUS 0x10401 +#define regBIF_CFG_DEV0_EPF1_0_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_REVISION_ID 0x10402 +#define regBIF_CFG_DEV0_EPF1_0_REVISION_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE 0x10402 +#define regBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_SUB_CLASS 0x10402 +#define regBIF_CFG_DEV0_EPF1_0_SUB_CLASS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_BASE_CLASS 0x10402 +#define regBIF_CFG_DEV0_EPF1_0_BASE_CLASS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_CACHE_LINE 0x10403 +#define regBIF_CFG_DEV0_EPF1_0_CACHE_LINE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_LATENCY 0x10403 +#define regBIF_CFG_DEV0_EPF1_0_LATENCY_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_HEADER 0x10403 +#define regBIF_CFG_DEV0_EPF1_0_HEADER_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_BIST 0x10403 +#define regBIF_CFG_DEV0_EPF1_0_BIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 0x10404 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 0x10405 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 0x10406 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 0x10407 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 0x10408 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 0x10409 +#define regBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR 0x1040a +#define regBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID 0x1040b +#define regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR 0x1040c +#define regBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_CAP_PTR 0x1040d +#define regBIF_CFG_DEV0_EPF1_0_CAP_PTR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE 0x1040f +#define regBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN 0x1040f +#define regBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MIN_GRANT 0x1040f +#define regBIF_CFG_DEV0_EPF1_0_MIN_GRANT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MAX_LATENCY 0x1040f +#define regBIF_CFG_DEV0_EPF1_0_MAX_LATENCY_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST 0x10412 +#define regBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W 0x10413 +#define regBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST 0x10414 +#define regBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PMI_CAP 0x10414 +#define regBIF_CFG_DEV0_EPF1_0_PMI_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL 0x10415 +#define regBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST 0x10419 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_CAP 0x10419 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP 0x1041a +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL 0x1041b +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS 0x1041b +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_LINK_CAP 0x1041c +#define regBIF_CFG_DEV0_EPF1_0_LINK_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_LINK_CNTL 0x1041d +#define regBIF_CFG_DEV0_EPF1_0_LINK_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_LINK_STATUS 0x1041d +#define regBIF_CFG_DEV0_EPF1_0_LINK_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 0x10422 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 0x10423 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 0x10423 +#define regBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_LINK_CAP2 0x10424 +#define regBIF_CFG_DEV0_EPF1_0_LINK_CAP2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_LINK_CNTL2 0x10425 +#define regBIF_CFG_DEV0_EPF1_0_LINK_CNTL2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_LINK_STATUS2 0x10425 +#define regBIF_CFG_DEV0_EPF1_0_LINK_STATUS2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST 0x10428 +#define regBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL 0x10428 +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO 0x10429 +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI 0x1042a +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA 0x1042a +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA 0x1042a +#define regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_MASK 0x1042b +#define regBIF_CFG_DEV0_EPF1_0_MSI_MASK_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 0x1042b +#define regBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64 0x1042b +#define regBIF_CFG_DEV0_EPF1_0_MSI_EXT_MSG_DATA_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_MASK_64 0x1042c +#define regBIF_CFG_DEV0_EPF1_0_MSI_MASK_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_PENDING 0x1042c +#define regBIF_CFG_DEV0_EPF1_0_MSI_PENDING_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 0x1042d +#define regBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST 0x10430 +#define regBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL 0x10430 +#define regBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSIX_TABLE 0x10431 +#define regBIF_CFG_DEV0_EPF1_0_MSIX_TABLE_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_MSIX_PBA 0x10432 +#define regBIF_CFG_DEV0_EPF1_0_MSIX_PBA_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x10440 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x10441 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 0x10442 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 0x10443 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x10454 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS 0x10455 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK 0x10456 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0x10457 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS 0x10458 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK 0x10459 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0x1045a +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 0x1045b +#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 0x1045c +#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 0x1045d +#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 0x1045e +#define regBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 0x10462 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 0x10463 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 0x10464 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 0x10465 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0x10480 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP 0x10481 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL 0x10482 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP 0x10483 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL 0x10484 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP 0x10485 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL 0x10486 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP 0x10487 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL 0x10488 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP 0x10489 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL 0x1048a +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP 0x1048b +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL 0x1048c +#define regBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x10490 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0x10491 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA 0x10492 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP 0x10493 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0x10494 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP 0x10495 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0x10496 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS 0x10497 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL 0x10497 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x10498 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x10498 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x10498 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x10498 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x10499 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x10499 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x10499 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x10499 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0x104a8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP 0x104a9 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL 0x104a9 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST 0x104b4 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP 0x104b5 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL 0x104b5 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0x104ca +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP 0x104cb +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP_BASE_IDX 8 +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL 0x104cb +#define regBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_RCCPORTDEC +// base address: 0x10131000 +#define regRCC_DEV0_1_RCC_VDM_SUPPORT 0xc440 +#define regRCC_DEV0_1_RCC_VDM_SUPPORT_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_BUS_CNTL 0xc441 +#define regRCC_DEV0_1_RCC_BUS_CNTL_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC 0xc442 +#define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL 0xc443 +#define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_CMN_LINK_CNTL 0xc444 +#define regRCC_DEV0_1_RCC_CMN_LINK_CNTL_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE 0xc445 +#define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL 0xc446 +#define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_MH_ARB_CNTL 0xc447 +#define regRCC_DEV0_1_RCC_MH_ARB_CNTL_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0 0xc448 +#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1 0xc449 +#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_ep_dev0_RCCPORTDEC +// base address: 0x10131000 +#define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH 0xc44c +#define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_CNTL 0xc44e +#define regRCC_EP_DEV0_1_EP_PCIE_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL 0xc44f +#define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS 0xc450 +#define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2 0xc451 +#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL 0xc452 +#define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL 0xc453 +#define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL 0xc454 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC 0xc455 +#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2 0xc456 +#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP 0xc457 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0xc458 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL 0xc458 +#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0xc458 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0xc459 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0xc459 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0xc459 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0xc459 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0xc45a +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0xc45a +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0xc45a +#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL 0xc45c +#define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED 0xc45d +#define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL 0xc45f +#define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID 0xc460 +#define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL 0xc461 +#define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL 0xc462 +#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL 0xc463 +#define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_dwn_dev0_RCCPORTDEC +// base address: 0x10131000 +#define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED 0xc468 +#define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED_BASE_IDX 8 +#define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH 0xc469 +#define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH_BASE_IDX 8 +#define regRCC_DWN_DEV0_1_DN_PCIE_CNTL 0xc46b +#define regRCC_DWN_DEV0_1_DN_PCIE_CNTL_BASE_IDX 8 +#define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL 0xc46c +#define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL_BASE_IDX 8 +#define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2 0xc46d +#define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2_BASE_IDX 8 +#define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL 0xc46e +#define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL_BASE_IDX 8 +#define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL 0xc46f +#define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL_BASE_IDX 8 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0 0xc470 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0_BASE_IDX 8 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC 0xc471 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC_BASE_IDX 8 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2 0xc472 +#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_dwnp_dev0_RCCPORTDEC +// base address: 0x10131000 +#define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL 0xc475 +#define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL_BASE_IDX 8 +#define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL 0xc476 +#define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL_BASE_IDX 8 +#define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL 0xc477 +#define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL_BASE_IDX 8 +#define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2 0xc478 +#define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2_BASE_IDX 8 +#define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC 0xc479 +#define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC_BASE_IDX 8 +#define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP 0xc47a +#define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_pfc_amdgfx_RCCPFCDEC +// base address: 0x10134000 +#define regRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL 0xd040 +#define regRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL_BASE_IDX 8 +#define regRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE 0xd041 +#define regRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE_BASE_IDX 8 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0 0xd042 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0_BASE_IDX 8 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1 0xd043 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1_BASE_IDX 8 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2 0xd044 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2_BASE_IDX 8 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3 0xd045 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3_BASE_IDX 8 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4 0xd046 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4_BASE_IDX 8 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5 0xd047 +#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5_BASE_IDX 8 +#define regRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL 0xd048 +#define regRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_pciemsix_0_usb_MSIXTDEC +// base address: 0x10168000 +#define regPCIEMSIX_VECT0_ADDR_LO 0x1a000 +#define regPCIEMSIX_VECT0_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT0_ADDR_HI 0x1a001 +#define regPCIEMSIX_VECT0_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT0_MSG_DATA 0x1a002 +#define regPCIEMSIX_VECT0_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT0_CONTROL 0x1a003 +#define regPCIEMSIX_VECT0_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT1_ADDR_LO 0x1a004 +#define regPCIEMSIX_VECT1_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT1_ADDR_HI 0x1a005 +#define regPCIEMSIX_VECT1_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT1_MSG_DATA 0x1a006 +#define regPCIEMSIX_VECT1_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT1_CONTROL 0x1a007 +#define regPCIEMSIX_VECT1_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT2_ADDR_LO 0x1a008 +#define regPCIEMSIX_VECT2_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT2_ADDR_HI 0x1a009 +#define regPCIEMSIX_VECT2_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT2_MSG_DATA 0x1a00a +#define regPCIEMSIX_VECT2_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT2_CONTROL 0x1a00b +#define regPCIEMSIX_VECT2_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT3_ADDR_LO 0x1a00c +#define regPCIEMSIX_VECT3_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT3_ADDR_HI 0x1a00d +#define regPCIEMSIX_VECT3_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT3_MSG_DATA 0x1a00e +#define regPCIEMSIX_VECT3_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT3_CONTROL 0x1a00f +#define regPCIEMSIX_VECT3_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT4_ADDR_LO 0x1a010 +#define regPCIEMSIX_VECT4_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT4_ADDR_HI 0x1a011 +#define regPCIEMSIX_VECT4_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT4_MSG_DATA 0x1a012 +#define regPCIEMSIX_VECT4_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT4_CONTROL 0x1a013 +#define regPCIEMSIX_VECT4_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT5_ADDR_LO 0x1a014 +#define regPCIEMSIX_VECT5_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT5_ADDR_HI 0x1a015 +#define regPCIEMSIX_VECT5_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT5_MSG_DATA 0x1a016 +#define regPCIEMSIX_VECT5_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT5_CONTROL 0x1a017 +#define regPCIEMSIX_VECT5_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT6_ADDR_LO 0x1a018 +#define regPCIEMSIX_VECT6_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT6_ADDR_HI 0x1a019 +#define regPCIEMSIX_VECT6_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT6_MSG_DATA 0x1a01a +#define regPCIEMSIX_VECT6_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT6_CONTROL 0x1a01b +#define regPCIEMSIX_VECT6_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT7_ADDR_LO 0x1a01c +#define regPCIEMSIX_VECT7_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT7_ADDR_HI 0x1a01d +#define regPCIEMSIX_VECT7_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT7_MSG_DATA 0x1a01e +#define regPCIEMSIX_VECT7_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT7_CONTROL 0x1a01f +#define regPCIEMSIX_VECT7_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT8_ADDR_LO 0x1a020 +#define regPCIEMSIX_VECT8_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT8_ADDR_HI 0x1a021 +#define regPCIEMSIX_VECT8_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT8_MSG_DATA 0x1a022 +#define regPCIEMSIX_VECT8_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT8_CONTROL 0x1a023 +#define regPCIEMSIX_VECT8_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT9_ADDR_LO 0x1a024 +#define regPCIEMSIX_VECT9_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT9_ADDR_HI 0x1a025 +#define regPCIEMSIX_VECT9_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT9_MSG_DATA 0x1a026 +#define regPCIEMSIX_VECT9_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT9_CONTROL 0x1a027 +#define regPCIEMSIX_VECT9_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT10_ADDR_LO 0x1a028 +#define regPCIEMSIX_VECT10_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT10_ADDR_HI 0x1a029 +#define regPCIEMSIX_VECT10_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT10_MSG_DATA 0x1a02a +#define regPCIEMSIX_VECT10_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT10_CONTROL 0x1a02b +#define regPCIEMSIX_VECT10_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT11_ADDR_LO 0x1a02c +#define regPCIEMSIX_VECT11_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT11_ADDR_HI 0x1a02d +#define regPCIEMSIX_VECT11_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT11_MSG_DATA 0x1a02e +#define regPCIEMSIX_VECT11_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT11_CONTROL 0x1a02f +#define regPCIEMSIX_VECT11_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT12_ADDR_LO 0x1a030 +#define regPCIEMSIX_VECT12_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT12_ADDR_HI 0x1a031 +#define regPCIEMSIX_VECT12_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT12_MSG_DATA 0x1a032 +#define regPCIEMSIX_VECT12_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT12_CONTROL 0x1a033 +#define regPCIEMSIX_VECT12_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT13_ADDR_LO 0x1a034 +#define regPCIEMSIX_VECT13_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT13_ADDR_HI 0x1a035 +#define regPCIEMSIX_VECT13_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT13_MSG_DATA 0x1a036 +#define regPCIEMSIX_VECT13_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT13_CONTROL 0x1a037 +#define regPCIEMSIX_VECT13_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT14_ADDR_LO 0x1a038 +#define regPCIEMSIX_VECT14_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT14_ADDR_HI 0x1a039 +#define regPCIEMSIX_VECT14_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT14_MSG_DATA 0x1a03a +#define regPCIEMSIX_VECT14_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT14_CONTROL 0x1a03b +#define regPCIEMSIX_VECT14_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT15_ADDR_LO 0x1a03c +#define regPCIEMSIX_VECT15_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT15_ADDR_HI 0x1a03d +#define regPCIEMSIX_VECT15_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT15_MSG_DATA 0x1a03e +#define regPCIEMSIX_VECT15_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT15_CONTROL 0x1a03f +#define regPCIEMSIX_VECT15_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT16_ADDR_LO 0x1a040 +#define regPCIEMSIX_VECT16_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT16_ADDR_HI 0x1a041 +#define regPCIEMSIX_VECT16_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT16_MSG_DATA 0x1a042 +#define regPCIEMSIX_VECT16_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT16_CONTROL 0x1a043 +#define regPCIEMSIX_VECT16_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT17_ADDR_LO 0x1a044 +#define regPCIEMSIX_VECT17_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT17_ADDR_HI 0x1a045 +#define regPCIEMSIX_VECT17_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT17_MSG_DATA 0x1a046 +#define regPCIEMSIX_VECT17_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT17_CONTROL 0x1a047 +#define regPCIEMSIX_VECT17_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT18_ADDR_LO 0x1a048 +#define regPCIEMSIX_VECT18_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT18_ADDR_HI 0x1a049 +#define regPCIEMSIX_VECT18_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT18_MSG_DATA 0x1a04a +#define regPCIEMSIX_VECT18_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT18_CONTROL 0x1a04b +#define regPCIEMSIX_VECT18_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT19_ADDR_LO 0x1a04c +#define regPCIEMSIX_VECT19_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT19_ADDR_HI 0x1a04d +#define regPCIEMSIX_VECT19_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT19_MSG_DATA 0x1a04e +#define regPCIEMSIX_VECT19_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT19_CONTROL 0x1a04f +#define regPCIEMSIX_VECT19_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT20_ADDR_LO 0x1a050 +#define regPCIEMSIX_VECT20_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT20_ADDR_HI 0x1a051 +#define regPCIEMSIX_VECT20_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT20_MSG_DATA 0x1a052 +#define regPCIEMSIX_VECT20_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT20_CONTROL 0x1a053 +#define regPCIEMSIX_VECT20_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT21_ADDR_LO 0x1a054 +#define regPCIEMSIX_VECT21_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT21_ADDR_HI 0x1a055 +#define regPCIEMSIX_VECT21_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT21_MSG_DATA 0x1a056 +#define regPCIEMSIX_VECT21_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT21_CONTROL 0x1a057 +#define regPCIEMSIX_VECT21_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT22_ADDR_LO 0x1a058 +#define regPCIEMSIX_VECT22_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT22_ADDR_HI 0x1a059 +#define regPCIEMSIX_VECT22_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT22_MSG_DATA 0x1a05a +#define regPCIEMSIX_VECT22_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT22_CONTROL 0x1a05b +#define regPCIEMSIX_VECT22_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT23_ADDR_LO 0x1a05c +#define regPCIEMSIX_VECT23_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT23_ADDR_HI 0x1a05d +#define regPCIEMSIX_VECT23_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT23_MSG_DATA 0x1a05e +#define regPCIEMSIX_VECT23_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT23_CONTROL 0x1a05f +#define regPCIEMSIX_VECT23_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT24_ADDR_LO 0x1a060 +#define regPCIEMSIX_VECT24_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT24_ADDR_HI 0x1a061 +#define regPCIEMSIX_VECT24_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT24_MSG_DATA 0x1a062 +#define regPCIEMSIX_VECT24_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT24_CONTROL 0x1a063 +#define regPCIEMSIX_VECT24_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT25_ADDR_LO 0x1a064 +#define regPCIEMSIX_VECT25_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT25_ADDR_HI 0x1a065 +#define regPCIEMSIX_VECT25_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT25_MSG_DATA 0x1a066 +#define regPCIEMSIX_VECT25_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT25_CONTROL 0x1a067 +#define regPCIEMSIX_VECT25_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT26_ADDR_LO 0x1a068 +#define regPCIEMSIX_VECT26_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT26_ADDR_HI 0x1a069 +#define regPCIEMSIX_VECT26_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT26_MSG_DATA 0x1a06a +#define regPCIEMSIX_VECT26_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT26_CONTROL 0x1a06b +#define regPCIEMSIX_VECT26_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT27_ADDR_LO 0x1a06c +#define regPCIEMSIX_VECT27_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT27_ADDR_HI 0x1a06d +#define regPCIEMSIX_VECT27_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT27_MSG_DATA 0x1a06e +#define regPCIEMSIX_VECT27_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT27_CONTROL 0x1a06f +#define regPCIEMSIX_VECT27_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT28_ADDR_LO 0x1a070 +#define regPCIEMSIX_VECT28_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT28_ADDR_HI 0x1a071 +#define regPCIEMSIX_VECT28_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT28_MSG_DATA 0x1a072 +#define regPCIEMSIX_VECT28_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT28_CONTROL 0x1a073 +#define regPCIEMSIX_VECT28_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT29_ADDR_LO 0x1a074 +#define regPCIEMSIX_VECT29_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT29_ADDR_HI 0x1a075 +#define regPCIEMSIX_VECT29_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT29_MSG_DATA 0x1a076 +#define regPCIEMSIX_VECT29_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT29_CONTROL 0x1a077 +#define regPCIEMSIX_VECT29_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT30_ADDR_LO 0x1a078 +#define regPCIEMSIX_VECT30_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT30_ADDR_HI 0x1a079 +#define regPCIEMSIX_VECT30_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT30_MSG_DATA 0x1a07a +#define regPCIEMSIX_VECT30_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT30_CONTROL 0x1a07b +#define regPCIEMSIX_VECT30_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT31_ADDR_LO 0x1a07c +#define regPCIEMSIX_VECT31_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT31_ADDR_HI 0x1a07d +#define regPCIEMSIX_VECT31_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT31_MSG_DATA 0x1a07e +#define regPCIEMSIX_VECT31_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT31_CONTROL 0x1a07f +#define regPCIEMSIX_VECT31_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT32_ADDR_LO 0x1a080 +#define regPCIEMSIX_VECT32_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT32_ADDR_HI 0x1a081 +#define regPCIEMSIX_VECT32_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT32_MSG_DATA 0x1a082 +#define regPCIEMSIX_VECT32_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT32_CONTROL 0x1a083 +#define regPCIEMSIX_VECT32_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT33_ADDR_LO 0x1a084 +#define regPCIEMSIX_VECT33_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT33_ADDR_HI 0x1a085 +#define regPCIEMSIX_VECT33_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT33_MSG_DATA 0x1a086 +#define regPCIEMSIX_VECT33_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT33_CONTROL 0x1a087 +#define regPCIEMSIX_VECT33_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT34_ADDR_LO 0x1a088 +#define regPCIEMSIX_VECT34_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT34_ADDR_HI 0x1a089 +#define regPCIEMSIX_VECT34_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT34_MSG_DATA 0x1a08a +#define regPCIEMSIX_VECT34_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT34_CONTROL 0x1a08b +#define regPCIEMSIX_VECT34_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT35_ADDR_LO 0x1a08c +#define regPCIEMSIX_VECT35_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT35_ADDR_HI 0x1a08d +#define regPCIEMSIX_VECT35_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT35_MSG_DATA 0x1a08e +#define regPCIEMSIX_VECT35_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT35_CONTROL 0x1a08f +#define regPCIEMSIX_VECT35_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT36_ADDR_LO 0x1a090 +#define regPCIEMSIX_VECT36_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT36_ADDR_HI 0x1a091 +#define regPCIEMSIX_VECT36_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT36_MSG_DATA 0x1a092 +#define regPCIEMSIX_VECT36_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT36_CONTROL 0x1a093 +#define regPCIEMSIX_VECT36_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT37_ADDR_LO 0x1a094 +#define regPCIEMSIX_VECT37_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT37_ADDR_HI 0x1a095 +#define regPCIEMSIX_VECT37_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT37_MSG_DATA 0x1a096 +#define regPCIEMSIX_VECT37_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT37_CONTROL 0x1a097 +#define regPCIEMSIX_VECT37_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT38_ADDR_LO 0x1a098 +#define regPCIEMSIX_VECT38_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT38_ADDR_HI 0x1a099 +#define regPCIEMSIX_VECT38_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT38_MSG_DATA 0x1a09a +#define regPCIEMSIX_VECT38_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT38_CONTROL 0x1a09b +#define regPCIEMSIX_VECT38_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT39_ADDR_LO 0x1a09c +#define regPCIEMSIX_VECT39_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT39_ADDR_HI 0x1a09d +#define regPCIEMSIX_VECT39_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT39_MSG_DATA 0x1a09e +#define regPCIEMSIX_VECT39_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT39_CONTROL 0x1a09f +#define regPCIEMSIX_VECT39_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT40_ADDR_LO 0x1a0a0 +#define regPCIEMSIX_VECT40_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT40_ADDR_HI 0x1a0a1 +#define regPCIEMSIX_VECT40_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT40_MSG_DATA 0x1a0a2 +#define regPCIEMSIX_VECT40_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT40_CONTROL 0x1a0a3 +#define regPCIEMSIX_VECT40_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT41_ADDR_LO 0x1a0a4 +#define regPCIEMSIX_VECT41_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT41_ADDR_HI 0x1a0a5 +#define regPCIEMSIX_VECT41_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT41_MSG_DATA 0x1a0a6 +#define regPCIEMSIX_VECT41_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT41_CONTROL 0x1a0a7 +#define regPCIEMSIX_VECT41_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT42_ADDR_LO 0x1a0a8 +#define regPCIEMSIX_VECT42_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT42_ADDR_HI 0x1a0a9 +#define regPCIEMSIX_VECT42_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT42_MSG_DATA 0x1a0aa +#define regPCIEMSIX_VECT42_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT42_CONTROL 0x1a0ab +#define regPCIEMSIX_VECT42_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT43_ADDR_LO 0x1a0ac +#define regPCIEMSIX_VECT43_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT43_ADDR_HI 0x1a0ad +#define regPCIEMSIX_VECT43_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT43_MSG_DATA 0x1a0ae +#define regPCIEMSIX_VECT43_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT43_CONTROL 0x1a0af +#define regPCIEMSIX_VECT43_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT44_ADDR_LO 0x1a0b0 +#define regPCIEMSIX_VECT44_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT44_ADDR_HI 0x1a0b1 +#define regPCIEMSIX_VECT44_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT44_MSG_DATA 0x1a0b2 +#define regPCIEMSIX_VECT44_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT44_CONTROL 0x1a0b3 +#define regPCIEMSIX_VECT44_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT45_ADDR_LO 0x1a0b4 +#define regPCIEMSIX_VECT45_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT45_ADDR_HI 0x1a0b5 +#define regPCIEMSIX_VECT45_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT45_MSG_DATA 0x1a0b6 +#define regPCIEMSIX_VECT45_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT45_CONTROL 0x1a0b7 +#define regPCIEMSIX_VECT45_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT46_ADDR_LO 0x1a0b8 +#define regPCIEMSIX_VECT46_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT46_ADDR_HI 0x1a0b9 +#define regPCIEMSIX_VECT46_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT46_MSG_DATA 0x1a0ba +#define regPCIEMSIX_VECT46_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT46_CONTROL 0x1a0bb +#define regPCIEMSIX_VECT46_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT47_ADDR_LO 0x1a0bc +#define regPCIEMSIX_VECT47_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT47_ADDR_HI 0x1a0bd +#define regPCIEMSIX_VECT47_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT47_MSG_DATA 0x1a0be +#define regPCIEMSIX_VECT47_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT47_CONTROL 0x1a0bf +#define regPCIEMSIX_VECT47_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT48_ADDR_LO 0x1a0c0 +#define regPCIEMSIX_VECT48_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT48_ADDR_HI 0x1a0c1 +#define regPCIEMSIX_VECT48_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT48_MSG_DATA 0x1a0c2 +#define regPCIEMSIX_VECT48_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT48_CONTROL 0x1a0c3 +#define regPCIEMSIX_VECT48_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT49_ADDR_LO 0x1a0c4 +#define regPCIEMSIX_VECT49_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT49_ADDR_HI 0x1a0c5 +#define regPCIEMSIX_VECT49_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT49_MSG_DATA 0x1a0c6 +#define regPCIEMSIX_VECT49_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT49_CONTROL 0x1a0c7 +#define regPCIEMSIX_VECT49_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT50_ADDR_LO 0x1a0c8 +#define regPCIEMSIX_VECT50_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT50_ADDR_HI 0x1a0c9 +#define regPCIEMSIX_VECT50_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT50_MSG_DATA 0x1a0ca +#define regPCIEMSIX_VECT50_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT50_CONTROL 0x1a0cb +#define regPCIEMSIX_VECT50_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT51_ADDR_LO 0x1a0cc +#define regPCIEMSIX_VECT51_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT51_ADDR_HI 0x1a0cd +#define regPCIEMSIX_VECT51_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT51_MSG_DATA 0x1a0ce +#define regPCIEMSIX_VECT51_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT51_CONTROL 0x1a0cf +#define regPCIEMSIX_VECT51_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT52_ADDR_LO 0x1a0d0 +#define regPCIEMSIX_VECT52_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT52_ADDR_HI 0x1a0d1 +#define regPCIEMSIX_VECT52_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT52_MSG_DATA 0x1a0d2 +#define regPCIEMSIX_VECT52_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT52_CONTROL 0x1a0d3 +#define regPCIEMSIX_VECT52_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT53_ADDR_LO 0x1a0d4 +#define regPCIEMSIX_VECT53_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT53_ADDR_HI 0x1a0d5 +#define regPCIEMSIX_VECT53_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT53_MSG_DATA 0x1a0d6 +#define regPCIEMSIX_VECT53_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT53_CONTROL 0x1a0d7 +#define regPCIEMSIX_VECT53_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT54_ADDR_LO 0x1a0d8 +#define regPCIEMSIX_VECT54_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT54_ADDR_HI 0x1a0d9 +#define regPCIEMSIX_VECT54_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT54_MSG_DATA 0x1a0da +#define regPCIEMSIX_VECT54_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT54_CONTROL 0x1a0db +#define regPCIEMSIX_VECT54_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT55_ADDR_LO 0x1a0dc +#define regPCIEMSIX_VECT55_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT55_ADDR_HI 0x1a0dd +#define regPCIEMSIX_VECT55_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT55_MSG_DATA 0x1a0de +#define regPCIEMSIX_VECT55_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT55_CONTROL 0x1a0df +#define regPCIEMSIX_VECT55_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT56_ADDR_LO 0x1a0e0 +#define regPCIEMSIX_VECT56_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT56_ADDR_HI 0x1a0e1 +#define regPCIEMSIX_VECT56_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT56_MSG_DATA 0x1a0e2 +#define regPCIEMSIX_VECT56_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT56_CONTROL 0x1a0e3 +#define regPCIEMSIX_VECT56_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT57_ADDR_LO 0x1a0e4 +#define regPCIEMSIX_VECT57_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT57_ADDR_HI 0x1a0e5 +#define regPCIEMSIX_VECT57_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT57_MSG_DATA 0x1a0e6 +#define regPCIEMSIX_VECT57_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT57_CONTROL 0x1a0e7 +#define regPCIEMSIX_VECT57_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT58_ADDR_LO 0x1a0e8 +#define regPCIEMSIX_VECT58_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT58_ADDR_HI 0x1a0e9 +#define regPCIEMSIX_VECT58_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT58_MSG_DATA 0x1a0ea +#define regPCIEMSIX_VECT58_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT58_CONTROL 0x1a0eb +#define regPCIEMSIX_VECT58_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT59_ADDR_LO 0x1a0ec +#define regPCIEMSIX_VECT59_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT59_ADDR_HI 0x1a0ed +#define regPCIEMSIX_VECT59_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT59_MSG_DATA 0x1a0ee +#define regPCIEMSIX_VECT59_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT59_CONTROL 0x1a0ef +#define regPCIEMSIX_VECT59_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT60_ADDR_LO 0x1a0f0 +#define regPCIEMSIX_VECT60_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT60_ADDR_HI 0x1a0f1 +#define regPCIEMSIX_VECT60_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT60_MSG_DATA 0x1a0f2 +#define regPCIEMSIX_VECT60_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT60_CONTROL 0x1a0f3 +#define regPCIEMSIX_VECT60_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT61_ADDR_LO 0x1a0f4 +#define regPCIEMSIX_VECT61_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT61_ADDR_HI 0x1a0f5 +#define regPCIEMSIX_VECT61_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT61_MSG_DATA 0x1a0f6 +#define regPCIEMSIX_VECT61_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT61_CONTROL 0x1a0f7 +#define regPCIEMSIX_VECT61_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT62_ADDR_LO 0x1a0f8 +#define regPCIEMSIX_VECT62_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT62_ADDR_HI 0x1a0f9 +#define regPCIEMSIX_VECT62_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT62_MSG_DATA 0x1a0fa +#define regPCIEMSIX_VECT62_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT62_CONTROL 0x1a0fb +#define regPCIEMSIX_VECT62_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT63_ADDR_LO 0x1a0fc +#define regPCIEMSIX_VECT63_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT63_ADDR_HI 0x1a0fd +#define regPCIEMSIX_VECT63_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT63_MSG_DATA 0x1a0fe +#define regPCIEMSIX_VECT63_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT63_CONTROL 0x1a0ff +#define regPCIEMSIX_VECT63_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT64_ADDR_LO 0x1a100 +#define regPCIEMSIX_VECT64_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT64_ADDR_HI 0x1a101 +#define regPCIEMSIX_VECT64_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT64_MSG_DATA 0x1a102 +#define regPCIEMSIX_VECT64_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT64_CONTROL 0x1a103 +#define regPCIEMSIX_VECT64_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT65_ADDR_LO 0x1a104 +#define regPCIEMSIX_VECT65_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT65_ADDR_HI 0x1a105 +#define regPCIEMSIX_VECT65_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT65_MSG_DATA 0x1a106 +#define regPCIEMSIX_VECT65_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT65_CONTROL 0x1a107 +#define regPCIEMSIX_VECT65_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT66_ADDR_LO 0x1a108 +#define regPCIEMSIX_VECT66_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT66_ADDR_HI 0x1a109 +#define regPCIEMSIX_VECT66_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT66_MSG_DATA 0x1a10a +#define regPCIEMSIX_VECT66_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT66_CONTROL 0x1a10b +#define regPCIEMSIX_VECT66_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT67_ADDR_LO 0x1a10c +#define regPCIEMSIX_VECT67_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT67_ADDR_HI 0x1a10d +#define regPCIEMSIX_VECT67_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT67_MSG_DATA 0x1a10e +#define regPCIEMSIX_VECT67_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT67_CONTROL 0x1a10f +#define regPCIEMSIX_VECT67_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT68_ADDR_LO 0x1a110 +#define regPCIEMSIX_VECT68_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT68_ADDR_HI 0x1a111 +#define regPCIEMSIX_VECT68_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT68_MSG_DATA 0x1a112 +#define regPCIEMSIX_VECT68_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT68_CONTROL 0x1a113 +#define regPCIEMSIX_VECT68_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT69_ADDR_LO 0x1a114 +#define regPCIEMSIX_VECT69_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT69_ADDR_HI 0x1a115 +#define regPCIEMSIX_VECT69_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT69_MSG_DATA 0x1a116 +#define regPCIEMSIX_VECT69_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT69_CONTROL 0x1a117 +#define regPCIEMSIX_VECT69_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT70_ADDR_LO 0x1a118 +#define regPCIEMSIX_VECT70_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT70_ADDR_HI 0x1a119 +#define regPCIEMSIX_VECT70_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT70_MSG_DATA 0x1a11a +#define regPCIEMSIX_VECT70_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT70_CONTROL 0x1a11b +#define regPCIEMSIX_VECT70_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT71_ADDR_LO 0x1a11c +#define regPCIEMSIX_VECT71_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT71_ADDR_HI 0x1a11d +#define regPCIEMSIX_VECT71_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT71_MSG_DATA 0x1a11e +#define regPCIEMSIX_VECT71_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT71_CONTROL 0x1a11f +#define regPCIEMSIX_VECT71_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT72_ADDR_LO 0x1a120 +#define regPCIEMSIX_VECT72_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT72_ADDR_HI 0x1a121 +#define regPCIEMSIX_VECT72_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT72_MSG_DATA 0x1a122 +#define regPCIEMSIX_VECT72_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT72_CONTROL 0x1a123 +#define regPCIEMSIX_VECT72_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT73_ADDR_LO 0x1a124 +#define regPCIEMSIX_VECT73_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT73_ADDR_HI 0x1a125 +#define regPCIEMSIX_VECT73_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT73_MSG_DATA 0x1a126 +#define regPCIEMSIX_VECT73_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT73_CONTROL 0x1a127 +#define regPCIEMSIX_VECT73_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT74_ADDR_LO 0x1a128 +#define regPCIEMSIX_VECT74_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT74_ADDR_HI 0x1a129 +#define regPCIEMSIX_VECT74_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT74_MSG_DATA 0x1a12a +#define regPCIEMSIX_VECT74_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT74_CONTROL 0x1a12b +#define regPCIEMSIX_VECT74_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT75_ADDR_LO 0x1a12c +#define regPCIEMSIX_VECT75_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT75_ADDR_HI 0x1a12d +#define regPCIEMSIX_VECT75_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT75_MSG_DATA 0x1a12e +#define regPCIEMSIX_VECT75_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT75_CONTROL 0x1a12f +#define regPCIEMSIX_VECT75_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT76_ADDR_LO 0x1a130 +#define regPCIEMSIX_VECT76_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT76_ADDR_HI 0x1a131 +#define regPCIEMSIX_VECT76_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT76_MSG_DATA 0x1a132 +#define regPCIEMSIX_VECT76_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT76_CONTROL 0x1a133 +#define regPCIEMSIX_VECT76_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT77_ADDR_LO 0x1a134 +#define regPCIEMSIX_VECT77_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT77_ADDR_HI 0x1a135 +#define regPCIEMSIX_VECT77_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT77_MSG_DATA 0x1a136 +#define regPCIEMSIX_VECT77_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT77_CONTROL 0x1a137 +#define regPCIEMSIX_VECT77_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT78_ADDR_LO 0x1a138 +#define regPCIEMSIX_VECT78_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT78_ADDR_HI 0x1a139 +#define regPCIEMSIX_VECT78_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT78_MSG_DATA 0x1a13a +#define regPCIEMSIX_VECT78_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT78_CONTROL 0x1a13b +#define regPCIEMSIX_VECT78_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT79_ADDR_LO 0x1a13c +#define regPCIEMSIX_VECT79_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT79_ADDR_HI 0x1a13d +#define regPCIEMSIX_VECT79_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT79_MSG_DATA 0x1a13e +#define regPCIEMSIX_VECT79_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT79_CONTROL 0x1a13f +#define regPCIEMSIX_VECT79_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT80_ADDR_LO 0x1a140 +#define regPCIEMSIX_VECT80_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT80_ADDR_HI 0x1a141 +#define regPCIEMSIX_VECT80_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT80_MSG_DATA 0x1a142 +#define regPCIEMSIX_VECT80_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT80_CONTROL 0x1a143 +#define regPCIEMSIX_VECT80_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT81_ADDR_LO 0x1a144 +#define regPCIEMSIX_VECT81_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT81_ADDR_HI 0x1a145 +#define regPCIEMSIX_VECT81_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT81_MSG_DATA 0x1a146 +#define regPCIEMSIX_VECT81_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT81_CONTROL 0x1a147 +#define regPCIEMSIX_VECT81_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT82_ADDR_LO 0x1a148 +#define regPCIEMSIX_VECT82_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT82_ADDR_HI 0x1a149 +#define regPCIEMSIX_VECT82_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT82_MSG_DATA 0x1a14a +#define regPCIEMSIX_VECT82_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT82_CONTROL 0x1a14b +#define regPCIEMSIX_VECT82_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT83_ADDR_LO 0x1a14c +#define regPCIEMSIX_VECT83_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT83_ADDR_HI 0x1a14d +#define regPCIEMSIX_VECT83_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT83_MSG_DATA 0x1a14e +#define regPCIEMSIX_VECT83_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT83_CONTROL 0x1a14f +#define regPCIEMSIX_VECT83_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT84_ADDR_LO 0x1a150 +#define regPCIEMSIX_VECT84_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT84_ADDR_HI 0x1a151 +#define regPCIEMSIX_VECT84_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT84_MSG_DATA 0x1a152 +#define regPCIEMSIX_VECT84_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT84_CONTROL 0x1a153 +#define regPCIEMSIX_VECT84_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT85_ADDR_LO 0x1a154 +#define regPCIEMSIX_VECT85_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT85_ADDR_HI 0x1a155 +#define regPCIEMSIX_VECT85_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT85_MSG_DATA 0x1a156 +#define regPCIEMSIX_VECT85_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT85_CONTROL 0x1a157 +#define regPCIEMSIX_VECT85_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT86_ADDR_LO 0x1a158 +#define regPCIEMSIX_VECT86_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT86_ADDR_HI 0x1a159 +#define regPCIEMSIX_VECT86_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT86_MSG_DATA 0x1a15a +#define regPCIEMSIX_VECT86_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT86_CONTROL 0x1a15b +#define regPCIEMSIX_VECT86_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT87_ADDR_LO 0x1a15c +#define regPCIEMSIX_VECT87_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT87_ADDR_HI 0x1a15d +#define regPCIEMSIX_VECT87_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT87_MSG_DATA 0x1a15e +#define regPCIEMSIX_VECT87_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT87_CONTROL 0x1a15f +#define regPCIEMSIX_VECT87_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT88_ADDR_LO 0x1a160 +#define regPCIEMSIX_VECT88_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT88_ADDR_HI 0x1a161 +#define regPCIEMSIX_VECT88_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT88_MSG_DATA 0x1a162 +#define regPCIEMSIX_VECT88_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT88_CONTROL 0x1a163 +#define regPCIEMSIX_VECT88_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT89_ADDR_LO 0x1a164 +#define regPCIEMSIX_VECT89_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT89_ADDR_HI 0x1a165 +#define regPCIEMSIX_VECT89_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT89_MSG_DATA 0x1a166 +#define regPCIEMSIX_VECT89_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT89_CONTROL 0x1a167 +#define regPCIEMSIX_VECT89_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT90_ADDR_LO 0x1a168 +#define regPCIEMSIX_VECT90_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT90_ADDR_HI 0x1a169 +#define regPCIEMSIX_VECT90_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT90_MSG_DATA 0x1a16a +#define regPCIEMSIX_VECT90_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT90_CONTROL 0x1a16b +#define regPCIEMSIX_VECT90_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT91_ADDR_LO 0x1a16c +#define regPCIEMSIX_VECT91_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT91_ADDR_HI 0x1a16d +#define regPCIEMSIX_VECT91_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT91_MSG_DATA 0x1a16e +#define regPCIEMSIX_VECT91_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT91_CONTROL 0x1a16f +#define regPCIEMSIX_VECT91_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT92_ADDR_LO 0x1a170 +#define regPCIEMSIX_VECT92_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT92_ADDR_HI 0x1a171 +#define regPCIEMSIX_VECT92_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT92_MSG_DATA 0x1a172 +#define regPCIEMSIX_VECT92_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT92_CONTROL 0x1a173 +#define regPCIEMSIX_VECT92_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT93_ADDR_LO 0x1a174 +#define regPCIEMSIX_VECT93_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT93_ADDR_HI 0x1a175 +#define regPCIEMSIX_VECT93_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT93_MSG_DATA 0x1a176 +#define regPCIEMSIX_VECT93_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT93_CONTROL 0x1a177 +#define regPCIEMSIX_VECT93_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT94_ADDR_LO 0x1a178 +#define regPCIEMSIX_VECT94_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT94_ADDR_HI 0x1a179 +#define regPCIEMSIX_VECT94_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT94_MSG_DATA 0x1a17a +#define regPCIEMSIX_VECT94_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT94_CONTROL 0x1a17b +#define regPCIEMSIX_VECT94_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT95_ADDR_LO 0x1a17c +#define regPCIEMSIX_VECT95_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT95_ADDR_HI 0x1a17d +#define regPCIEMSIX_VECT95_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT95_MSG_DATA 0x1a17e +#define regPCIEMSIX_VECT95_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT95_CONTROL 0x1a17f +#define regPCIEMSIX_VECT95_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT96_ADDR_LO 0x1a180 +#define regPCIEMSIX_VECT96_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT96_ADDR_HI 0x1a181 +#define regPCIEMSIX_VECT96_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT96_MSG_DATA 0x1a182 +#define regPCIEMSIX_VECT96_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT96_CONTROL 0x1a183 +#define regPCIEMSIX_VECT96_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT97_ADDR_LO 0x1a184 +#define regPCIEMSIX_VECT97_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT97_ADDR_HI 0x1a185 +#define regPCIEMSIX_VECT97_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT97_MSG_DATA 0x1a186 +#define regPCIEMSIX_VECT97_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT97_CONTROL 0x1a187 +#define regPCIEMSIX_VECT97_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT98_ADDR_LO 0x1a188 +#define regPCIEMSIX_VECT98_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT98_ADDR_HI 0x1a189 +#define regPCIEMSIX_VECT98_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT98_MSG_DATA 0x1a18a +#define regPCIEMSIX_VECT98_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT98_CONTROL 0x1a18b +#define regPCIEMSIX_VECT98_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT99_ADDR_LO 0x1a18c +#define regPCIEMSIX_VECT99_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT99_ADDR_HI 0x1a18d +#define regPCIEMSIX_VECT99_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT99_MSG_DATA 0x1a18e +#define regPCIEMSIX_VECT99_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT99_CONTROL 0x1a18f +#define regPCIEMSIX_VECT99_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT100_ADDR_LO 0x1a190 +#define regPCIEMSIX_VECT100_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT100_ADDR_HI 0x1a191 +#define regPCIEMSIX_VECT100_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT100_MSG_DATA 0x1a192 +#define regPCIEMSIX_VECT100_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT100_CONTROL 0x1a193 +#define regPCIEMSIX_VECT100_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT101_ADDR_LO 0x1a194 +#define regPCIEMSIX_VECT101_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT101_ADDR_HI 0x1a195 +#define regPCIEMSIX_VECT101_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT101_MSG_DATA 0x1a196 +#define regPCIEMSIX_VECT101_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT101_CONTROL 0x1a197 +#define regPCIEMSIX_VECT101_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT102_ADDR_LO 0x1a198 +#define regPCIEMSIX_VECT102_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT102_ADDR_HI 0x1a199 +#define regPCIEMSIX_VECT102_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT102_MSG_DATA 0x1a19a +#define regPCIEMSIX_VECT102_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT102_CONTROL 0x1a19b +#define regPCIEMSIX_VECT102_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT103_ADDR_LO 0x1a19c +#define regPCIEMSIX_VECT103_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT103_ADDR_HI 0x1a19d +#define regPCIEMSIX_VECT103_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT103_MSG_DATA 0x1a19e +#define regPCIEMSIX_VECT103_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT103_CONTROL 0x1a19f +#define regPCIEMSIX_VECT103_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT104_ADDR_LO 0x1a1a0 +#define regPCIEMSIX_VECT104_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT104_ADDR_HI 0x1a1a1 +#define regPCIEMSIX_VECT104_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT104_MSG_DATA 0x1a1a2 +#define regPCIEMSIX_VECT104_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT104_CONTROL 0x1a1a3 +#define regPCIEMSIX_VECT104_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT105_ADDR_LO 0x1a1a4 +#define regPCIEMSIX_VECT105_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT105_ADDR_HI 0x1a1a5 +#define regPCIEMSIX_VECT105_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT105_MSG_DATA 0x1a1a6 +#define regPCIEMSIX_VECT105_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT105_CONTROL 0x1a1a7 +#define regPCIEMSIX_VECT105_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT106_ADDR_LO 0x1a1a8 +#define regPCIEMSIX_VECT106_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT106_ADDR_HI 0x1a1a9 +#define regPCIEMSIX_VECT106_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT106_MSG_DATA 0x1a1aa +#define regPCIEMSIX_VECT106_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT106_CONTROL 0x1a1ab +#define regPCIEMSIX_VECT106_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT107_ADDR_LO 0x1a1ac +#define regPCIEMSIX_VECT107_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT107_ADDR_HI 0x1a1ad +#define regPCIEMSIX_VECT107_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT107_MSG_DATA 0x1a1ae +#define regPCIEMSIX_VECT107_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT107_CONTROL 0x1a1af +#define regPCIEMSIX_VECT107_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT108_ADDR_LO 0x1a1b0 +#define regPCIEMSIX_VECT108_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT108_ADDR_HI 0x1a1b1 +#define regPCIEMSIX_VECT108_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT108_MSG_DATA 0x1a1b2 +#define regPCIEMSIX_VECT108_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT108_CONTROL 0x1a1b3 +#define regPCIEMSIX_VECT108_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT109_ADDR_LO 0x1a1b4 +#define regPCIEMSIX_VECT109_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT109_ADDR_HI 0x1a1b5 +#define regPCIEMSIX_VECT109_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT109_MSG_DATA 0x1a1b6 +#define regPCIEMSIX_VECT109_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT109_CONTROL 0x1a1b7 +#define regPCIEMSIX_VECT109_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT110_ADDR_LO 0x1a1b8 +#define regPCIEMSIX_VECT110_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT110_ADDR_HI 0x1a1b9 +#define regPCIEMSIX_VECT110_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT110_MSG_DATA 0x1a1ba +#define regPCIEMSIX_VECT110_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT110_CONTROL 0x1a1bb +#define regPCIEMSIX_VECT110_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT111_ADDR_LO 0x1a1bc +#define regPCIEMSIX_VECT111_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT111_ADDR_HI 0x1a1bd +#define regPCIEMSIX_VECT111_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT111_MSG_DATA 0x1a1be +#define regPCIEMSIX_VECT111_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT111_CONTROL 0x1a1bf +#define regPCIEMSIX_VECT111_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT112_ADDR_LO 0x1a1c0 +#define regPCIEMSIX_VECT112_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT112_ADDR_HI 0x1a1c1 +#define regPCIEMSIX_VECT112_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT112_MSG_DATA 0x1a1c2 +#define regPCIEMSIX_VECT112_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT112_CONTROL 0x1a1c3 +#define regPCIEMSIX_VECT112_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT113_ADDR_LO 0x1a1c4 +#define regPCIEMSIX_VECT113_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT113_ADDR_HI 0x1a1c5 +#define regPCIEMSIX_VECT113_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT113_MSG_DATA 0x1a1c6 +#define regPCIEMSIX_VECT113_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT113_CONTROL 0x1a1c7 +#define regPCIEMSIX_VECT113_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT114_ADDR_LO 0x1a1c8 +#define regPCIEMSIX_VECT114_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT114_ADDR_HI 0x1a1c9 +#define regPCIEMSIX_VECT114_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT114_MSG_DATA 0x1a1ca +#define regPCIEMSIX_VECT114_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT114_CONTROL 0x1a1cb +#define regPCIEMSIX_VECT114_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT115_ADDR_LO 0x1a1cc +#define regPCIEMSIX_VECT115_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT115_ADDR_HI 0x1a1cd +#define regPCIEMSIX_VECT115_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT115_MSG_DATA 0x1a1ce +#define regPCIEMSIX_VECT115_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT115_CONTROL 0x1a1cf +#define regPCIEMSIX_VECT115_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT116_ADDR_LO 0x1a1d0 +#define regPCIEMSIX_VECT116_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT116_ADDR_HI 0x1a1d1 +#define regPCIEMSIX_VECT116_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT116_MSG_DATA 0x1a1d2 +#define regPCIEMSIX_VECT116_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT116_CONTROL 0x1a1d3 +#define regPCIEMSIX_VECT116_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT117_ADDR_LO 0x1a1d4 +#define regPCIEMSIX_VECT117_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT117_ADDR_HI 0x1a1d5 +#define regPCIEMSIX_VECT117_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT117_MSG_DATA 0x1a1d6 +#define regPCIEMSIX_VECT117_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT117_CONTROL 0x1a1d7 +#define regPCIEMSIX_VECT117_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT118_ADDR_LO 0x1a1d8 +#define regPCIEMSIX_VECT118_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT118_ADDR_HI 0x1a1d9 +#define regPCIEMSIX_VECT118_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT118_MSG_DATA 0x1a1da +#define regPCIEMSIX_VECT118_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT118_CONTROL 0x1a1db +#define regPCIEMSIX_VECT118_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT119_ADDR_LO 0x1a1dc +#define regPCIEMSIX_VECT119_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT119_ADDR_HI 0x1a1dd +#define regPCIEMSIX_VECT119_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT119_MSG_DATA 0x1a1de +#define regPCIEMSIX_VECT119_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT119_CONTROL 0x1a1df +#define regPCIEMSIX_VECT119_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT120_ADDR_LO 0x1a1e0 +#define regPCIEMSIX_VECT120_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT120_ADDR_HI 0x1a1e1 +#define regPCIEMSIX_VECT120_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT120_MSG_DATA 0x1a1e2 +#define regPCIEMSIX_VECT120_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT120_CONTROL 0x1a1e3 +#define regPCIEMSIX_VECT120_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT121_ADDR_LO 0x1a1e4 +#define regPCIEMSIX_VECT121_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT121_ADDR_HI 0x1a1e5 +#define regPCIEMSIX_VECT121_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT121_MSG_DATA 0x1a1e6 +#define regPCIEMSIX_VECT121_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT121_CONTROL 0x1a1e7 +#define regPCIEMSIX_VECT121_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT122_ADDR_LO 0x1a1e8 +#define regPCIEMSIX_VECT122_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT122_ADDR_HI 0x1a1e9 +#define regPCIEMSIX_VECT122_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT122_MSG_DATA 0x1a1ea +#define regPCIEMSIX_VECT122_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT122_CONTROL 0x1a1eb +#define regPCIEMSIX_VECT122_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT123_ADDR_LO 0x1a1ec +#define regPCIEMSIX_VECT123_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT123_ADDR_HI 0x1a1ed +#define regPCIEMSIX_VECT123_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT123_MSG_DATA 0x1a1ee +#define regPCIEMSIX_VECT123_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT123_CONTROL 0x1a1ef +#define regPCIEMSIX_VECT123_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT124_ADDR_LO 0x1a1f0 +#define regPCIEMSIX_VECT124_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT124_ADDR_HI 0x1a1f1 +#define regPCIEMSIX_VECT124_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT124_MSG_DATA 0x1a1f2 +#define regPCIEMSIX_VECT124_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT124_CONTROL 0x1a1f3 +#define regPCIEMSIX_VECT124_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT125_ADDR_LO 0x1a1f4 +#define regPCIEMSIX_VECT125_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT125_ADDR_HI 0x1a1f5 +#define regPCIEMSIX_VECT125_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT125_MSG_DATA 0x1a1f6 +#define regPCIEMSIX_VECT125_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT125_CONTROL 0x1a1f7 +#define regPCIEMSIX_VECT125_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT126_ADDR_LO 0x1a1f8 +#define regPCIEMSIX_VECT126_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT126_ADDR_HI 0x1a1f9 +#define regPCIEMSIX_VECT126_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT126_MSG_DATA 0x1a1fa +#define regPCIEMSIX_VECT126_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT126_CONTROL 0x1a1fb +#define regPCIEMSIX_VECT126_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT127_ADDR_LO 0x1a1fc +#define regPCIEMSIX_VECT127_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT127_ADDR_HI 0x1a1fd +#define regPCIEMSIX_VECT127_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT127_MSG_DATA 0x1a1fe +#define regPCIEMSIX_VECT127_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT127_CONTROL 0x1a1ff +#define regPCIEMSIX_VECT127_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT128_ADDR_LO 0x1a200 +#define regPCIEMSIX_VECT128_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT128_ADDR_HI 0x1a201 +#define regPCIEMSIX_VECT128_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT128_MSG_DATA 0x1a202 +#define regPCIEMSIX_VECT128_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT128_CONTROL 0x1a203 +#define regPCIEMSIX_VECT128_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT129_ADDR_LO 0x1a204 +#define regPCIEMSIX_VECT129_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT129_ADDR_HI 0x1a205 +#define regPCIEMSIX_VECT129_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT129_MSG_DATA 0x1a206 +#define regPCIEMSIX_VECT129_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT129_CONTROL 0x1a207 +#define regPCIEMSIX_VECT129_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT130_ADDR_LO 0x1a208 +#define regPCIEMSIX_VECT130_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT130_ADDR_HI 0x1a209 +#define regPCIEMSIX_VECT130_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT130_MSG_DATA 0x1a20a +#define regPCIEMSIX_VECT130_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT130_CONTROL 0x1a20b +#define regPCIEMSIX_VECT130_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT131_ADDR_LO 0x1a20c +#define regPCIEMSIX_VECT131_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT131_ADDR_HI 0x1a20d +#define regPCIEMSIX_VECT131_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT131_MSG_DATA 0x1a20e +#define regPCIEMSIX_VECT131_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT131_CONTROL 0x1a20f +#define regPCIEMSIX_VECT131_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT132_ADDR_LO 0x1a210 +#define regPCIEMSIX_VECT132_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT132_ADDR_HI 0x1a211 +#define regPCIEMSIX_VECT132_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT132_MSG_DATA 0x1a212 +#define regPCIEMSIX_VECT132_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT132_CONTROL 0x1a213 +#define regPCIEMSIX_VECT132_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT133_ADDR_LO 0x1a214 +#define regPCIEMSIX_VECT133_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT133_ADDR_HI 0x1a215 +#define regPCIEMSIX_VECT133_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT133_MSG_DATA 0x1a216 +#define regPCIEMSIX_VECT133_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT133_CONTROL 0x1a217 +#define regPCIEMSIX_VECT133_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT134_ADDR_LO 0x1a218 +#define regPCIEMSIX_VECT134_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT134_ADDR_HI 0x1a219 +#define regPCIEMSIX_VECT134_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT134_MSG_DATA 0x1a21a +#define regPCIEMSIX_VECT134_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT134_CONTROL 0x1a21b +#define regPCIEMSIX_VECT134_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT135_ADDR_LO 0x1a21c +#define regPCIEMSIX_VECT135_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT135_ADDR_HI 0x1a21d +#define regPCIEMSIX_VECT135_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT135_MSG_DATA 0x1a21e +#define regPCIEMSIX_VECT135_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT135_CONTROL 0x1a21f +#define regPCIEMSIX_VECT135_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT136_ADDR_LO 0x1a220 +#define regPCIEMSIX_VECT136_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT136_ADDR_HI 0x1a221 +#define regPCIEMSIX_VECT136_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT136_MSG_DATA 0x1a222 +#define regPCIEMSIX_VECT136_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT136_CONTROL 0x1a223 +#define regPCIEMSIX_VECT136_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT137_ADDR_LO 0x1a224 +#define regPCIEMSIX_VECT137_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT137_ADDR_HI 0x1a225 +#define regPCIEMSIX_VECT137_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT137_MSG_DATA 0x1a226 +#define regPCIEMSIX_VECT137_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT137_CONTROL 0x1a227 +#define regPCIEMSIX_VECT137_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT138_ADDR_LO 0x1a228 +#define regPCIEMSIX_VECT138_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT138_ADDR_HI 0x1a229 +#define regPCIEMSIX_VECT138_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT138_MSG_DATA 0x1a22a +#define regPCIEMSIX_VECT138_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT138_CONTROL 0x1a22b +#define regPCIEMSIX_VECT138_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT139_ADDR_LO 0x1a22c +#define regPCIEMSIX_VECT139_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT139_ADDR_HI 0x1a22d +#define regPCIEMSIX_VECT139_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT139_MSG_DATA 0x1a22e +#define regPCIEMSIX_VECT139_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT139_CONTROL 0x1a22f +#define regPCIEMSIX_VECT139_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT140_ADDR_LO 0x1a230 +#define regPCIEMSIX_VECT140_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT140_ADDR_HI 0x1a231 +#define regPCIEMSIX_VECT140_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT140_MSG_DATA 0x1a232 +#define regPCIEMSIX_VECT140_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT140_CONTROL 0x1a233 +#define regPCIEMSIX_VECT140_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT141_ADDR_LO 0x1a234 +#define regPCIEMSIX_VECT141_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT141_ADDR_HI 0x1a235 +#define regPCIEMSIX_VECT141_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT141_MSG_DATA 0x1a236 +#define regPCIEMSIX_VECT141_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT141_CONTROL 0x1a237 +#define regPCIEMSIX_VECT141_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT142_ADDR_LO 0x1a238 +#define regPCIEMSIX_VECT142_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT142_ADDR_HI 0x1a239 +#define regPCIEMSIX_VECT142_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT142_MSG_DATA 0x1a23a +#define regPCIEMSIX_VECT142_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT142_CONTROL 0x1a23b +#define regPCIEMSIX_VECT142_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT143_ADDR_LO 0x1a23c +#define regPCIEMSIX_VECT143_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT143_ADDR_HI 0x1a23d +#define regPCIEMSIX_VECT143_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT143_MSG_DATA 0x1a23e +#define regPCIEMSIX_VECT143_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT143_CONTROL 0x1a23f +#define regPCIEMSIX_VECT143_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT144_ADDR_LO 0x1a240 +#define regPCIEMSIX_VECT144_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT144_ADDR_HI 0x1a241 +#define regPCIEMSIX_VECT144_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT144_MSG_DATA 0x1a242 +#define regPCIEMSIX_VECT144_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT144_CONTROL 0x1a243 +#define regPCIEMSIX_VECT144_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT145_ADDR_LO 0x1a244 +#define regPCIEMSIX_VECT145_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT145_ADDR_HI 0x1a245 +#define regPCIEMSIX_VECT145_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT145_MSG_DATA 0x1a246 +#define regPCIEMSIX_VECT145_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT145_CONTROL 0x1a247 +#define regPCIEMSIX_VECT145_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT146_ADDR_LO 0x1a248 +#define regPCIEMSIX_VECT146_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT146_ADDR_HI 0x1a249 +#define regPCIEMSIX_VECT146_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT146_MSG_DATA 0x1a24a +#define regPCIEMSIX_VECT146_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT146_CONTROL 0x1a24b +#define regPCIEMSIX_VECT146_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT147_ADDR_LO 0x1a24c +#define regPCIEMSIX_VECT147_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT147_ADDR_HI 0x1a24d +#define regPCIEMSIX_VECT147_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT147_MSG_DATA 0x1a24e +#define regPCIEMSIX_VECT147_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT147_CONTROL 0x1a24f +#define regPCIEMSIX_VECT147_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT148_ADDR_LO 0x1a250 +#define regPCIEMSIX_VECT148_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT148_ADDR_HI 0x1a251 +#define regPCIEMSIX_VECT148_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT148_MSG_DATA 0x1a252 +#define regPCIEMSIX_VECT148_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT148_CONTROL 0x1a253 +#define regPCIEMSIX_VECT148_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT149_ADDR_LO 0x1a254 +#define regPCIEMSIX_VECT149_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT149_ADDR_HI 0x1a255 +#define regPCIEMSIX_VECT149_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT149_MSG_DATA 0x1a256 +#define regPCIEMSIX_VECT149_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT149_CONTROL 0x1a257 +#define regPCIEMSIX_VECT149_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT150_ADDR_LO 0x1a258 +#define regPCIEMSIX_VECT150_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT150_ADDR_HI 0x1a259 +#define regPCIEMSIX_VECT150_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT150_MSG_DATA 0x1a25a +#define regPCIEMSIX_VECT150_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT150_CONTROL 0x1a25b +#define regPCIEMSIX_VECT150_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT151_ADDR_LO 0x1a25c +#define regPCIEMSIX_VECT151_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT151_ADDR_HI 0x1a25d +#define regPCIEMSIX_VECT151_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT151_MSG_DATA 0x1a25e +#define regPCIEMSIX_VECT151_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT151_CONTROL 0x1a25f +#define regPCIEMSIX_VECT151_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT152_ADDR_LO 0x1a260 +#define regPCIEMSIX_VECT152_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT152_ADDR_HI 0x1a261 +#define regPCIEMSIX_VECT152_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT152_MSG_DATA 0x1a262 +#define regPCIEMSIX_VECT152_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT152_CONTROL 0x1a263 +#define regPCIEMSIX_VECT152_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT153_ADDR_LO 0x1a264 +#define regPCIEMSIX_VECT153_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT153_ADDR_HI 0x1a265 +#define regPCIEMSIX_VECT153_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT153_MSG_DATA 0x1a266 +#define regPCIEMSIX_VECT153_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT153_CONTROL 0x1a267 +#define regPCIEMSIX_VECT153_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT154_ADDR_LO 0x1a268 +#define regPCIEMSIX_VECT154_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT154_ADDR_HI 0x1a269 +#define regPCIEMSIX_VECT154_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT154_MSG_DATA 0x1a26a +#define regPCIEMSIX_VECT154_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT154_CONTROL 0x1a26b +#define regPCIEMSIX_VECT154_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT155_ADDR_LO 0x1a26c +#define regPCIEMSIX_VECT155_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT155_ADDR_HI 0x1a26d +#define regPCIEMSIX_VECT155_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT155_MSG_DATA 0x1a26e +#define regPCIEMSIX_VECT155_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT155_CONTROL 0x1a26f +#define regPCIEMSIX_VECT155_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT156_ADDR_LO 0x1a270 +#define regPCIEMSIX_VECT156_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT156_ADDR_HI 0x1a271 +#define regPCIEMSIX_VECT156_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT156_MSG_DATA 0x1a272 +#define regPCIEMSIX_VECT156_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT156_CONTROL 0x1a273 +#define regPCIEMSIX_VECT156_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT157_ADDR_LO 0x1a274 +#define regPCIEMSIX_VECT157_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT157_ADDR_HI 0x1a275 +#define regPCIEMSIX_VECT157_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT157_MSG_DATA 0x1a276 +#define regPCIEMSIX_VECT157_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT157_CONTROL 0x1a277 +#define regPCIEMSIX_VECT157_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT158_ADDR_LO 0x1a278 +#define regPCIEMSIX_VECT158_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT158_ADDR_HI 0x1a279 +#define regPCIEMSIX_VECT158_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT158_MSG_DATA 0x1a27a +#define regPCIEMSIX_VECT158_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT158_CONTROL 0x1a27b +#define regPCIEMSIX_VECT158_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT159_ADDR_LO 0x1a27c +#define regPCIEMSIX_VECT159_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT159_ADDR_HI 0x1a27d +#define regPCIEMSIX_VECT159_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT159_MSG_DATA 0x1a27e +#define regPCIEMSIX_VECT159_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT159_CONTROL 0x1a27f +#define regPCIEMSIX_VECT159_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT160_ADDR_LO 0x1a280 +#define regPCIEMSIX_VECT160_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT160_ADDR_HI 0x1a281 +#define regPCIEMSIX_VECT160_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT160_MSG_DATA 0x1a282 +#define regPCIEMSIX_VECT160_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT160_CONTROL 0x1a283 +#define regPCIEMSIX_VECT160_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT161_ADDR_LO 0x1a284 +#define regPCIEMSIX_VECT161_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT161_ADDR_HI 0x1a285 +#define regPCIEMSIX_VECT161_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT161_MSG_DATA 0x1a286 +#define regPCIEMSIX_VECT161_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT161_CONTROL 0x1a287 +#define regPCIEMSIX_VECT161_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT162_ADDR_LO 0x1a288 +#define regPCIEMSIX_VECT162_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT162_ADDR_HI 0x1a289 +#define regPCIEMSIX_VECT162_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT162_MSG_DATA 0x1a28a +#define regPCIEMSIX_VECT162_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT162_CONTROL 0x1a28b +#define regPCIEMSIX_VECT162_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT163_ADDR_LO 0x1a28c +#define regPCIEMSIX_VECT163_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT163_ADDR_HI 0x1a28d +#define regPCIEMSIX_VECT163_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT163_MSG_DATA 0x1a28e +#define regPCIEMSIX_VECT163_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT163_CONTROL 0x1a28f +#define regPCIEMSIX_VECT163_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT164_ADDR_LO 0x1a290 +#define regPCIEMSIX_VECT164_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT164_ADDR_HI 0x1a291 +#define regPCIEMSIX_VECT164_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT164_MSG_DATA 0x1a292 +#define regPCIEMSIX_VECT164_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT164_CONTROL 0x1a293 +#define regPCIEMSIX_VECT164_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT165_ADDR_LO 0x1a294 +#define regPCIEMSIX_VECT165_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT165_ADDR_HI 0x1a295 +#define regPCIEMSIX_VECT165_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT165_MSG_DATA 0x1a296 +#define regPCIEMSIX_VECT165_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT165_CONTROL 0x1a297 +#define regPCIEMSIX_VECT165_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT166_ADDR_LO 0x1a298 +#define regPCIEMSIX_VECT166_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT166_ADDR_HI 0x1a299 +#define regPCIEMSIX_VECT166_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT166_MSG_DATA 0x1a29a +#define regPCIEMSIX_VECT166_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT166_CONTROL 0x1a29b +#define regPCIEMSIX_VECT166_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT167_ADDR_LO 0x1a29c +#define regPCIEMSIX_VECT167_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT167_ADDR_HI 0x1a29d +#define regPCIEMSIX_VECT167_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT167_MSG_DATA 0x1a29e +#define regPCIEMSIX_VECT167_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT167_CONTROL 0x1a29f +#define regPCIEMSIX_VECT167_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT168_ADDR_LO 0x1a2a0 +#define regPCIEMSIX_VECT168_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT168_ADDR_HI 0x1a2a1 +#define regPCIEMSIX_VECT168_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT168_MSG_DATA 0x1a2a2 +#define regPCIEMSIX_VECT168_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT168_CONTROL 0x1a2a3 +#define regPCIEMSIX_VECT168_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT169_ADDR_LO 0x1a2a4 +#define regPCIEMSIX_VECT169_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT169_ADDR_HI 0x1a2a5 +#define regPCIEMSIX_VECT169_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT169_MSG_DATA 0x1a2a6 +#define regPCIEMSIX_VECT169_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT169_CONTROL 0x1a2a7 +#define regPCIEMSIX_VECT169_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT170_ADDR_LO 0x1a2a8 +#define regPCIEMSIX_VECT170_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT170_ADDR_HI 0x1a2a9 +#define regPCIEMSIX_VECT170_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT170_MSG_DATA 0x1a2aa +#define regPCIEMSIX_VECT170_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT170_CONTROL 0x1a2ab +#define regPCIEMSIX_VECT170_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT171_ADDR_LO 0x1a2ac +#define regPCIEMSIX_VECT171_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT171_ADDR_HI 0x1a2ad +#define regPCIEMSIX_VECT171_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT171_MSG_DATA 0x1a2ae +#define regPCIEMSIX_VECT171_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT171_CONTROL 0x1a2af +#define regPCIEMSIX_VECT171_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT172_ADDR_LO 0x1a2b0 +#define regPCIEMSIX_VECT172_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT172_ADDR_HI 0x1a2b1 +#define regPCIEMSIX_VECT172_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT172_MSG_DATA 0x1a2b2 +#define regPCIEMSIX_VECT172_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT172_CONTROL 0x1a2b3 +#define regPCIEMSIX_VECT172_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT173_ADDR_LO 0x1a2b4 +#define regPCIEMSIX_VECT173_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT173_ADDR_HI 0x1a2b5 +#define regPCIEMSIX_VECT173_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT173_MSG_DATA 0x1a2b6 +#define regPCIEMSIX_VECT173_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT173_CONTROL 0x1a2b7 +#define regPCIEMSIX_VECT173_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT174_ADDR_LO 0x1a2b8 +#define regPCIEMSIX_VECT174_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT174_ADDR_HI 0x1a2b9 +#define regPCIEMSIX_VECT174_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT174_MSG_DATA 0x1a2ba +#define regPCIEMSIX_VECT174_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT174_CONTROL 0x1a2bb +#define regPCIEMSIX_VECT174_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT175_ADDR_LO 0x1a2bc +#define regPCIEMSIX_VECT175_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT175_ADDR_HI 0x1a2bd +#define regPCIEMSIX_VECT175_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT175_MSG_DATA 0x1a2be +#define regPCIEMSIX_VECT175_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT175_CONTROL 0x1a2bf +#define regPCIEMSIX_VECT175_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT176_ADDR_LO 0x1a2c0 +#define regPCIEMSIX_VECT176_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT176_ADDR_HI 0x1a2c1 +#define regPCIEMSIX_VECT176_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT176_MSG_DATA 0x1a2c2 +#define regPCIEMSIX_VECT176_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT176_CONTROL 0x1a2c3 +#define regPCIEMSIX_VECT176_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT177_ADDR_LO 0x1a2c4 +#define regPCIEMSIX_VECT177_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT177_ADDR_HI 0x1a2c5 +#define regPCIEMSIX_VECT177_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT177_MSG_DATA 0x1a2c6 +#define regPCIEMSIX_VECT177_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT177_CONTROL 0x1a2c7 +#define regPCIEMSIX_VECT177_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT178_ADDR_LO 0x1a2c8 +#define regPCIEMSIX_VECT178_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT178_ADDR_HI 0x1a2c9 +#define regPCIEMSIX_VECT178_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT178_MSG_DATA 0x1a2ca +#define regPCIEMSIX_VECT178_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT178_CONTROL 0x1a2cb +#define regPCIEMSIX_VECT178_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT179_ADDR_LO 0x1a2cc +#define regPCIEMSIX_VECT179_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT179_ADDR_HI 0x1a2cd +#define regPCIEMSIX_VECT179_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT179_MSG_DATA 0x1a2ce +#define regPCIEMSIX_VECT179_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT179_CONTROL 0x1a2cf +#define regPCIEMSIX_VECT179_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT180_ADDR_LO 0x1a2d0 +#define regPCIEMSIX_VECT180_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT180_ADDR_HI 0x1a2d1 +#define regPCIEMSIX_VECT180_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT180_MSG_DATA 0x1a2d2 +#define regPCIEMSIX_VECT180_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT180_CONTROL 0x1a2d3 +#define regPCIEMSIX_VECT180_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT181_ADDR_LO 0x1a2d4 +#define regPCIEMSIX_VECT181_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT181_ADDR_HI 0x1a2d5 +#define regPCIEMSIX_VECT181_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT181_MSG_DATA 0x1a2d6 +#define regPCIEMSIX_VECT181_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT181_CONTROL 0x1a2d7 +#define regPCIEMSIX_VECT181_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT182_ADDR_LO 0x1a2d8 +#define regPCIEMSIX_VECT182_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT182_ADDR_HI 0x1a2d9 +#define regPCIEMSIX_VECT182_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT182_MSG_DATA 0x1a2da +#define regPCIEMSIX_VECT182_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT182_CONTROL 0x1a2db +#define regPCIEMSIX_VECT182_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT183_ADDR_LO 0x1a2dc +#define regPCIEMSIX_VECT183_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT183_ADDR_HI 0x1a2dd +#define regPCIEMSIX_VECT183_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT183_MSG_DATA 0x1a2de +#define regPCIEMSIX_VECT183_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT183_CONTROL 0x1a2df +#define regPCIEMSIX_VECT183_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT184_ADDR_LO 0x1a2e0 +#define regPCIEMSIX_VECT184_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT184_ADDR_HI 0x1a2e1 +#define regPCIEMSIX_VECT184_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT184_MSG_DATA 0x1a2e2 +#define regPCIEMSIX_VECT184_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT184_CONTROL 0x1a2e3 +#define regPCIEMSIX_VECT184_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT185_ADDR_LO 0x1a2e4 +#define regPCIEMSIX_VECT185_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT185_ADDR_HI 0x1a2e5 +#define regPCIEMSIX_VECT185_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT185_MSG_DATA 0x1a2e6 +#define regPCIEMSIX_VECT185_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT185_CONTROL 0x1a2e7 +#define regPCIEMSIX_VECT185_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT186_ADDR_LO 0x1a2e8 +#define regPCIEMSIX_VECT186_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT186_ADDR_HI 0x1a2e9 +#define regPCIEMSIX_VECT186_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT186_MSG_DATA 0x1a2ea +#define regPCIEMSIX_VECT186_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT186_CONTROL 0x1a2eb +#define regPCIEMSIX_VECT186_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT187_ADDR_LO 0x1a2ec +#define regPCIEMSIX_VECT187_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT187_ADDR_HI 0x1a2ed +#define regPCIEMSIX_VECT187_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT187_MSG_DATA 0x1a2ee +#define regPCIEMSIX_VECT187_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT187_CONTROL 0x1a2ef +#define regPCIEMSIX_VECT187_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT188_ADDR_LO 0x1a2f0 +#define regPCIEMSIX_VECT188_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT188_ADDR_HI 0x1a2f1 +#define regPCIEMSIX_VECT188_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT188_MSG_DATA 0x1a2f2 +#define regPCIEMSIX_VECT188_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT188_CONTROL 0x1a2f3 +#define regPCIEMSIX_VECT188_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT189_ADDR_LO 0x1a2f4 +#define regPCIEMSIX_VECT189_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT189_ADDR_HI 0x1a2f5 +#define regPCIEMSIX_VECT189_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT189_MSG_DATA 0x1a2f6 +#define regPCIEMSIX_VECT189_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT189_CONTROL 0x1a2f7 +#define regPCIEMSIX_VECT189_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT190_ADDR_LO 0x1a2f8 +#define regPCIEMSIX_VECT190_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT190_ADDR_HI 0x1a2f9 +#define regPCIEMSIX_VECT190_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT190_MSG_DATA 0x1a2fa +#define regPCIEMSIX_VECT190_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT190_CONTROL 0x1a2fb +#define regPCIEMSIX_VECT190_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT191_ADDR_LO 0x1a2fc +#define regPCIEMSIX_VECT191_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT191_ADDR_HI 0x1a2fd +#define regPCIEMSIX_VECT191_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT191_MSG_DATA 0x1a2fe +#define regPCIEMSIX_VECT191_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT191_CONTROL 0x1a2ff +#define regPCIEMSIX_VECT191_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT192_ADDR_LO 0x1a300 +#define regPCIEMSIX_VECT192_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT192_ADDR_HI 0x1a301 +#define regPCIEMSIX_VECT192_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT192_MSG_DATA 0x1a302 +#define regPCIEMSIX_VECT192_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT192_CONTROL 0x1a303 +#define regPCIEMSIX_VECT192_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT193_ADDR_LO 0x1a304 +#define regPCIEMSIX_VECT193_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT193_ADDR_HI 0x1a305 +#define regPCIEMSIX_VECT193_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT193_MSG_DATA 0x1a306 +#define regPCIEMSIX_VECT193_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT193_CONTROL 0x1a307 +#define regPCIEMSIX_VECT193_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT194_ADDR_LO 0x1a308 +#define regPCIEMSIX_VECT194_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT194_ADDR_HI 0x1a309 +#define regPCIEMSIX_VECT194_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT194_MSG_DATA 0x1a30a +#define regPCIEMSIX_VECT194_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT194_CONTROL 0x1a30b +#define regPCIEMSIX_VECT194_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT195_ADDR_LO 0x1a30c +#define regPCIEMSIX_VECT195_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT195_ADDR_HI 0x1a30d +#define regPCIEMSIX_VECT195_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT195_MSG_DATA 0x1a30e +#define regPCIEMSIX_VECT195_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT195_CONTROL 0x1a30f +#define regPCIEMSIX_VECT195_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT196_ADDR_LO 0x1a310 +#define regPCIEMSIX_VECT196_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT196_ADDR_HI 0x1a311 +#define regPCIEMSIX_VECT196_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT196_MSG_DATA 0x1a312 +#define regPCIEMSIX_VECT196_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT196_CONTROL 0x1a313 +#define regPCIEMSIX_VECT196_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT197_ADDR_LO 0x1a314 +#define regPCIEMSIX_VECT197_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT197_ADDR_HI 0x1a315 +#define regPCIEMSIX_VECT197_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT197_MSG_DATA 0x1a316 +#define regPCIEMSIX_VECT197_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT197_CONTROL 0x1a317 +#define regPCIEMSIX_VECT197_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT198_ADDR_LO 0x1a318 +#define regPCIEMSIX_VECT198_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT198_ADDR_HI 0x1a319 +#define regPCIEMSIX_VECT198_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT198_MSG_DATA 0x1a31a +#define regPCIEMSIX_VECT198_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT198_CONTROL 0x1a31b +#define regPCIEMSIX_VECT198_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT199_ADDR_LO 0x1a31c +#define regPCIEMSIX_VECT199_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT199_ADDR_HI 0x1a31d +#define regPCIEMSIX_VECT199_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT199_MSG_DATA 0x1a31e +#define regPCIEMSIX_VECT199_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT199_CONTROL 0x1a31f +#define regPCIEMSIX_VECT199_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT200_ADDR_LO 0x1a320 +#define regPCIEMSIX_VECT200_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT200_ADDR_HI 0x1a321 +#define regPCIEMSIX_VECT200_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT200_MSG_DATA 0x1a322 +#define regPCIEMSIX_VECT200_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT200_CONTROL 0x1a323 +#define regPCIEMSIX_VECT200_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT201_ADDR_LO 0x1a324 +#define regPCIEMSIX_VECT201_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT201_ADDR_HI 0x1a325 +#define regPCIEMSIX_VECT201_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT201_MSG_DATA 0x1a326 +#define regPCIEMSIX_VECT201_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT201_CONTROL 0x1a327 +#define regPCIEMSIX_VECT201_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT202_ADDR_LO 0x1a328 +#define regPCIEMSIX_VECT202_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT202_ADDR_HI 0x1a329 +#define regPCIEMSIX_VECT202_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT202_MSG_DATA 0x1a32a +#define regPCIEMSIX_VECT202_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT202_CONTROL 0x1a32b +#define regPCIEMSIX_VECT202_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT203_ADDR_LO 0x1a32c +#define regPCIEMSIX_VECT203_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT203_ADDR_HI 0x1a32d +#define regPCIEMSIX_VECT203_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT203_MSG_DATA 0x1a32e +#define regPCIEMSIX_VECT203_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT203_CONTROL 0x1a32f +#define regPCIEMSIX_VECT203_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT204_ADDR_LO 0x1a330 +#define regPCIEMSIX_VECT204_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT204_ADDR_HI 0x1a331 +#define regPCIEMSIX_VECT204_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT204_MSG_DATA 0x1a332 +#define regPCIEMSIX_VECT204_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT204_CONTROL 0x1a333 +#define regPCIEMSIX_VECT204_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT205_ADDR_LO 0x1a334 +#define regPCIEMSIX_VECT205_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT205_ADDR_HI 0x1a335 +#define regPCIEMSIX_VECT205_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT205_MSG_DATA 0x1a336 +#define regPCIEMSIX_VECT205_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT205_CONTROL 0x1a337 +#define regPCIEMSIX_VECT205_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT206_ADDR_LO 0x1a338 +#define regPCIEMSIX_VECT206_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT206_ADDR_HI 0x1a339 +#define regPCIEMSIX_VECT206_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT206_MSG_DATA 0x1a33a +#define regPCIEMSIX_VECT206_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT206_CONTROL 0x1a33b +#define regPCIEMSIX_VECT206_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT207_ADDR_LO 0x1a33c +#define regPCIEMSIX_VECT207_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT207_ADDR_HI 0x1a33d +#define regPCIEMSIX_VECT207_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT207_MSG_DATA 0x1a33e +#define regPCIEMSIX_VECT207_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT207_CONTROL 0x1a33f +#define regPCIEMSIX_VECT207_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT208_ADDR_LO 0x1a340 +#define regPCIEMSIX_VECT208_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT208_ADDR_HI 0x1a341 +#define regPCIEMSIX_VECT208_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT208_MSG_DATA 0x1a342 +#define regPCIEMSIX_VECT208_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT208_CONTROL 0x1a343 +#define regPCIEMSIX_VECT208_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT209_ADDR_LO 0x1a344 +#define regPCIEMSIX_VECT209_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT209_ADDR_HI 0x1a345 +#define regPCIEMSIX_VECT209_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT209_MSG_DATA 0x1a346 +#define regPCIEMSIX_VECT209_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT209_CONTROL 0x1a347 +#define regPCIEMSIX_VECT209_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT210_ADDR_LO 0x1a348 +#define regPCIEMSIX_VECT210_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT210_ADDR_HI 0x1a349 +#define regPCIEMSIX_VECT210_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT210_MSG_DATA 0x1a34a +#define regPCIEMSIX_VECT210_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT210_CONTROL 0x1a34b +#define regPCIEMSIX_VECT210_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT211_ADDR_LO 0x1a34c +#define regPCIEMSIX_VECT211_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT211_ADDR_HI 0x1a34d +#define regPCIEMSIX_VECT211_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT211_MSG_DATA 0x1a34e +#define regPCIEMSIX_VECT211_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT211_CONTROL 0x1a34f +#define regPCIEMSIX_VECT211_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT212_ADDR_LO 0x1a350 +#define regPCIEMSIX_VECT212_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT212_ADDR_HI 0x1a351 +#define regPCIEMSIX_VECT212_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT212_MSG_DATA 0x1a352 +#define regPCIEMSIX_VECT212_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT212_CONTROL 0x1a353 +#define regPCIEMSIX_VECT212_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT213_ADDR_LO 0x1a354 +#define regPCIEMSIX_VECT213_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT213_ADDR_HI 0x1a355 +#define regPCIEMSIX_VECT213_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT213_MSG_DATA 0x1a356 +#define regPCIEMSIX_VECT213_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT213_CONTROL 0x1a357 +#define regPCIEMSIX_VECT213_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT214_ADDR_LO 0x1a358 +#define regPCIEMSIX_VECT214_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT214_ADDR_HI 0x1a359 +#define regPCIEMSIX_VECT214_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT214_MSG_DATA 0x1a35a +#define regPCIEMSIX_VECT214_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT214_CONTROL 0x1a35b +#define regPCIEMSIX_VECT214_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT215_ADDR_LO 0x1a35c +#define regPCIEMSIX_VECT215_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT215_ADDR_HI 0x1a35d +#define regPCIEMSIX_VECT215_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT215_MSG_DATA 0x1a35e +#define regPCIEMSIX_VECT215_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT215_CONTROL 0x1a35f +#define regPCIEMSIX_VECT215_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT216_ADDR_LO 0x1a360 +#define regPCIEMSIX_VECT216_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT216_ADDR_HI 0x1a361 +#define regPCIEMSIX_VECT216_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT216_MSG_DATA 0x1a362 +#define regPCIEMSIX_VECT216_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT216_CONTROL 0x1a363 +#define regPCIEMSIX_VECT216_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT217_ADDR_LO 0x1a364 +#define regPCIEMSIX_VECT217_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT217_ADDR_HI 0x1a365 +#define regPCIEMSIX_VECT217_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT217_MSG_DATA 0x1a366 +#define regPCIEMSIX_VECT217_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT217_CONTROL 0x1a367 +#define regPCIEMSIX_VECT217_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT218_ADDR_LO 0x1a368 +#define regPCIEMSIX_VECT218_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT218_ADDR_HI 0x1a369 +#define regPCIEMSIX_VECT218_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT218_MSG_DATA 0x1a36a +#define regPCIEMSIX_VECT218_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT218_CONTROL 0x1a36b +#define regPCIEMSIX_VECT218_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT219_ADDR_LO 0x1a36c +#define regPCIEMSIX_VECT219_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT219_ADDR_HI 0x1a36d +#define regPCIEMSIX_VECT219_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT219_MSG_DATA 0x1a36e +#define regPCIEMSIX_VECT219_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT219_CONTROL 0x1a36f +#define regPCIEMSIX_VECT219_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT220_ADDR_LO 0x1a370 +#define regPCIEMSIX_VECT220_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT220_ADDR_HI 0x1a371 +#define regPCIEMSIX_VECT220_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT220_MSG_DATA 0x1a372 +#define regPCIEMSIX_VECT220_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT220_CONTROL 0x1a373 +#define regPCIEMSIX_VECT220_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT221_ADDR_LO 0x1a374 +#define regPCIEMSIX_VECT221_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT221_ADDR_HI 0x1a375 +#define regPCIEMSIX_VECT221_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT221_MSG_DATA 0x1a376 +#define regPCIEMSIX_VECT221_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT221_CONTROL 0x1a377 +#define regPCIEMSIX_VECT221_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT222_ADDR_LO 0x1a378 +#define regPCIEMSIX_VECT222_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT222_ADDR_HI 0x1a379 +#define regPCIEMSIX_VECT222_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT222_MSG_DATA 0x1a37a +#define regPCIEMSIX_VECT222_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT222_CONTROL 0x1a37b +#define regPCIEMSIX_VECT222_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT223_ADDR_LO 0x1a37c +#define regPCIEMSIX_VECT223_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT223_ADDR_HI 0x1a37d +#define regPCIEMSIX_VECT223_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT223_MSG_DATA 0x1a37e +#define regPCIEMSIX_VECT223_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT223_CONTROL 0x1a37f +#define regPCIEMSIX_VECT223_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT224_ADDR_LO 0x1a380 +#define regPCIEMSIX_VECT224_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT224_ADDR_HI 0x1a381 +#define regPCIEMSIX_VECT224_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT224_MSG_DATA 0x1a382 +#define regPCIEMSIX_VECT224_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT224_CONTROL 0x1a383 +#define regPCIEMSIX_VECT224_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT225_ADDR_LO 0x1a384 +#define regPCIEMSIX_VECT225_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT225_ADDR_HI 0x1a385 +#define regPCIEMSIX_VECT225_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT225_MSG_DATA 0x1a386 +#define regPCIEMSIX_VECT225_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT225_CONTROL 0x1a387 +#define regPCIEMSIX_VECT225_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT226_ADDR_LO 0x1a388 +#define regPCIEMSIX_VECT226_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT226_ADDR_HI 0x1a389 +#define regPCIEMSIX_VECT226_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT226_MSG_DATA 0x1a38a +#define regPCIEMSIX_VECT226_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT226_CONTROL 0x1a38b +#define regPCIEMSIX_VECT226_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT227_ADDR_LO 0x1a38c +#define regPCIEMSIX_VECT227_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT227_ADDR_HI 0x1a38d +#define regPCIEMSIX_VECT227_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT227_MSG_DATA 0x1a38e +#define regPCIEMSIX_VECT227_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT227_CONTROL 0x1a38f +#define regPCIEMSIX_VECT227_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT228_ADDR_LO 0x1a390 +#define regPCIEMSIX_VECT228_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT228_ADDR_HI 0x1a391 +#define regPCIEMSIX_VECT228_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT228_MSG_DATA 0x1a392 +#define regPCIEMSIX_VECT228_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT228_CONTROL 0x1a393 +#define regPCIEMSIX_VECT228_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT229_ADDR_LO 0x1a394 +#define regPCIEMSIX_VECT229_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT229_ADDR_HI 0x1a395 +#define regPCIEMSIX_VECT229_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT229_MSG_DATA 0x1a396 +#define regPCIEMSIX_VECT229_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT229_CONTROL 0x1a397 +#define regPCIEMSIX_VECT229_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT230_ADDR_LO 0x1a398 +#define regPCIEMSIX_VECT230_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT230_ADDR_HI 0x1a399 +#define regPCIEMSIX_VECT230_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT230_MSG_DATA 0x1a39a +#define regPCIEMSIX_VECT230_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT230_CONTROL 0x1a39b +#define regPCIEMSIX_VECT230_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT231_ADDR_LO 0x1a39c +#define regPCIEMSIX_VECT231_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT231_ADDR_HI 0x1a39d +#define regPCIEMSIX_VECT231_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT231_MSG_DATA 0x1a39e +#define regPCIEMSIX_VECT231_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT231_CONTROL 0x1a39f +#define regPCIEMSIX_VECT231_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT232_ADDR_LO 0x1a3a0 +#define regPCIEMSIX_VECT232_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT232_ADDR_HI 0x1a3a1 +#define regPCIEMSIX_VECT232_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT232_MSG_DATA 0x1a3a2 +#define regPCIEMSIX_VECT232_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT232_CONTROL 0x1a3a3 +#define regPCIEMSIX_VECT232_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT233_ADDR_LO 0x1a3a4 +#define regPCIEMSIX_VECT233_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT233_ADDR_HI 0x1a3a5 +#define regPCIEMSIX_VECT233_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT233_MSG_DATA 0x1a3a6 +#define regPCIEMSIX_VECT233_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT233_CONTROL 0x1a3a7 +#define regPCIEMSIX_VECT233_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT234_ADDR_LO 0x1a3a8 +#define regPCIEMSIX_VECT234_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT234_ADDR_HI 0x1a3a9 +#define regPCIEMSIX_VECT234_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT234_MSG_DATA 0x1a3aa +#define regPCIEMSIX_VECT234_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT234_CONTROL 0x1a3ab +#define regPCIEMSIX_VECT234_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT235_ADDR_LO 0x1a3ac +#define regPCIEMSIX_VECT235_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT235_ADDR_HI 0x1a3ad +#define regPCIEMSIX_VECT235_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT235_MSG_DATA 0x1a3ae +#define regPCIEMSIX_VECT235_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT235_CONTROL 0x1a3af +#define regPCIEMSIX_VECT235_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT236_ADDR_LO 0x1a3b0 +#define regPCIEMSIX_VECT236_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT236_ADDR_HI 0x1a3b1 +#define regPCIEMSIX_VECT236_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT236_MSG_DATA 0x1a3b2 +#define regPCIEMSIX_VECT236_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT236_CONTROL 0x1a3b3 +#define regPCIEMSIX_VECT236_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT237_ADDR_LO 0x1a3b4 +#define regPCIEMSIX_VECT237_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT237_ADDR_HI 0x1a3b5 +#define regPCIEMSIX_VECT237_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT237_MSG_DATA 0x1a3b6 +#define regPCIEMSIX_VECT237_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT237_CONTROL 0x1a3b7 +#define regPCIEMSIX_VECT237_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT238_ADDR_LO 0x1a3b8 +#define regPCIEMSIX_VECT238_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT238_ADDR_HI 0x1a3b9 +#define regPCIEMSIX_VECT238_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT238_MSG_DATA 0x1a3ba +#define regPCIEMSIX_VECT238_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT238_CONTROL 0x1a3bb +#define regPCIEMSIX_VECT238_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT239_ADDR_LO 0x1a3bc +#define regPCIEMSIX_VECT239_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT239_ADDR_HI 0x1a3bd +#define regPCIEMSIX_VECT239_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT239_MSG_DATA 0x1a3be +#define regPCIEMSIX_VECT239_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT239_CONTROL 0x1a3bf +#define regPCIEMSIX_VECT239_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT240_ADDR_LO 0x1a3c0 +#define regPCIEMSIX_VECT240_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT240_ADDR_HI 0x1a3c1 +#define regPCIEMSIX_VECT240_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT240_MSG_DATA 0x1a3c2 +#define regPCIEMSIX_VECT240_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT240_CONTROL 0x1a3c3 +#define regPCIEMSIX_VECT240_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT241_ADDR_LO 0x1a3c4 +#define regPCIEMSIX_VECT241_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT241_ADDR_HI 0x1a3c5 +#define regPCIEMSIX_VECT241_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT241_MSG_DATA 0x1a3c6 +#define regPCIEMSIX_VECT241_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT241_CONTROL 0x1a3c7 +#define regPCIEMSIX_VECT241_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT242_ADDR_LO 0x1a3c8 +#define regPCIEMSIX_VECT242_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT242_ADDR_HI 0x1a3c9 +#define regPCIEMSIX_VECT242_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT242_MSG_DATA 0x1a3ca +#define regPCIEMSIX_VECT242_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT242_CONTROL 0x1a3cb +#define regPCIEMSIX_VECT242_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT243_ADDR_LO 0x1a3cc +#define regPCIEMSIX_VECT243_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT243_ADDR_HI 0x1a3cd +#define regPCIEMSIX_VECT243_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT243_MSG_DATA 0x1a3ce +#define regPCIEMSIX_VECT243_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT243_CONTROL 0x1a3cf +#define regPCIEMSIX_VECT243_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT244_ADDR_LO 0x1a3d0 +#define regPCIEMSIX_VECT244_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT244_ADDR_HI 0x1a3d1 +#define regPCIEMSIX_VECT244_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT244_MSG_DATA 0x1a3d2 +#define regPCIEMSIX_VECT244_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT244_CONTROL 0x1a3d3 +#define regPCIEMSIX_VECT244_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT245_ADDR_LO 0x1a3d4 +#define regPCIEMSIX_VECT245_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT245_ADDR_HI 0x1a3d5 +#define regPCIEMSIX_VECT245_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT245_MSG_DATA 0x1a3d6 +#define regPCIEMSIX_VECT245_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT245_CONTROL 0x1a3d7 +#define regPCIEMSIX_VECT245_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT246_ADDR_LO 0x1a3d8 +#define regPCIEMSIX_VECT246_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT246_ADDR_HI 0x1a3d9 +#define regPCIEMSIX_VECT246_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT246_MSG_DATA 0x1a3da +#define regPCIEMSIX_VECT246_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT246_CONTROL 0x1a3db +#define regPCIEMSIX_VECT246_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT247_ADDR_LO 0x1a3dc +#define regPCIEMSIX_VECT247_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT247_ADDR_HI 0x1a3dd +#define regPCIEMSIX_VECT247_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT247_MSG_DATA 0x1a3de +#define regPCIEMSIX_VECT247_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT247_CONTROL 0x1a3df +#define regPCIEMSIX_VECT247_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT248_ADDR_LO 0x1a3e0 +#define regPCIEMSIX_VECT248_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT248_ADDR_HI 0x1a3e1 +#define regPCIEMSIX_VECT248_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT248_MSG_DATA 0x1a3e2 +#define regPCIEMSIX_VECT248_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT248_CONTROL 0x1a3e3 +#define regPCIEMSIX_VECT248_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT249_ADDR_LO 0x1a3e4 +#define regPCIEMSIX_VECT249_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT249_ADDR_HI 0x1a3e5 +#define regPCIEMSIX_VECT249_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT249_MSG_DATA 0x1a3e6 +#define regPCIEMSIX_VECT249_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT249_CONTROL 0x1a3e7 +#define regPCIEMSIX_VECT249_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT250_ADDR_LO 0x1a3e8 +#define regPCIEMSIX_VECT250_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT250_ADDR_HI 0x1a3e9 +#define regPCIEMSIX_VECT250_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT250_MSG_DATA 0x1a3ea +#define regPCIEMSIX_VECT250_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT250_CONTROL 0x1a3eb +#define regPCIEMSIX_VECT250_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT251_ADDR_LO 0x1a3ec +#define regPCIEMSIX_VECT251_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT251_ADDR_HI 0x1a3ed +#define regPCIEMSIX_VECT251_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT251_MSG_DATA 0x1a3ee +#define regPCIEMSIX_VECT251_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT251_CONTROL 0x1a3ef +#define regPCIEMSIX_VECT251_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT252_ADDR_LO 0x1a3f0 +#define regPCIEMSIX_VECT252_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT252_ADDR_HI 0x1a3f1 +#define regPCIEMSIX_VECT252_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT252_MSG_DATA 0x1a3f2 +#define regPCIEMSIX_VECT252_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT252_CONTROL 0x1a3f3 +#define regPCIEMSIX_VECT252_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT253_ADDR_LO 0x1a3f4 +#define regPCIEMSIX_VECT253_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT253_ADDR_HI 0x1a3f5 +#define regPCIEMSIX_VECT253_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT253_MSG_DATA 0x1a3f6 +#define regPCIEMSIX_VECT253_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT253_CONTROL 0x1a3f7 +#define regPCIEMSIX_VECT253_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT254_ADDR_LO 0x1a3f8 +#define regPCIEMSIX_VECT254_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT254_ADDR_HI 0x1a3f9 +#define regPCIEMSIX_VECT254_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT254_MSG_DATA 0x1a3fa +#define regPCIEMSIX_VECT254_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT254_CONTROL 0x1a3fb +#define regPCIEMSIX_VECT254_CONTROL_BASE_IDX 8 +#define regPCIEMSIX_VECT255_ADDR_LO 0x1a3fc +#define regPCIEMSIX_VECT255_ADDR_LO_BASE_IDX 8 +#define regPCIEMSIX_VECT255_ADDR_HI 0x1a3fd +#define regPCIEMSIX_VECT255_ADDR_HI_BASE_IDX 8 +#define regPCIEMSIX_VECT255_MSG_DATA 0x1a3fe +#define regPCIEMSIX_VECT255_MSG_DATA_BASE_IDX 8 +#define regPCIEMSIX_VECT255_CONTROL 0x1a3ff +#define regPCIEMSIX_VECT255_CONTROL_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_pciemsix_0_usb_MSIXPDEC +// base address: 0x10169000 +#define regPCIEMSIX_PBA_0 0x1a400 +#define regPCIEMSIX_PBA_0_BASE_IDX 8 +#define regPCIEMSIX_PBA_1 0x1a401 +#define regPCIEMSIX_PBA_1_BASE_IDX 8 +#define regPCIEMSIX_PBA_2 0x1a402 +#define regPCIEMSIX_PBA_2_BASE_IDX 8 +#define regPCIEMSIX_PBA_3 0x1a403 +#define regPCIEMSIX_PBA_3_BASE_IDX 8 +#define regPCIEMSIX_PBA_4 0x1a404 +#define regPCIEMSIX_PBA_4_BASE_IDX 8 +#define regPCIEMSIX_PBA_5 0x1a405 +#define regPCIEMSIX_PBA_5_BASE_IDX 8 +#define regPCIEMSIX_PBA_6 0x1a406 +#define regPCIEMSIX_PBA_6_BASE_IDX 8 +#define regPCIEMSIX_PBA_7 0x1a407 +#define regPCIEMSIX_PBA_7_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_swus_SUMDEC +// base address: 0x1013b000 +#define regSUM_INDEX 0xec38 +#define regSUM_INDEX_BASE_IDX 8 +#define regSUM_DATA 0xec39 +#define regSUM_DATA_BASE_IDX 8 +#define regSUM_INDEX_HI 0xec3b +#define regSUM_INDEX_HI_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_strap_rcc_strap_internal +// base address: 0x10100000 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0 0xc400 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1 0xc401 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2 0xc402 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3 0xc403 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4 0xc404 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5 0xc405 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6 0xc406 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7 0xc407 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8 0xc408 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9 0xc409 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP10 0xc40a +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP10_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP11 0xc40b +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP11_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP12 0xc40c +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP12_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP13 0xc40d +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP13_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP14 0xc40e +#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP14_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP0 0xc480 +#define regRCC_DEV1_PORT_STRAP0_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP1 0xc481 +#define regRCC_DEV1_PORT_STRAP1_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP2 0xc482 +#define regRCC_DEV1_PORT_STRAP2_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP3 0xc483 +#define regRCC_DEV1_PORT_STRAP3_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP4 0xc484 +#define regRCC_DEV1_PORT_STRAP4_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP5 0xc485 +#define regRCC_DEV1_PORT_STRAP5_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP6 0xc486 +#define regRCC_DEV1_PORT_STRAP6_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP7 0xc487 +#define regRCC_DEV1_PORT_STRAP7_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP8 0xc488 +#define regRCC_DEV1_PORT_STRAP8_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP9 0xc489 +#define regRCC_DEV1_PORT_STRAP9_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP10 0xc48a +#define regRCC_DEV1_PORT_STRAP10_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP11 0xc48b +#define regRCC_DEV1_PORT_STRAP11_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP12 0xc48c +#define regRCC_DEV1_PORT_STRAP12_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP13 0xc48d +#define regRCC_DEV1_PORT_STRAP13_BASE_IDX 8 +#define regRCC_DEV1_PORT_STRAP14 0xc48e +#define regRCC_DEV1_PORT_STRAP14_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP0 0xc500 +#define regRCC_DEV2_PORT_STRAP0_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP1 0xc501 +#define regRCC_DEV2_PORT_STRAP1_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP2 0xc502 +#define regRCC_DEV2_PORT_STRAP2_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP3 0xc503 +#define regRCC_DEV2_PORT_STRAP3_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP4 0xc504 +#define regRCC_DEV2_PORT_STRAP4_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP5 0xc505 +#define regRCC_DEV2_PORT_STRAP5_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP6 0xc506 +#define regRCC_DEV2_PORT_STRAP6_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP7 0xc507 +#define regRCC_DEV2_PORT_STRAP7_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP8 0xc508 +#define regRCC_DEV2_PORT_STRAP8_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP9 0xc509 +#define regRCC_DEV2_PORT_STRAP9_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP10 0xc50a +#define regRCC_DEV2_PORT_STRAP10_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP11 0xc50b +#define regRCC_DEV2_PORT_STRAP11_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP12 0xc50c +#define regRCC_DEV2_PORT_STRAP12_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP13 0xc50d +#define regRCC_DEV2_PORT_STRAP13_BASE_IDX 8 +#define regRCC_DEV2_PORT_STRAP14 0xc50e +#define regRCC_DEV2_PORT_STRAP14_BASE_IDX 8 +#define regRCC_STRAP1_RCC_BIF_STRAP0 0xc600 +#define regRCC_STRAP1_RCC_BIF_STRAP0_BASE_IDX 8 +#define regRCC_STRAP1_RCC_BIF_STRAP1 0xc601 +#define regRCC_STRAP1_RCC_BIF_STRAP1_BASE_IDX 8 +#define regRCC_STRAP1_RCC_BIF_STRAP2 0xc602 +#define regRCC_STRAP1_RCC_BIF_STRAP2_BASE_IDX 8 +#define regRCC_STRAP1_RCC_BIF_STRAP3 0xc603 +#define regRCC_STRAP1_RCC_BIF_STRAP3_BASE_IDX 8 +#define regRCC_STRAP1_RCC_BIF_STRAP4 0xc604 +#define regRCC_STRAP1_RCC_BIF_STRAP4_BASE_IDX 8 +#define regRCC_STRAP1_RCC_BIF_STRAP5 0xc605 +#define regRCC_STRAP1_RCC_BIF_STRAP5_BASE_IDX 8 +#define regRCC_STRAP1_RCC_BIF_STRAP6 0xc606 +#define regRCC_STRAP1_RCC_BIF_STRAP6_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0 0xd000 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1 0xd001 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2 0xd002 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3 0xd003 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4 0xd004 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5 0xd005 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8 0xd008 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9 0xd009 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13 0xd00d +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14 0xd00e +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15 0xd00f +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16 0xd010 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17 0xd011 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18 0xd012 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP26 0xd01a +#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP26_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0 0xd080 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2 0xd082 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3 0xd083 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4 0xd084 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5 0xd085 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6 0xd086 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7 0xd087 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20 0xd094 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21 0xd095 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP22 0xd096 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP22_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23 0xd097 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24 0xd098 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24_BASE_IDX 8 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP25 0xd099 +#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP25_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP0 0xd100 +#define regRCC_DEV0_EPF2_STRAP0_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP2 0xd102 +#define regRCC_DEV0_EPF2_STRAP2_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP3 0xd103 +#define regRCC_DEV0_EPF2_STRAP3_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP4 0xd104 +#define regRCC_DEV0_EPF2_STRAP4_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP5 0xd105 +#define regRCC_DEV0_EPF2_STRAP5_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP6 0xd106 +#define regRCC_DEV0_EPF2_STRAP6_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP7 0xd107 +#define regRCC_DEV0_EPF2_STRAP7_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP10 0xd10a +#define regRCC_DEV0_EPF2_STRAP10_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP11 0xd10b +#define regRCC_DEV0_EPF2_STRAP11_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP12 0xd10c +#define regRCC_DEV0_EPF2_STRAP12_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP13 0xd10d +#define regRCC_DEV0_EPF2_STRAP13_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP14 0xd10e +#define regRCC_DEV0_EPF2_STRAP14_BASE_IDX 8 +#define regRCC_DEV0_EPF2_STRAP20 0xd114 +#define regRCC_DEV0_EPF2_STRAP20_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP0 0xd180 +#define regRCC_DEV0_EPF3_STRAP0_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP2 0xd182 +#define regRCC_DEV0_EPF3_STRAP2_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP3 0xd183 +#define regRCC_DEV0_EPF3_STRAP3_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP4 0xd184 +#define regRCC_DEV0_EPF3_STRAP4_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP5 0xd185 +#define regRCC_DEV0_EPF3_STRAP5_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP6 0xd186 +#define regRCC_DEV0_EPF3_STRAP6_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP7 0xd187 +#define regRCC_DEV0_EPF3_STRAP7_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP10 0xd18a +#define regRCC_DEV0_EPF3_STRAP10_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP11 0xd18b +#define regRCC_DEV0_EPF3_STRAP11_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP12 0xd18c +#define regRCC_DEV0_EPF3_STRAP12_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP13 0xd18d +#define regRCC_DEV0_EPF3_STRAP13_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP14 0xd18e +#define regRCC_DEV0_EPF3_STRAP14_BASE_IDX 8 +#define regRCC_DEV0_EPF3_STRAP20 0xd194 +#define regRCC_DEV0_EPF3_STRAP20_BASE_IDX 8 +#define regRCC_DEV0_EPF4_STRAP0 0xd200 +#define regRCC_DEV0_EPF4_STRAP0_BASE_IDX 8 +#define regRCC_DEV0_EPF4_STRAP2 0xd202 +#define regRCC_DEV0_EPF4_STRAP2_BASE_IDX 8 +#define regRCC_DEV0_EPF4_STRAP3 0xd203 +#define regRCC_DEV0_EPF4_STRAP3_BASE_IDX 8 +#define regRCC_DEV0_EPF4_STRAP4 0xd204 +#define regRCC_DEV0_EPF4_STRAP4_BASE_IDX 8 +#define regRCC_DEV0_EPF4_STRAP5 0xd205 +#define regRCC_DEV0_EPF4_STRAP5_BASE_IDX 8 +#define regRCC_DEV0_EPF4_STRAP6 0xd206 +#define regRCC_DEV0_EPF4_STRAP6_BASE_IDX 8 +#define regRCC_DEV0_EPF4_STRAP7 0xd207 +#define regRCC_DEV0_EPF4_STRAP7_BASE_IDX 8 +#define regRCC_DEV0_EPF4_STRAP13 0xd20d +#define regRCC_DEV0_EPF4_STRAP13_BASE_IDX 8 +#define regRCC_DEV0_EPF4_STRAP14 0xd20e +#define regRCC_DEV0_EPF4_STRAP14_BASE_IDX 8 +#define regRCC_DEV0_EPF5_STRAP0 0xd280 +#define regRCC_DEV0_EPF5_STRAP0_BASE_IDX 8 +#define regRCC_DEV0_EPF5_STRAP2 0xd282 +#define regRCC_DEV0_EPF5_STRAP2_BASE_IDX 8 +#define regRCC_DEV0_EPF5_STRAP3 0xd283 +#define regRCC_DEV0_EPF5_STRAP3_BASE_IDX 8 +#define regRCC_DEV0_EPF5_STRAP4 0xd284 +#define regRCC_DEV0_EPF5_STRAP4_BASE_IDX 8 +#define regRCC_DEV0_EPF5_STRAP5 0xd285 +#define regRCC_DEV0_EPF5_STRAP5_BASE_IDX 8 +#define regRCC_DEV0_EPF5_STRAP6 0xd286 +#define regRCC_DEV0_EPF5_STRAP6_BASE_IDX 8 +#define regRCC_DEV0_EPF5_STRAP7 0xd287 +#define regRCC_DEV0_EPF5_STRAP7_BASE_IDX 8 +#define regRCC_DEV0_EPF5_STRAP13 0xd28d +#define regRCC_DEV0_EPF5_STRAP13_BASE_IDX 8 +#define regRCC_DEV0_EPF5_STRAP14 0xd28e +#define regRCC_DEV0_EPF5_STRAP14_BASE_IDX 8 +#define regRCC_DEV0_EPF6_STRAP0 0xd300 +#define regRCC_DEV0_EPF6_STRAP0_BASE_IDX 8 +#define regRCC_DEV0_EPF6_STRAP2 0xd302 +#define regRCC_DEV0_EPF6_STRAP2_BASE_IDX 8 +#define regRCC_DEV0_EPF6_STRAP3 0xd303 +#define regRCC_DEV0_EPF6_STRAP3_BASE_IDX 8 +#define regRCC_DEV0_EPF6_STRAP4 0xd304 +#define regRCC_DEV0_EPF6_STRAP4_BASE_IDX 8 +#define regRCC_DEV0_EPF6_STRAP5 0xd305 +#define regRCC_DEV0_EPF6_STRAP5_BASE_IDX 8 +#define regRCC_DEV0_EPF6_STRAP6 0xd306 +#define regRCC_DEV0_EPF6_STRAP6_BASE_IDX 8 +#define regRCC_DEV0_EPF6_STRAP13 0xd30d +#define regRCC_DEV0_EPF6_STRAP13_BASE_IDX 8 +#define regRCC_DEV0_EPF6_STRAP14 0xd30e +#define regRCC_DEV0_EPF6_STRAP14_BASE_IDX 8 +#define regRCC_DEV0_EPF7_STRAP0 0xd380 +#define regRCC_DEV0_EPF7_STRAP0_BASE_IDX 8 +#define regRCC_DEV0_EPF7_STRAP2 0xd382 +#define regRCC_DEV0_EPF7_STRAP2_BASE_IDX 8 +#define regRCC_DEV0_EPF7_STRAP3 0xd383 +#define regRCC_DEV0_EPF7_STRAP3_BASE_IDX 8 +#define regRCC_DEV0_EPF7_STRAP4 0xd384 +#define regRCC_DEV0_EPF7_STRAP4_BASE_IDX 8 +#define regRCC_DEV0_EPF7_STRAP5 0xd385 +#define regRCC_DEV0_EPF7_STRAP5_BASE_IDX 8 +#define regRCC_DEV0_EPF7_STRAP6 0xd386 +#define regRCC_DEV0_EPF7_STRAP6_BASE_IDX 8 +#define regRCC_DEV0_EPF7_STRAP7 0xd387 +#define regRCC_DEV0_EPF7_STRAP7_BASE_IDX 8 +#define regRCC_DEV0_EPF7_STRAP13 0xd38d +#define regRCC_DEV0_EPF7_STRAP13_BASE_IDX 8 +#define regRCC_DEV0_EPF7_STRAP14 0xd38e +#define regRCC_DEV0_EPF7_STRAP14_BASE_IDX 8 +#define regRCC_DEV1_EPF0_STRAP0 0xd400 +#define regRCC_DEV1_EPF0_STRAP0_BASE_IDX 8 +#define regRCC_DEV1_EPF0_STRAP2 0xd402 +#define regRCC_DEV1_EPF0_STRAP2_BASE_IDX 8 +#define regRCC_DEV1_EPF0_STRAP3 0xd403 +#define regRCC_DEV1_EPF0_STRAP3_BASE_IDX 8 +#define regRCC_DEV1_EPF0_STRAP4 0xd404 +#define regRCC_DEV1_EPF0_STRAP4_BASE_IDX 8 +#define regRCC_DEV1_EPF0_STRAP5 0xd405 +#define regRCC_DEV1_EPF0_STRAP5_BASE_IDX 8 +#define regRCC_DEV1_EPF0_STRAP6 0xd406 +#define regRCC_DEV1_EPF0_STRAP6_BASE_IDX 8 +#define regRCC_DEV1_EPF0_STRAP7 0xd407 +#define regRCC_DEV1_EPF0_STRAP7_BASE_IDX 8 +#define regRCC_DEV1_EPF0_STRAP13 0xd40d +#define regRCC_DEV1_EPF0_STRAP13_BASE_IDX 8 +#define regRCC_DEV1_EPF0_STRAP14 0xd40e +#define regRCC_DEV1_EPF0_STRAP14_BASE_IDX 8 +#define regRCC_DEV1_EPF1_STRAP0 0xd480 +#define regRCC_DEV1_EPF1_STRAP0_BASE_IDX 8 +#define regRCC_DEV1_EPF1_STRAP2 0xd482 +#define regRCC_DEV1_EPF1_STRAP2_BASE_IDX 8 +#define regRCC_DEV1_EPF1_STRAP3 0xd483 +#define regRCC_DEV1_EPF1_STRAP3_BASE_IDX 8 +#define regRCC_DEV1_EPF1_STRAP4 0xd484 +#define regRCC_DEV1_EPF1_STRAP4_BASE_IDX 8 +#define regRCC_DEV1_EPF1_STRAP5 0xd485 +#define regRCC_DEV1_EPF1_STRAP5_BASE_IDX 8 +#define regRCC_DEV1_EPF1_STRAP6 0xd486 +#define regRCC_DEV1_EPF1_STRAP6_BASE_IDX 8 +#define regRCC_DEV1_EPF1_STRAP7 0xd487 +#define regRCC_DEV1_EPF1_STRAP7_BASE_IDX 8 +#define regRCC_DEV1_EPF1_STRAP13 0xd48d +#define regRCC_DEV1_EPF1_STRAP13_BASE_IDX 8 +#define regRCC_DEV1_EPF1_STRAP14 0xd48e +#define regRCC_DEV1_EPF1_STRAP14_BASE_IDX 8 +#define regRCC_DEV2_EPF0_STRAP0 0xd800 +#define regRCC_DEV2_EPF0_STRAP0_BASE_IDX 8 +#define regRCC_DEV2_EPF0_STRAP2 0xd802 +#define regRCC_DEV2_EPF0_STRAP2_BASE_IDX 8 +#define regRCC_DEV2_EPF0_STRAP3 0xd803 +#define regRCC_DEV2_EPF0_STRAP3_BASE_IDX 8 +#define regRCC_DEV2_EPF0_STRAP4 0xd804 +#define regRCC_DEV2_EPF0_STRAP4_BASE_IDX 8 +#define regRCC_DEV2_EPF0_STRAP5 0xd805 +#define regRCC_DEV2_EPF0_STRAP5_BASE_IDX 8 +#define regRCC_DEV2_EPF0_STRAP6 0xd806 +#define regRCC_DEV2_EPF0_STRAP6_BASE_IDX 8 +#define regRCC_DEV2_EPF0_STRAP7 0xd807 +#define regRCC_DEV2_EPF0_STRAP7_BASE_IDX 8 +#define regRCC_DEV2_EPF0_STRAP13 0xd80d +#define regRCC_DEV2_EPF0_STRAP13_BASE_IDX 8 +#define regRCC_DEV2_EPF0_STRAP14 0xd80e +#define regRCC_DEV2_EPF0_STRAP14_BASE_IDX 8 +#define regRCC_DEV2_EPF1_STRAP0 0xd880 +#define regRCC_DEV2_EPF1_STRAP0_BASE_IDX 8 +#define regRCC_DEV2_EPF1_STRAP2 0xd882 +#define regRCC_DEV2_EPF1_STRAP2_BASE_IDX 8 +#define regRCC_DEV2_EPF1_STRAP3 0xd883 +#define regRCC_DEV2_EPF1_STRAP3_BASE_IDX 8 +#define regRCC_DEV2_EPF1_STRAP4 0xd884 +#define regRCC_DEV2_EPF1_STRAP4_BASE_IDX 8 +#define regRCC_DEV2_EPF1_STRAP5 0xd885 +#define regRCC_DEV2_EPF1_STRAP5_BASE_IDX 8 +#define regRCC_DEV2_EPF1_STRAP6 0xd886 +#define regRCC_DEV2_EPF1_STRAP6_BASE_IDX 8 +#define regRCC_DEV2_EPF1_STRAP13 0xd88d +#define regRCC_DEV2_EPF1_STRAP13_BASE_IDX 8 +#define regRCC_DEV2_EPF1_STRAP14 0xd88e +#define regRCC_DEV2_EPF1_STRAP14_BASE_IDX 8 +#define regRCC_DEV2_EPF2_STRAP0 0xd900 +#define regRCC_DEV2_EPF2_STRAP0_BASE_IDX 8 +#define regRCC_DEV2_EPF2_STRAP2 0xd902 +#define regRCC_DEV2_EPF2_STRAP2_BASE_IDX 8 +#define regRCC_DEV2_EPF2_STRAP3 0xd903 +#define regRCC_DEV2_EPF2_STRAP3_BASE_IDX 8 +#define regRCC_DEV2_EPF2_STRAP4 0xd904 +#define regRCC_DEV2_EPF2_STRAP4_BASE_IDX 8 +#define regRCC_DEV2_EPF2_STRAP5 0xd905 +#define regRCC_DEV2_EPF2_STRAP5_BASE_IDX 8 +#define regRCC_DEV2_EPF2_STRAP6 0xd906 +#define regRCC_DEV2_EPF2_STRAP6_BASE_IDX 8 +#define regRCC_DEV2_EPF2_STRAP13 0xd90d +#define regRCC_DEV2_EPF2_STRAP13_BASE_IDX 8 +#define regRCC_DEV2_EPF2_STRAP14 0xd90e +#define regRCC_DEV2_EPF2_STRAP14_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_rst_bif_rst_regblk +// base address: 0x10100000 +#define regHARD_RST_CTRL 0xe000 +#define regHARD_RST_CTRL_BASE_IDX 8 +#define regSELF_SOFT_RST 0xe002 +#define regSELF_SOFT_RST_BASE_IDX 8 +#define regBIF_GFX_DRV_VPU_RST 0xe003 +#define regBIF_GFX_DRV_VPU_RST_BASE_IDX 8 +#define regBIF_RST_MISC_CTRL 0xe004 +#define regBIF_RST_MISC_CTRL_BASE_IDX 8 +#define regBIF_RST_MISC_CTRL2 0xe005 +#define regBIF_RST_MISC_CTRL2_BASE_IDX 8 +#define regBIF_RST_MISC_CTRL3 0xe006 +#define regBIF_RST_MISC_CTRL3_BASE_IDX 8 +#define regDEV0_PF0_FLR_RST_CTRL 0xe008 +#define regDEV0_PF0_FLR_RST_CTRL_BASE_IDX 8 +#define regDEV0_PF1_FLR_RST_CTRL 0xe009 +#define regDEV0_PF1_FLR_RST_CTRL_BASE_IDX 8 +#define regBIF_INST_RESET_INTR_STS 0xe010 +#define regBIF_INST_RESET_INTR_STS_BASE_IDX 8 +#define regBIF_PF_FLR_INTR_STS 0xe011 +#define regBIF_PF_FLR_INTR_STS_BASE_IDX 8 +#define regBIF_D3HOTD0_INTR_STS 0xe012 +#define regBIF_D3HOTD0_INTR_STS_BASE_IDX 8 +#define regBIF_POWER_INTR_STS 0xe014 +#define regBIF_POWER_INTR_STS_BASE_IDX 8 +#define regBIF_PF_DSTATE_INTR_STS 0xe015 +#define regBIF_PF_DSTATE_INTR_STS_BASE_IDX 8 +#define regSELF_SOFT_RST_2 0xe016 +#define regSELF_SOFT_RST_2_BASE_IDX 8 +#define regBIF_INST_RESET_INTR_MASK 0xe020 +#define regBIF_INST_RESET_INTR_MASK_BASE_IDX 8 +#define regBIF_PF_FLR_INTR_MASK 0xe021 +#define regBIF_PF_FLR_INTR_MASK_BASE_IDX 8 +#define regBIF_D3HOTD0_INTR_MASK 0xe022 +#define regBIF_D3HOTD0_INTR_MASK_BASE_IDX 8 +#define regBIF_POWER_INTR_MASK 0xe024 +#define regBIF_POWER_INTR_MASK_BASE_IDX 8 +#define regBIF_PF_DSTATE_INTR_MASK 0xe025 +#define regBIF_PF_DSTATE_INTR_MASK_BASE_IDX 8 +#define regBIF_PF_FLR_RST 0xe040 +#define regBIF_PF_FLR_RST_BASE_IDX 8 +#define regBIF_DEV0_PF0_DSTATE_VALUE 0xe050 +#define regBIF_DEV0_PF0_DSTATE_VALUE_BASE_IDX 8 +#define regBIF_DEV0_PF1_DSTATE_VALUE 0xe051 +#define regBIF_DEV0_PF1_DSTATE_VALUE_BASE_IDX 8 +#define regDEV0_PF0_D3HOTD0_RST_CTRL 0xe078 +#define regDEV0_PF0_D3HOTD0_RST_CTRL_BASE_IDX 8 +#define regDEV0_PF1_D3HOTD0_RST_CTRL 0xe079 +#define regDEV0_PF1_D3HOTD0_RST_CTRL_BASE_IDX 8 +#define regBIF_PORT0_DSTATE_VALUE 0xe230 +#define regBIF_PORT0_DSTATE_VALUE_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_misc_bif_misc_regblk +// base address: 0x10100000 +#define regREGS_ROM_OFFSET_CTRL 0xcc23 +#define regREGS_ROM_OFFSET_CTRL_BASE_IDX 8 +#define regNBIF_STRAP_BIOS_CNTL 0xcc81 +#define regNBIF_STRAP_BIOS_CNTL_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_0 0xcd00 +#define regDOORBELL0_CTRL_ENTRY_0_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_1 0xcd01 +#define regDOORBELL0_CTRL_ENTRY_1_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_2 0xcd02 +#define regDOORBELL0_CTRL_ENTRY_2_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_3 0xcd03 +#define regDOORBELL0_CTRL_ENTRY_3_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_4 0xcd04 +#define regDOORBELL0_CTRL_ENTRY_4_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_5 0xcd05 +#define regDOORBELL0_CTRL_ENTRY_5_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_6 0xcd06 +#define regDOORBELL0_CTRL_ENTRY_6_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_7 0xcd07 +#define regDOORBELL0_CTRL_ENTRY_7_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_8 0xcd08 +#define regDOORBELL0_CTRL_ENTRY_8_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_9 0xcd09 +#define regDOORBELL0_CTRL_ENTRY_9_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_10 0xcd0a +#define regDOORBELL0_CTRL_ENTRY_10_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_11 0xcd0b +#define regDOORBELL0_CTRL_ENTRY_11_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_12 0xcd0c +#define regDOORBELL0_CTRL_ENTRY_12_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_13 0xcd0d +#define regDOORBELL0_CTRL_ENTRY_13_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_14 0xcd0e +#define regDOORBELL0_CTRL_ENTRY_14_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_15 0xcd0f +#define regDOORBELL0_CTRL_ENTRY_15_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_16 0xcd10 +#define regDOORBELL0_CTRL_ENTRY_16_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_17 0xcd11 +#define regDOORBELL0_CTRL_ENTRY_17_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_18 0xcd12 +#define regDOORBELL0_CTRL_ENTRY_18_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_19 0xcd13 +#define regDOORBELL0_CTRL_ENTRY_19_BASE_IDX 8 +#define regDOORBELL0_CTRL_ENTRY_20 0xcd14 +#define regDOORBELL0_CTRL_ENTRY_20_BASE_IDX 8 +#define regAID0_VF0_BASE_ADDR 0xcd40 +#define regAID0_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID1_VF0_BASE_ADDR 0xcd41 +#define regAID1_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID2_VF0_BASE_ADDR 0xcd42 +#define regAID2_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID3_VF0_BASE_ADDR 0xcd43 +#define regAID3_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC0_VF0_BASE_ADDR 0xcd44 +#define regAID0_XCC0_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC1_VF0_BASE_ADDR 0xcd45 +#define regAID0_XCC1_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC0_VF0_BASE_ADDR 0xcd46 +#define regAID1_XCC0_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC1_VF0_BASE_ADDR 0xcd47 +#define regAID1_XCC1_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC0_VF0_BASE_ADDR 0xcd48 +#define regAID2_XCC0_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC1_VF0_BASE_ADDR 0xcd49 +#define regAID2_XCC1_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC0_VF0_BASE_ADDR 0xcd4a +#define regAID3_XCC0_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC1_VF0_BASE_ADDR 0xcd4b +#define regAID3_XCC1_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID0_NBIF_VF0_BASE_ADDR 0xcd4c +#define regAID0_NBIF_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID0_ATHUB_VF0_BASE_ADDR 0xcd4d +#define regAID0_ATHUB_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID0_IH_VF0_BASE_ADDR 0xcd4e +#define regAID0_IH_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID0_HDP_VF0_BASE_ADDR 0xcd4f +#define regAID0_HDP_VF0_BASE_ADDR_BASE_IDX 8 +#define regAID0_VF1_BASE_ADDR 0xcd50 +#define regAID0_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID1_VF1_BASE_ADDR 0xcd51 +#define regAID1_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID2_VF1_BASE_ADDR 0xcd52 +#define regAID2_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID3_VF1_BASE_ADDR 0xcd53 +#define regAID3_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC0_VF1_BASE_ADDR 0xcd54 +#define regAID0_XCC0_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC1_VF1_BASE_ADDR 0xcd55 +#define regAID0_XCC1_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC0_VF1_BASE_ADDR 0xcd56 +#define regAID1_XCC0_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC1_VF1_BASE_ADDR 0xcd57 +#define regAID1_XCC1_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC0_VF1_BASE_ADDR 0xcd58 +#define regAID2_XCC0_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC1_VF1_BASE_ADDR 0xcd59 +#define regAID2_XCC1_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC0_VF1_BASE_ADDR 0xcd5a +#define regAID3_XCC0_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC1_VF1_BASE_ADDR 0xcd5b +#define regAID3_XCC1_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID0_NBIF_VF1_BASE_ADDR 0xcd5c +#define regAID0_NBIF_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID0_ATHUB_VF1_BASE_ADDR 0xcd5d +#define regAID0_ATHUB_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID0_IH_VF1_BASE_ADDR 0xcd5e +#define regAID0_IH_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID0_HDP_VF1_BASE_ADDR 0xcd5f +#define regAID0_HDP_VF1_BASE_ADDR_BASE_IDX 8 +#define regAID0_VF2_BASE_ADDR 0xcd60 +#define regAID0_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID1_VF2_BASE_ADDR 0xcd61 +#define regAID1_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID2_VF2_BASE_ADDR 0xcd62 +#define regAID2_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID3_VF2_BASE_ADDR 0xcd63 +#define regAID3_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC0_VF2_BASE_ADDR 0xcd64 +#define regAID0_XCC0_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC1_VF2_BASE_ADDR 0xcd65 +#define regAID0_XCC1_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC0_VF2_BASE_ADDR 0xcd66 +#define regAID1_XCC0_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC1_VF2_BASE_ADDR 0xcd67 +#define regAID1_XCC1_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC0_VF2_BASE_ADDR 0xcd68 +#define regAID2_XCC0_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC1_VF2_BASE_ADDR 0xcd69 +#define regAID2_XCC1_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC0_VF2_BASE_ADDR 0xcd6a +#define regAID3_XCC0_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC1_VF2_BASE_ADDR 0xcd6b +#define regAID3_XCC1_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID0_NBIF_VF2_BASE_ADDR 0xcd6c +#define regAID0_NBIF_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID0_ATHUB_VF2_BASE_ADDR 0xcd6d +#define regAID0_ATHUB_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID0_IH_VF2_BASE_ADDR 0xcd6e +#define regAID0_IH_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID0_HDP_VF2_BASE_ADDR 0xcd6f +#define regAID0_HDP_VF2_BASE_ADDR_BASE_IDX 8 +#define regAID0_VF3_BASE_ADDR 0xcd70 +#define regAID0_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID1_VF3_BASE_ADDR 0xcd71 +#define regAID1_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID2_VF3_BASE_ADDR 0xcd72 +#define regAID2_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID3_VF3_BASE_ADDR 0xcd73 +#define regAID3_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC0_VF3_BASE_ADDR 0xcd74 +#define regAID0_XCC0_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC1_VF3_BASE_ADDR 0xcd75 +#define regAID0_XCC1_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC0_VF3_BASE_ADDR 0xcd76 +#define regAID1_XCC0_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC1_VF3_BASE_ADDR 0xcd77 +#define regAID1_XCC1_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC0_VF3_BASE_ADDR 0xcd78 +#define regAID2_XCC0_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC1_VF3_BASE_ADDR 0xcd79 +#define regAID2_XCC1_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC0_VF3_BASE_ADDR 0xcd7a +#define regAID3_XCC0_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC1_VF3_BASE_ADDR 0xcd7b +#define regAID3_XCC1_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID0_NBIF_VF3_BASE_ADDR 0xcd7c +#define regAID0_NBIF_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID0_ATHUB_VF3_BASE_ADDR 0xcd7d +#define regAID0_ATHUB_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID0_IH_VF3_BASE_ADDR 0xcd7e +#define regAID0_IH_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID0_HDP_VF3_BASE_ADDR 0xcd7f +#define regAID0_HDP_VF3_BASE_ADDR_BASE_IDX 8 +#define regAID0_VF4_BASE_ADDR 0xcd80 +#define regAID0_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID1_VF4_BASE_ADDR 0xcd81 +#define regAID1_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID2_VF4_BASE_ADDR 0xcd82 +#define regAID2_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID3_VF4_BASE_ADDR 0xcd83 +#define regAID3_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC0_VF4_BASE_ADDR 0xcd84 +#define regAID0_XCC0_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC1_VF4_BASE_ADDR 0xcd85 +#define regAID0_XCC1_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC0_VF4_BASE_ADDR 0xcd86 +#define regAID1_XCC0_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC1_VF4_BASE_ADDR 0xcd87 +#define regAID1_XCC1_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC0_VF4_BASE_ADDR 0xcd88 +#define regAID2_XCC0_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC1_VF4_BASE_ADDR 0xcd89 +#define regAID2_XCC1_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC0_VF4_BASE_ADDR 0xcd8a +#define regAID3_XCC0_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC1_VF4_BASE_ADDR 0xcd8b +#define regAID3_XCC1_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID0_NBIF_VF4_BASE_ADDR 0xcd8c +#define regAID0_NBIF_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID0_ATHUB_VF4_BASE_ADDR 0xcd8d +#define regAID0_ATHUB_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID0_IH_VF4_BASE_ADDR 0xcd8e +#define regAID0_IH_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID0_HDP_VF4_BASE_ADDR 0xcd8f +#define regAID0_HDP_VF4_BASE_ADDR_BASE_IDX 8 +#define regAID0_VF5_BASE_ADDR 0xcd90 +#define regAID0_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID1_VF5_BASE_ADDR 0xcd91 +#define regAID1_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID2_VF5_BASE_ADDR 0xcd92 +#define regAID2_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID3_VF5_BASE_ADDR 0xcd93 +#define regAID3_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC0_VF5_BASE_ADDR 0xcd94 +#define regAID0_XCC0_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC1_VF5_BASE_ADDR 0xcd95 +#define regAID0_XCC1_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC0_VF5_BASE_ADDR 0xcd96 +#define regAID1_XCC0_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC1_VF5_BASE_ADDR 0xcd97 +#define regAID1_XCC1_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC0_VF5_BASE_ADDR 0xcd98 +#define regAID2_XCC0_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC1_VF5_BASE_ADDR 0xcd99 +#define regAID2_XCC1_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC0_VF5_BASE_ADDR 0xcd9a +#define regAID3_XCC0_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC1_VF5_BASE_ADDR 0xcd9b +#define regAID3_XCC1_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID0_NBIF_VF5_BASE_ADDR 0xcd9c +#define regAID0_NBIF_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID0_ATHUB_VF5_BASE_ADDR 0xcd9d +#define regAID0_ATHUB_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID0_IH_VF5_BASE_ADDR 0xcd9e +#define regAID0_IH_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID0_HDP_VF5_BASE_ADDR 0xcd9f +#define regAID0_HDP_VF5_BASE_ADDR_BASE_IDX 8 +#define regAID0_VF6_BASE_ADDR 0xcda0 +#define regAID0_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID1_VF6_BASE_ADDR 0xcda1 +#define regAID1_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID2_VF6_BASE_ADDR 0xcda2 +#define regAID2_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID3_VF6_BASE_ADDR 0xcda3 +#define regAID3_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC0_VF6_BASE_ADDR 0xcda4 +#define regAID0_XCC0_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC1_VF6_BASE_ADDR 0xcda5 +#define regAID0_XCC1_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC0_VF6_BASE_ADDR 0xcda6 +#define regAID1_XCC0_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC1_VF6_BASE_ADDR 0xcda7 +#define regAID1_XCC1_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC0_VF6_BASE_ADDR 0xcda8 +#define regAID2_XCC0_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC1_VF6_BASE_ADDR 0xcda9 +#define regAID2_XCC1_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC0_VF6_BASE_ADDR 0xcdaa +#define regAID3_XCC0_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC1_VF6_BASE_ADDR 0xcdab +#define regAID3_XCC1_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID0_NBIF_VF6_BASE_ADDR 0xcdac +#define regAID0_NBIF_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID0_ATHUB_VF6_BASE_ADDR 0xcdad +#define regAID0_ATHUB_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID0_IH_VF6_BASE_ADDR 0xcdae +#define regAID0_IH_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID0_HDP_VF6_BASE_ADDR 0xcdaf +#define regAID0_HDP_VF6_BASE_ADDR_BASE_IDX 8 +#define regAID0_VF7_BASE_ADDR 0xcdb0 +#define regAID0_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID1_VF7_BASE_ADDR 0xcdb1 +#define regAID1_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID2_VF7_BASE_ADDR 0xcdb2 +#define regAID2_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID3_VF7_BASE_ADDR 0xcdb3 +#define regAID3_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC0_VF7_BASE_ADDR 0xcdb4 +#define regAID0_XCC0_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC1_VF7_BASE_ADDR 0xcdb5 +#define regAID0_XCC1_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC0_VF7_BASE_ADDR 0xcdb6 +#define regAID1_XCC0_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC1_VF7_BASE_ADDR 0xcdb7 +#define regAID1_XCC1_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC0_VF7_BASE_ADDR 0xcdb8 +#define regAID2_XCC0_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC1_VF7_BASE_ADDR 0xcdb9 +#define regAID2_XCC1_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC0_VF7_BASE_ADDR 0xcdba +#define regAID3_XCC0_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC1_VF7_BASE_ADDR 0xcdbb +#define regAID3_XCC1_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID0_NBIF_VF7_BASE_ADDR 0xcdbc +#define regAID0_NBIF_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID0_ATHUB_VF7_BASE_ADDR 0xcdbd +#define regAID0_ATHUB_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID0_IH_VF7_BASE_ADDR 0xcdbe +#define regAID0_IH_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID0_HDP_VF7_BASE_ADDR 0xcdbf +#define regAID0_HDP_VF7_BASE_ADDR_BASE_IDX 8 +#define regAID0_PF_BASE_ADDR 0xcdc0 +#define regAID0_PF_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC0_PF_BASE_ADDR 0xcdc1 +#define regAID0_XCC0_PF_BASE_ADDR_BASE_IDX 8 +#define regAID0_XCC1_PF_BASE_ADDR 0xcdc2 +#define regAID0_XCC1_PF_BASE_ADDR_BASE_IDX 8 +#define regAID1_PF_BASE_ADDR 0xcdc3 +#define regAID1_PF_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC0_PF_BASE_ADDR 0xcdc4 +#define regAID1_XCC0_PF_BASE_ADDR_BASE_IDX 8 +#define regAID1_XCC1_PF_BASE_ADDR 0xcdc5 +#define regAID1_XCC1_PF_BASE_ADDR_BASE_IDX 8 +#define regAID2_PF_BASE_ADDR 0xcdc6 +#define regAID2_PF_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC0_PF_BASE_ADDR 0xcdc7 +#define regAID2_XCC0_PF_BASE_ADDR_BASE_IDX 8 +#define regAID2_XCC1_PF_BASE_ADDR 0xcdc8 +#define regAID2_XCC1_PF_BASE_ADDR_BASE_IDX 8 +#define regAID3_PF_BASE_ADDR 0xcdc9 +#define regAID3_PF_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC0_PF_BASE_ADDR 0xcdca +#define regAID3_XCC0_PF_BASE_ADDR_BASE_IDX 8 +#define regAID3_XCC1_PF_BASE_ADDR 0xcdcb +#define regAID3_XCC1_PF_BASE_ADDR_BASE_IDX 8 +#define regNBIF_RRMT_CNTL 0xcddc +#define regNBIF_RRMT_CNTL_BASE_IDX 8 +#define regBIFC_DOORBELL_ACCESS_EN_PF 0xcf6e +#define regBIFC_DOORBELL_ACCESS_EN_PF_BASE_IDX 8 +#define regBIFC_DOORBELL_ACCESS_EN_VF0 0xcf6f +#define regBIFC_DOORBELL_ACCESS_EN_VF0_BASE_IDX 8 +#define regBIFC_DOORBELL_ACCESS_EN_VF1 0xcf70 +#define regBIFC_DOORBELL_ACCESS_EN_VF1_BASE_IDX 8 +#define regBIFC_DOORBELL_ACCESS_EN_VF2 0xcf71 +#define regBIFC_DOORBELL_ACCESS_EN_VF2_BASE_IDX 8 +#define regBIFC_DOORBELL_ACCESS_EN_VF3 0xcf72 +#define regBIFC_DOORBELL_ACCESS_EN_VF3_BASE_IDX 8 +#define regBIFC_DOORBELL_ACCESS_EN_VF4 0xcf73 +#define regBIFC_DOORBELL_ACCESS_EN_VF4_BASE_IDX 8 +#define regBIFC_DOORBELL_ACCESS_EN_VF5 0xcf74 +#define regBIFC_DOORBELL_ACCESS_EN_VF5_BASE_IDX 8 +#define regBIFC_DOORBELL_ACCESS_EN_VF6 0xcf75 +#define regBIFC_DOORBELL_ACCESS_EN_VF6_BASE_IDX 8 +#define regBIFC_DOORBELL_ACCESS_EN_VF7 0xcf76 +#define regBIFC_DOORBELL_ACCESS_EN_VF7_BASE_IDX 8 +#define regMISC_SCRATCH 0xe800 +#define regMISC_SCRATCH_BASE_IDX 8 +#define regINTR_LINE_POLARITY 0xe801 +#define regINTR_LINE_POLARITY_BASE_IDX 8 +#define regINTR_LINE_ENABLE 0xe802 +#define regINTR_LINE_ENABLE_BASE_IDX 8 +#define regOUTSTANDING_VC_ALLOC 0xe803 +#define regOUTSTANDING_VC_ALLOC_BASE_IDX 8 +#define regBIFC_MISC_CTRL0 0xe804 +#define regBIFC_MISC_CTRL0_BASE_IDX 8 +#define regBIFC_MISC_CTRL1 0xe805 +#define regBIFC_MISC_CTRL1_BASE_IDX 8 +#define regBIFC_BME_ERR_LOG_LB 0xe806 +#define regBIFC_BME_ERR_LOG_LB_BASE_IDX 8 +#define regBIFC_LC_TIMER_CTRL 0xe807 +#define regBIFC_LC_TIMER_CTRL_BASE_IDX 8 +#define regBIFC_RCCBIH_BME_ERR_LOG0 0xe808 +#define regBIFC_RCCBIH_BME_ERR_LOG0_BASE_IDX 8 +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 0xe80a +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_BASE_IDX 8 +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 0xe80b +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_BASE_IDX 8 +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 0xe80c +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_BASE_IDX 8 +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 0xe80d +#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_BASE_IDX 8 +#define regBIFC_DMA_ATTR_CNTL2_DEV0 0xe81a +#define regBIFC_DMA_ATTR_CNTL2_DEV0_BASE_IDX 8 +#define regBME_DUMMY_CNTL_0 0xe825 +#define regBME_DUMMY_CNTL_0_BASE_IDX 8 +#define regBIFC_THT_CNTL 0xe827 +#define regBIFC_THT_CNTL_BASE_IDX 8 +#define regBIFC_HSTARB_CNTL 0xe828 +#define regBIFC_HSTARB_CNTL_BASE_IDX 8 +#define regBIFC_GSI_CNTL 0xe829 +#define regBIFC_GSI_CNTL_BASE_IDX 8 +#define regBIFC_PCIEFUNC_CNTL 0xe82a +#define regBIFC_PCIEFUNC_CNTL_BASE_IDX 8 +#define regBIFC_PASID_CHECK_DIS 0xe82b +#define regBIFC_PASID_CHECK_DIS_BASE_IDX 8 +#define regBIFC_SDP_CNTL_0 0xe82c +#define regBIFC_SDP_CNTL_0_BASE_IDX 8 +#define regBIFC_SDP_CNTL_1 0xe82d +#define regBIFC_SDP_CNTL_1_BASE_IDX 8 +#define regBIFC_PASID_STS 0xe82e +#define regBIFC_PASID_STS_BASE_IDX 8 +#define regBIFC_ATHUB_ACT_CNTL 0xe82f +#define regBIFC_ATHUB_ACT_CNTL_BASE_IDX 8 +#define regBIFC_PERF_CNTL_0 0xe830 +#define regBIFC_PERF_CNTL_0_BASE_IDX 8 +#define regBIFC_PERF_CNTL_1 0xe831 +#define regBIFC_PERF_CNTL_1_BASE_IDX 8 +#define regBIFC_PERF_CNT_MMIO_RD_L32BIT 0xe832 +#define regBIFC_PERF_CNT_MMIO_RD_L32BIT_BASE_IDX 8 +#define regBIFC_PERF_CNT_MMIO_WR_L32BIT 0xe833 +#define regBIFC_PERF_CNT_MMIO_WR_L32BIT_BASE_IDX 8 +#define regBIFC_PERF_CNT_DMA_RD_L32BIT 0xe834 +#define regBIFC_PERF_CNT_DMA_RD_L32BIT_BASE_IDX 8 +#define regBIFC_PERF_CNT_DMA_WR_L32BIT 0xe835 +#define regBIFC_PERF_CNT_DMA_WR_L32BIT_BASE_IDX 8 +#define regNBIF_REGIF_ERRSET_CTRL 0xe836 +#define regNBIF_REGIF_ERRSET_CTRL_BASE_IDX 8 +#define regBIFC_SDP_CNTL_2 0xe837 +#define regBIFC_SDP_CNTL_2_BASE_IDX 8 +#define regNBIF_PGMST_CTRL 0xe838 +#define regNBIF_PGMST_CTRL_BASE_IDX 8 +#define regNBIF_PGSLV_CTRL 0xe839 +#define regNBIF_PGSLV_CTRL_BASE_IDX 8 +#define regNBIF_PG_MISC_CTRL 0xe83a +#define regNBIF_PG_MISC_CTRL_BASE_IDX 8 +#define regSMN_MST_EP_CNTL3 0xe83c +#define regSMN_MST_EP_CNTL3_BASE_IDX 8 +#define regSMN_MST_EP_CNTL4 0xe83d +#define regSMN_MST_EP_CNTL4_BASE_IDX 8 +#define regSMN_MST_CNTL1 0xe83e +#define regSMN_MST_CNTL1_BASE_IDX 8 +#define regSMN_MST_EP_CNTL5 0xe83f +#define regSMN_MST_EP_CNTL5_BASE_IDX 8 +#define regBIF_SELFRING_BUFFER_VID 0xe840 +#define regBIF_SELFRING_BUFFER_VID_BASE_IDX 8 +#define regBIF_SELFRING_VECTOR_CNTL 0xe841 +#define regBIF_SELFRING_VECTOR_CNTL_BASE_IDX 8 +#define regNBIF_STRAP_WRITE_CTRL 0xe845 +#define regNBIF_STRAP_WRITE_CTRL_BASE_IDX 8 +#define regNBIF_INTX_DSTATE_MISC_CNTL 0xe846 +#define regNBIF_INTX_DSTATE_MISC_CNTL_BASE_IDX 8 +#define regNBIF_PENDING_MISC_CNTL 0xe847 +#define regNBIF_PENDING_MISC_CNTL_BASE_IDX 8 +#define regBIF_GMI_WRR_WEIGHT 0xe848 +#define regBIF_GMI_WRR_WEIGHT_BASE_IDX 8 +#define regBIF_GMI_WRR_WEIGHT2 0xe849 +#define regBIF_GMI_WRR_WEIGHT2_BASE_IDX 8 +#define regBIF_GMI_WRR_WEIGHT3 0xe84a +#define regBIF_GMI_WRR_WEIGHT3_BASE_IDX 8 +#define regNBIF_PWRBRK_REQUEST 0xe84c +#define regNBIF_PWRBRK_REQUEST_BASE_IDX 8 +#define regBIF_ATOMIC_ERR_LOG_DEV0_F0 0xe850 +#define regBIF_ATOMIC_ERR_LOG_DEV0_F0_BASE_IDX 8 +#define regBIF_ATOMIC_ERR_LOG_DEV0_F1 0xe851 +#define regBIF_ATOMIC_ERR_LOG_DEV0_F1_BASE_IDX 8 +#define regBIF_DMA_MP4_ERR_LOG 0xe870 +#define regBIF_DMA_MP4_ERR_LOG_BASE_IDX 8 +#define regBIF_PASID_ERR_LOG 0xe871 +#define regBIF_PASID_ERR_LOG_BASE_IDX 8 +#define regBIF_PASID_ERR_CLR 0xe872 +#define regBIF_PASID_ERR_CLR_BASE_IDX 8 +#define regNBIF_VWIRE_CTRL 0xe880 +#define regNBIF_VWIRE_CTRL_BASE_IDX 8 +#define regNBIF_SMN_VWR_VCHG_DIS_CTRL 0xe881 +#define regNBIF_SMN_VWR_VCHG_DIS_CTRL_BASE_IDX 8 +#define regNBIF_SMN_VWR_VCHG_RST_CTRL0 0xe882 +#define regNBIF_SMN_VWR_VCHG_RST_CTRL0_BASE_IDX 8 +#define regNBIF_SMN_VWR_VCHG_TRIG 0xe884 +#define regNBIF_SMN_VWR_VCHG_TRIG_BASE_IDX 8 +#define regNBIF_SMN_VWR_WTRIG_CNTL 0xe885 +#define regNBIF_SMN_VWR_WTRIG_CNTL_BASE_IDX 8 +#define regNBIF_SMN_VWR_VCHG_DIS_CTRL_1 0xe886 +#define regNBIF_SMN_VWR_VCHG_DIS_CTRL_1_BASE_IDX 8 +#define regNBIF_MGCG_CTRL_LCLK 0xe887 +#define regNBIF_MGCG_CTRL_LCLK_BASE_IDX 8 +#define regNBIF_DS_CTRL_LCLK 0xe888 +#define regNBIF_DS_CTRL_LCLK_BASE_IDX 8 +#define regSMN_MST_CNTL0 0xe889 +#define regSMN_MST_CNTL0_BASE_IDX 8 +#define regSMN_MST_EP_CNTL1 0xe88a +#define regSMN_MST_EP_CNTL1_BASE_IDX 8 +#define regSMN_MST_EP_CNTL2 0xe88b +#define regSMN_MST_EP_CNTL2_BASE_IDX 8 +#define regNBIF_SDP_VWR_VCHG_DIS_CTRL 0xe88c +#define regNBIF_SDP_VWR_VCHG_DIS_CTRL_BASE_IDX 8 +#define regNBIF_SDP_VWR_VCHG_RST_CTRL0 0xe88d +#define regNBIF_SDP_VWR_VCHG_RST_CTRL0_BASE_IDX 8 +#define regNBIF_SDP_VWR_VCHG_RST_CTRL1 0xe88e +#define regNBIF_SDP_VWR_VCHG_RST_CTRL1_BASE_IDX 8 +#define regNBIF_SDP_VWR_VCHG_TRIG 0xe88f +#define regNBIF_SDP_VWR_VCHG_TRIG_BASE_IDX 8 +#define regNBIF_SHUB_TODET_CTRL 0xe898 +#define regNBIF_SHUB_TODET_CTRL_BASE_IDX 8 +#define regNBIF_SHUB_TODET_CLIENT_CTRL 0xe899 +#define regNBIF_SHUB_TODET_CLIENT_CTRL_BASE_IDX 8 +#define regNBIF_SHUB_TODET_CLIENT_STATUS 0xe89a +#define regNBIF_SHUB_TODET_CLIENT_STATUS_BASE_IDX 8 +#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL 0xe89b +#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL_BASE_IDX 8 +#define regNBIF_SHUB_TODET_CLIENT_CTRL2 0xe89c +#define regNBIF_SHUB_TODET_CLIENT_CTRL2_BASE_IDX 8 +#define regNBIF_SHUB_TODET_CLIENT_STATUS2 0xe89d +#define regNBIF_SHUB_TODET_CLIENT_STATUS2_BASE_IDX 8 +#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2 0xe89e +#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2_BASE_IDX 8 +#define regBIFC_BME_ERR_LOG_HB 0xe8ab +#define regBIFC_BME_ERR_LOG_HB_BASE_IDX 8 +#define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC 0xe8c0 +#define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC_BASE_IDX 8 +#define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC 0xe8c1 +#define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC_BASE_IDX 8 +#define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC 0xe8c2 +#define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC_BASE_IDX 8 +#define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC 0xe8c3 +#define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC_BASE_IDX 8 +#define regDISCON_HYSTERESIS_HEAD_CTRL 0xe8c6 +#define regDISCON_HYSTERESIS_HEAD_CTRL_BASE_IDX 8 +#define regBIFC_EARLY_WAKEUP_CNTL 0xe8d2 +#define regBIFC_EARLY_WAKEUP_CNTL_BASE_IDX 8 +#define regBIFC_PERF_CNT_MMIO_RD_H16BIT 0xe8f0 +#define regBIFC_PERF_CNT_MMIO_RD_H16BIT_BASE_IDX 8 +#define regBIFC_PERF_CNT_MMIO_WR_H16BIT 0xe8f1 +#define regBIFC_PERF_CNT_MMIO_WR_H16BIT_BASE_IDX 8 +#define regBIFC_PERF_CNT_DMA_RD_H16BIT 0xe8f2 +#define regBIFC_PERF_CNT_DMA_RD_H16BIT_BASE_IDX 8 +#define regBIFC_PERF_CNT_DMA_WR_H16BIT 0xe8f3 +#define regBIFC_PERF_CNT_DMA_WR_H16BIT_BASE_IDX 8 +#define regBIFC_A2S_SDP_PORT_CTRL 0xeb00 +#define regBIFC_A2S_SDP_PORT_CTRL_BASE_IDX 8 +#define regBIFC_A2S_CNTL_SW0 0xeb01 +#define regBIFC_A2S_CNTL_SW0_BASE_IDX 8 +#define regBIFC_A2S_MISC_CNTL 0xeb02 +#define regBIFC_A2S_MISC_CNTL_BASE_IDX 8 +#define regBIFC_A2S_TAG_ALLOC_0 0xeb03 +#define regBIFC_A2S_TAG_ALLOC_0_BASE_IDX 8 +#define regBIFC_A2S_TAG_ALLOC_1 0xeb04 +#define regBIFC_A2S_TAG_ALLOC_1_BASE_IDX 8 +#define regBIFC_A2S_CNTL_CL0 0xeb05 +#define regBIFC_A2S_CNTL_CL0_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_dwn_dev0_BIFDEC1 +// base address: 0x10120000 +#define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED 0x8d80 +#define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED_BASE_IDX 8 +#define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH 0x8d81 +#define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH_BASE_IDX 8 +#define regRCC_DWN_DEV0_2_DN_PCIE_CNTL 0x8d83 +#define regRCC_DWN_DEV0_2_DN_PCIE_CNTL_BASE_IDX 8 +#define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL 0x8d84 +#define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL_BASE_IDX 8 +#define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2 0x8d85 +#define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2_BASE_IDX 8 +#define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL 0x8d86 +#define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL_BASE_IDX 8 +#define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL 0x8d87 +#define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL_BASE_IDX 8 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0 0x8d88 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0_BASE_IDX 8 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC 0x8d89 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC_BASE_IDX 8 +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2 0x8d8a +#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 +// base address: 0x10120000 +#define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL 0x8d8c +#define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL_BASE_IDX 8 +#define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL 0x8d8d +#define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL_BASE_IDX 8 +#define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL 0x8d8e +#define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL_BASE_IDX 8 +#define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2 0x8d8f +#define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2_BASE_IDX 8 +#define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC 0x8d90 +#define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC_BASE_IDX 8 +#define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP 0x8d91 +#define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_ep_dev0_BIFDEC1 +// base address: 0x10120000 +#define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH 0x8d60 +#define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_CNTL 0x8d62 +#define regRCC_EP_DEV0_2_EP_PCIE_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL 0x8d63 +#define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS 0x8d64 +#define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2 0x8d65 +#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL 0x8d66 +#define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL 0x8d67 +#define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL 0x8d69 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x8d6a +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x8d6a +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x8d6a +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x8d6a +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x8d6b +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x8d6b +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x8d6b +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 8 +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x8d6b +#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC 0x8d6c +#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2 0x8d6d +#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP 0x8d6f +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR 0x8d70 +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL 0x8d70 +#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x8d70 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 8 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x8d71 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 8 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x8d71 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 8 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x8d71 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 8 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x8d71 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 8 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x8d72 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 8 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x8d72 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 8 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x8d72 +#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL 0x8d72 +#define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED 0x8d73 +#define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL 0x8d75 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID 0x8d76 +#define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL 0x8d77 +#define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL 0x8d78 +#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL_BASE_IDX 8 +#define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL 0x8d79 +#define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_BIFDEC1 +// base address: 0x10120000 +#define regRCC_DEV0_1_RCC_ERR_INT_CNTL 0x8da6 +#define regRCC_DEV0_1_RCC_ERR_INT_CNTL_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_BACO_CNTL_MISC 0x8da7 +#define regRCC_DEV0_1_RCC_BACO_CNTL_MISC_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_RESET_EN 0x8da8 +#define regRCC_DEV0_1_RCC_RESET_EN_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_VDM_SUPPORT 0x8da9 +#define regRCC_DEV0_2_RCC_VDM_SUPPORT_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0 0x8daa +#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1 0x8dab +#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_GPUIOV_REGION 0x8dac +#define regRCC_DEV0_1_RCC_GPUIOV_REGION_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN 0x8dad +#define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL 0x8dae +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET 0x8daf +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE 0x8daf +#define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER_REG_RANGE0 0x8dde +#define regRCC_DEV0_1_RCC_PEER_REG_RANGE0_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER_REG_RANGE1 0x8ddf +#define regRCC_DEV0_1_RCC_PEER_REG_RANGE1_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_BUS_CNTL 0x8de1 +#define regRCC_DEV0_2_RCC_BUS_CNTL_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_CONFIG_CNTL 0x8de2 +#define regRCC_DEV0_1_RCC_CONFIG_CNTL_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_CONFIG_F0_BASE 0x8de6 +#define regRCC_DEV0_1_RCC_CONFIG_F0_BASE_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE 0x8de7 +#define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE 0x8de8 +#define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_XDMA_LO 0x8de9 +#define regRCC_DEV0_1_RCC_XDMA_LO_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_XDMA_HI 0x8dea +#define regRCC_DEV0_1_RCC_XDMA_HI_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC 0x8deb +#define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_BUSNUM_CNTL1 0x8dec +#define regRCC_DEV0_1_RCC_BUSNUM_CNTL1_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_BUSNUM_LIST0 0x8ded +#define regRCC_DEV0_1_RCC_BUSNUM_LIST0_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_BUSNUM_LIST1 0x8dee +#define regRCC_DEV0_1_RCC_BUSNUM_LIST1_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_BUSNUM_CNTL2 0x8def +#define regRCC_DEV0_1_RCC_BUSNUM_CNTL2_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM 0x8df0 +#define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_HOST_BUSNUM 0x8df1 +#define regRCC_DEV0_1_RCC_HOST_BUSNUM_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI 0x8df2 +#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO 0x8df3 +#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI 0x8df4 +#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO 0x8df5 +#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI 0x8df6 +#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO 0x8df7 +#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI 0x8df8 +#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO 0x8df9 +#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0 0x8dfa +#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0_BASE_IDX 8 +#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1 0x8dfb +#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL 0x8dfd +#define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_CMN_LINK_CNTL 0x8dfe +#define regRCC_DEV0_2_RCC_CMN_LINK_CNTL_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE 0x8dff +#define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL 0x8e00 +#define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL_BASE_IDX 8 +#define regRCC_DEV0_2_RCC_MH_ARB_CNTL 0x8e01 +#define regRCC_DEV0_2_RCC_MH_ARB_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_bx_SYSDEC +// base address: 0x10120000 +#define regBIF_BX1_PCIE_INDEX 0x800c +#define regBIF_BX1_PCIE_INDEX_BASE_IDX 8 +#define regBIF_BX1_PCIE_DATA 0x800d +#define regBIF_BX1_PCIE_DATA_BASE_IDX 8 +#define regBIF_BX1_PCIE_INDEX2 0x800e +#define regBIF_BX1_PCIE_INDEX2_BASE_IDX 8 +#define regBIF_BX1_PCIE_DATA2 0x800f +#define regBIF_BX1_PCIE_DATA2_BASE_IDX 8 +#define regBIF_BX1_PCIE_INDEX_HI 0x8010 +#define regBIF_BX1_PCIE_INDEX_HI_BASE_IDX 8 +#define regBIF_BX1_PCIE_INDEX2_HI 0x8011 +#define regBIF_BX1_PCIE_INDEX2_HI_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_0 0x8048 +#define regBIF_BX1_SBIOS_SCRATCH_0_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_1 0x8049 +#define regBIF_BX1_SBIOS_SCRATCH_1_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_2 0x804a +#define regBIF_BX1_SBIOS_SCRATCH_2_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_3 0x804b +#define regBIF_BX1_SBIOS_SCRATCH_3_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_0 0x804c +#define regBIF_BX1_BIOS_SCRATCH_0_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_1 0x804d +#define regBIF_BX1_BIOS_SCRATCH_1_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_2 0x804e +#define regBIF_BX1_BIOS_SCRATCH_2_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_3 0x804f +#define regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_4 0x8050 +#define regBIF_BX1_BIOS_SCRATCH_4_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_5 0x8051 +#define regBIF_BX1_BIOS_SCRATCH_5_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_6 0x8052 +#define regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_7 0x8053 +#define regBIF_BX1_BIOS_SCRATCH_7_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_8 0x8054 +#define regBIF_BX1_BIOS_SCRATCH_8_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_9 0x8055 +#define regBIF_BX1_BIOS_SCRATCH_9_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_10 0x8056 +#define regBIF_BX1_BIOS_SCRATCH_10_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_11 0x8057 +#define regBIF_BX1_BIOS_SCRATCH_11_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_12 0x8058 +#define regBIF_BX1_BIOS_SCRATCH_12_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_13 0x8059 +#define regBIF_BX1_BIOS_SCRATCH_13_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_14 0x805a +#define regBIF_BX1_BIOS_SCRATCH_14_BASE_IDX 8 +#define regBIF_BX1_BIOS_SCRATCH_15 0x805b +#define regBIF_BX1_BIOS_SCRATCH_15_BASE_IDX 8 +#define regBIF_BX1_BIF_RLC_INTR_CNTL 0x8060 +#define regBIF_BX1_BIF_RLC_INTR_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_VCE_INTR_CNTL 0x8061 +#define regBIF_BX1_BIF_VCE_INTR_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_UVD_INTR_CNTL 0x8062 +#define regBIF_BX1_BIF_UVD_INTR_CNTL_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0 0x8080 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0 0x8081 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1 0x8082 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1 0x8083 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2 0x8084 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2 0x8085 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3 0x8086 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3 0x8087 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4 0x8088 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4 0x8089 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5 0x808a +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5 0x808b +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6 0x808c +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6 0x808d +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7 0x808e +#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7 0x808f +#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_CNTL 0x8090 +#define regBIF_BX1_GFX_MMIOREG_CAM_CNTL_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL 0x8091 +#define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL 0x8092 +#define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 8 +#define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x8093 +#define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_0 0x8094 +#define regBIF_BX1_DRIVER_SCRATCH_0_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_1 0x8095 +#define regBIF_BX1_DRIVER_SCRATCH_1_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_2 0x8096 +#define regBIF_BX1_DRIVER_SCRATCH_2_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_3 0x8097 +#define regBIF_BX1_DRIVER_SCRATCH_3_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_4 0x8098 +#define regBIF_BX1_DRIVER_SCRATCH_4_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_5 0x8099 +#define regBIF_BX1_DRIVER_SCRATCH_5_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_6 0x809a +#define regBIF_BX1_DRIVER_SCRATCH_6_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_7 0x809b +#define regBIF_BX1_DRIVER_SCRATCH_7_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_8 0x809c +#define regBIF_BX1_DRIVER_SCRATCH_8_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_9 0x809d +#define regBIF_BX1_DRIVER_SCRATCH_9_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_10 0x809e +#define regBIF_BX1_DRIVER_SCRATCH_10_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_11 0x809f +#define regBIF_BX1_DRIVER_SCRATCH_11_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_12 0x80a0 +#define regBIF_BX1_DRIVER_SCRATCH_12_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_13 0x80a1 +#define regBIF_BX1_DRIVER_SCRATCH_13_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_14 0x80a2 +#define regBIF_BX1_DRIVER_SCRATCH_14_BASE_IDX 8 +#define regBIF_BX1_DRIVER_SCRATCH_15 0x80a3 +#define regBIF_BX1_DRIVER_SCRATCH_15_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_0 0x80a4 +#define regBIF_BX1_FW_SCRATCH_0_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_1 0x80a5 +#define regBIF_BX1_FW_SCRATCH_1_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_2 0x80a6 +#define regBIF_BX1_FW_SCRATCH_2_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_3 0x80a7 +#define regBIF_BX1_FW_SCRATCH_3_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_4 0x80a8 +#define regBIF_BX1_FW_SCRATCH_4_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_5 0x80a9 +#define regBIF_BX1_FW_SCRATCH_5_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_6 0x80aa +#define regBIF_BX1_FW_SCRATCH_6_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_7 0x80ab +#define regBIF_BX1_FW_SCRATCH_7_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_8 0x80ac +#define regBIF_BX1_FW_SCRATCH_8_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_9 0x80ad +#define regBIF_BX1_FW_SCRATCH_9_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_10 0x80ae +#define regBIF_BX1_FW_SCRATCH_10_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_11 0x80af +#define regBIF_BX1_FW_SCRATCH_11_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_12 0x80b0 +#define regBIF_BX1_FW_SCRATCH_12_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_13 0x80b1 +#define regBIF_BX1_FW_SCRATCH_13_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_14 0x80b2 +#define regBIF_BX1_FW_SCRATCH_14_BASE_IDX 8 +#define regBIF_BX1_FW_SCRATCH_15 0x80b3 +#define regBIF_BX1_FW_SCRATCH_15_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_4 0x80b4 +#define regBIF_BX1_SBIOS_SCRATCH_4_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_5 0x80b5 +#define regBIF_BX1_SBIOS_SCRATCH_5_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_6 0x80b6 +#define regBIF_BX1_SBIOS_SCRATCH_6_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_7 0x80b7 +#define regBIF_BX1_SBIOS_SCRATCH_7_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_8 0x80b8 +#define regBIF_BX1_SBIOS_SCRATCH_8_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_9 0x80b9 +#define regBIF_BX1_SBIOS_SCRATCH_9_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_10 0x80ba +#define regBIF_BX1_SBIOS_SCRATCH_10_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_11 0x80bb +#define regBIF_BX1_SBIOS_SCRATCH_11_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_12 0x80bc +#define regBIF_BX1_SBIOS_SCRATCH_12_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_13 0x80bd +#define regBIF_BX1_SBIOS_SCRATCH_13_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_14 0x80be +#define regBIF_BX1_SBIOS_SCRATCH_14_BASE_IDX 8 +#define regBIF_BX1_SBIOS_SCRATCH_15 0x80bf +#define regBIF_BX1_SBIOS_SCRATCH_15_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_bx_pf_SYSPFVFDEC +// base address: 0x10120000 +#define regBIF_BX_PF1_MM_INDEX 0x8000 +#define regBIF_BX_PF1_MM_INDEX_BASE_IDX 8 +#define regBIF_BX_PF1_MM_DATA 0x8001 +#define regBIF_BX_PF1_MM_DATA_BASE_IDX 8 +#define regBIF_BX_PF1_MM_INDEX_HI 0x8006 +#define regBIF_BX_PF1_MM_INDEX_HI_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_bx_BIFDEC1 +// base address: 0x10120000 +#define regBIF_BX1_CC_BIF_BX_STRAP0 0x8e02 +#define regBIF_BX1_CC_BIF_BX_STRAP0_BASE_IDX 8 +#define regBIF_BX1_CC_BIF_BX_PINSTRAP0 0x8e04 +#define regBIF_BX1_CC_BIF_BX_PINSTRAP0_BASE_IDX 8 +#define regBIF_BX1_BIF_MM_INDACCESS_CNTL 0x8e06 +#define regBIF_BX1_BIF_MM_INDACCESS_CNTL_BASE_IDX 8 +#define regBIF_BX1_BUS_CNTL 0x8e07 +#define regBIF_BX1_BUS_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_SCRATCH0 0x8e08 +#define regBIF_BX1_BIF_SCRATCH0_BASE_IDX 8 +#define regBIF_BX1_BIF_SCRATCH1 0x8e09 +#define regBIF_BX1_BIF_SCRATCH1_BASE_IDX 8 +#define regBIF_BX1_BX_RESET_EN 0x8e0d +#define regBIF_BX1_BX_RESET_EN_BASE_IDX 8 +#define regBIF_BX1_MM_CFGREGS_CNTL 0x8e0e +#define regBIF_BX1_MM_CFGREGS_CNTL_BASE_IDX 8 +#define regBIF_BX1_BX_RESET_CNTL 0x8e10 +#define regBIF_BX1_BX_RESET_CNTL_BASE_IDX 8 +#define regBIF_BX1_INTERRUPT_CNTL 0x8e11 +#define regBIF_BX1_INTERRUPT_CNTL_BASE_IDX 8 +#define regBIF_BX1_INTERRUPT_CNTL2 0x8e12 +#define regBIF_BX1_INTERRUPT_CNTL2_BASE_IDX 8 +#define regBIF_BX1_CLKREQB_PAD_CNTL 0x8e18 +#define regBIF_BX1_CLKREQB_PAD_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_FEATURES_CONTROL_MISC 0x8e1b +#define regBIF_BX1_BIF_FEATURES_CONTROL_MISC_BASE_IDX 8 +#define regBIF_BX1_HDP_ATOMIC_CONTROL_MISC 0x8e1c +#define regBIF_BX1_HDP_ATOMIC_CONTROL_MISC_BASE_IDX 8 +#define regBIF_BX1_BIF_DOORBELL_CNTL 0x8e1d +#define regBIF_BX1_BIF_DOORBELL_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_DOORBELL_INT_CNTL 0x8e1e +#define regBIF_BX1_BIF_DOORBELL_INT_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_FB_EN 0x8e20 +#define regBIF_BX1_BIF_FB_EN_BASE_IDX 8 +#define regBIF_BX1_BIF_INTR_CNTL 0x8e21 +#define regBIF_BX1_BIF_INTR_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_MST_TRANS_PENDING_VF 0x8e29 +#define regBIF_BX1_BIF_MST_TRANS_PENDING_VF_BASE_IDX 8 +#define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF 0x8e2a +#define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF_BASE_IDX 8 +#define regBIF_BX1_BACO_CNTL 0x8e2b +#define regBIF_BX1_BACO_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_BACO_EXIT_TIME0 0x8e2c +#define regBIF_BX1_BIF_BACO_EXIT_TIME0_BASE_IDX 8 +#define regBIF_BX1_BIF_BACO_EXIT_TIMER1 0x8e2d +#define regBIF_BX1_BIF_BACO_EXIT_TIMER1_BASE_IDX 8 +#define regBIF_BX1_BIF_BACO_EXIT_TIMER2 0x8e2e +#define regBIF_BX1_BIF_BACO_EXIT_TIMER2_BASE_IDX 8 +#define regBIF_BX1_BIF_BACO_EXIT_TIMER3 0x8e2f +#define regBIF_BX1_BIF_BACO_EXIT_TIMER3_BASE_IDX 8 +#define regBIF_BX1_BIF_BACO_EXIT_TIMER4 0x8e30 +#define regBIF_BX1_BIF_BACO_EXIT_TIMER4_BASE_IDX 8 +#define regBIF_BX1_MEM_TYPE_CNTL 0x8e31 +#define regBIF_BX1_MEM_TYPE_CNTL_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL 0x8e33 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_0 0x8e34 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_0_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_1 0x8e35 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_1_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_2 0x8e36 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_2_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_3 0x8e37 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_3_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_4 0x8e38 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_4_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_5 0x8e39 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_5_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_6 0x8e3a +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_6_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_7 0x8e3b +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_7_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_8 0x8e3c +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_8_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_9 0x8e3d +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_9_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_10 0x8e3e +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_10_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_11 0x8e3f +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_11_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_12 0x8e40 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_12_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_13 0x8e41 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_13_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_14 0x8e42 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_14_BASE_IDX 8 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_15 0x8e43 +#define regBIF_BX1_NBIF_GFX_ADDR_LUT_15_BASE_IDX 8 +#define regBIF_BX1_VF_REGWR_EN 0x8e44 +#define regBIF_BX1_VF_REGWR_EN_BASE_IDX 8 +#define regBIF_BX1_VF_DOORBELL_EN 0x8e45 +#define regBIF_BX1_VF_DOORBELL_EN_BASE_IDX 8 +#define regBIF_BX1_VF_FB_EN 0x8e46 +#define regBIF_BX1_VF_FB_EN_BASE_IDX 8 +#define regBIF_BX1_VF_REGWR_STATUS 0x8e47 +#define regBIF_BX1_VF_REGWR_STATUS_BASE_IDX 8 +#define regBIF_BX1_VF_DOORBELL_STATUS 0x8e48 +#define regBIF_BX1_VF_DOORBELL_STATUS_BASE_IDX 8 +#define regBIF_BX1_VF_FB_STATUS 0x8e49 +#define regBIF_BX1_VF_FB_STATUS_BASE_IDX 8 +#define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL 0x8e4d +#define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 8 +#define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL 0x8e4e +#define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_RB_CNTL 0x8e4f +#define regBIF_BX1_BIF_RB_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_RB_BASE 0x8e50 +#define regBIF_BX1_BIF_RB_BASE_BASE_IDX 8 +#define regBIF_BX1_BIF_RB_RPTR 0x8e51 +#define regBIF_BX1_BIF_RB_RPTR_BASE_IDX 8 +#define regBIF_BX1_BIF_RB_WPTR 0x8e52 +#define regBIF_BX1_BIF_RB_WPTR_BASE_IDX 8 +#define regBIF_BX1_BIF_RB_WPTR_ADDR_HI 0x8e53 +#define regBIF_BX1_BIF_RB_WPTR_ADDR_HI_BASE_IDX 8 +#define regBIF_BX1_BIF_RB_WPTR_ADDR_LO 0x8e54 +#define regBIF_BX1_BIF_RB_WPTR_ADDR_LO_BASE_IDX 8 +#define regBIF_BX1_MAILBOX_INDEX 0x8e55 +#define regBIF_BX1_MAILBOX_INDEX_BASE_IDX 8 +#define regBIF_BX1_BIF_MP1_INTR_CTRL 0x8e62 +#define regBIF_BX1_BIF_MP1_INTR_CTRL_BASE_IDX 8 +#define regBIF_BX1_BIF_PERSTB_PAD_CNTL 0x8e66 +#define regBIF_BX1_BIF_PERSTB_PAD_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_PX_EN_PAD_CNTL 0x8e67 +#define regBIF_BX1_BIF_PX_EN_PAD_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL 0x8e68 +#define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_CLKREQB_PAD_CNTL 0x8e69 +#define regBIF_BX1_BIF_CLKREQB_PAD_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_PWRBRK_PAD_CNTL 0x8e6a +#define regBIF_BX1_BIF_PWRBRK_PAD_CNTL_BASE_IDX 8 +#define regBIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE 0x8e6b +#define regBIF_BX1_BIF_VCN0_GPUIOV_CFG_SIZE_BASE_IDX 8 +#define regBIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE 0x8e6c +#define regBIF_BX1_BIF_VCN1_GPUIOV_CFG_SIZE_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 +// base address: 0x10120000 +#define regBIF_BX_PF1_BIF_BME_STATUS 0x8e0b +#define regBIF_BX_PF1_BIF_BME_STATUS_BASE_IDX 8 +#define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG 0x8e0c +#define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 8 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x8e13 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 8 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x8e14 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 8 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x8e15 +#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 8 +#define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x8e16 +#define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 8 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x8e17 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 8 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x8e19 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 8 +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x8e1a +#define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 8 +#define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ 0x8e26 +#define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ_BASE_IDX 8 +#define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE 0x8e27 +#define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE_BASE_IDX 8 +#define regBIF_BX_PF1_BIF_TRANS_PENDING 0x8e28 +#define regBIF_BX_PF1_BIF_TRANS_PENDING_BASE_IDX 8 +#define regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS 0x8e32 +#define regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0 0x8e56 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1 0x8e57 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2 0x8e58 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3 0x8e59 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0 0x8e5a +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1 0x8e5b +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2 0x8e5c +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3 0x8e5d +#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_CONTROL 0x8e5e +#define regBIF_BX_PF1_MAILBOX_CONTROL_BASE_IDX 8 +#define regBIF_BX_PF1_MAILBOX_INT_CNTL 0x8e5f +#define regBIF_BX_PF1_MAILBOX_INT_CNTL_BASE_IDX 8 +#define regBIF_BX_PF1_BIF_VMHV_MAILBOX 0x8e60 +#define regBIF_BX_PF1_BIF_VMHV_MAILBOX_BASE_IDX 8 +#define regBIF_BX_PF1_PARTITION_COMPUTE_CAP 0x8e81 +#define regBIF_BX_PF1_PARTITION_COMPUTE_CAP_BASE_IDX 8 +#define regBIF_BX_PF1_PARTITION_MEM_CAP 0x8e82 +#define regBIF_BX_PF1_PARTITION_MEM_CAP_BASE_IDX 8 +#define regBIF_BX_PF1_PARTITION_COMPUTE_STATUS 0x8e83 +#define regBIF_BX_PF1_PARTITION_COMPUTE_STATUS_BASE_IDX 8 +#define regBIF_BX_PF1_PARTITION_MEM_STATUS 0x8e84 +#define regBIF_BX_PF1_PARTITION_MEM_STATUS_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_rcc_strap_BIFDEC1:1 +// base address: 0x10120000 +#define regRCC_STRAP2_RCC_BIF_STRAP0 0x8d20 +#define regRCC_STRAP2_RCC_BIF_STRAP0_BASE_IDX 8 +#define regRCC_STRAP2_RCC_BIF_STRAP1 0x8d21 +#define regRCC_STRAP2_RCC_BIF_STRAP1_BASE_IDX 8 +#define regRCC_STRAP2_RCC_BIF_STRAP2 0x8d22 +#define regRCC_STRAP2_RCC_BIF_STRAP2_BASE_IDX 8 +#define regRCC_STRAP2_RCC_BIF_STRAP3 0x8d23 +#define regRCC_STRAP2_RCC_BIF_STRAP3_BASE_IDX 8 +#define regRCC_STRAP2_RCC_BIF_STRAP4 0x8d24 +#define regRCC_STRAP2_RCC_BIF_STRAP4_BASE_IDX 8 +#define regRCC_STRAP2_RCC_BIF_STRAP5 0x8d25 +#define regRCC_STRAP2_RCC_BIF_STRAP5_BASE_IDX 8 +#define regRCC_STRAP2_RCC_BIF_STRAP6 0x8d26 +#define regRCC_STRAP2_RCC_BIF_STRAP6_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0 0x8d27 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1 0x8d28 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP10 0x8d29 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP10_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP11 0x8d2a +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP11_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP12 0x8d2b +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP12_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP13 0x8d2c +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP13_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP14 0x8d2d +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP14_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2 0x8d2e +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3 0x8d2f +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4 0x8d30 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5 0x8d31 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6 0x8d32 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7 0x8d33 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8 0x8d34 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9 0x8d35 +#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0 0x8d36 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1 0x8d37 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13 0x8d38 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14 0x8d39 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15 0x8d3a +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16 0x8d3b +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17 0x8d3c +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18 0x8d3d +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2 0x8d3e +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP26 0x8d3f +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP26_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3 0x8d40 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4 0x8d41 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5 0x8d42 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8 0x8d44 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9 0x8d45 +#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0 0x8d46 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2 0x8d52 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20 0x8d53 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21 0x8d54 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP22 0x8d55 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP22_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23 0x8d56 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24 0x8d57 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP25 0x8d58 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP25_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3 0x8d59 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4 0x8d5a +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5 0x8d5b +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6 0x8d5c +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6_BASE_IDX 8 +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7 0x8d5d +#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_gdc_hst_sion_SIONDEC +// base address: 0x1400000 +#define regS2A_DOORBELL_ENTRY_0_CTRL 0x7a80 +#define regS2A_DOORBELL_ENTRY_0_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_1_CTRL 0x7a81 +#define regS2A_DOORBELL_ENTRY_1_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_2_CTRL 0x7a82 +#define regS2A_DOORBELL_ENTRY_2_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_3_CTRL 0x7a83 +#define regS2A_DOORBELL_ENTRY_3_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_4_CTRL 0x7a84 +#define regS2A_DOORBELL_ENTRY_4_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_5_CTRL 0x7a85 +#define regS2A_DOORBELL_ENTRY_5_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_6_CTRL 0x7a86 +#define regS2A_DOORBELL_ENTRY_6_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_7_CTRL 0x7a87 +#define regS2A_DOORBELL_ENTRY_7_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_8_CTRL 0x7a88 +#define regS2A_DOORBELL_ENTRY_8_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_9_CTRL 0x7a89 +#define regS2A_DOORBELL_ENTRY_9_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_10_CTRL 0x7a8a +#define regS2A_DOORBELL_ENTRY_10_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_11_CTRL 0x7a8b +#define regS2A_DOORBELL_ENTRY_11_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_12_CTRL 0x7a8c +#define regS2A_DOORBELL_ENTRY_12_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_13_CTRL 0x7a8d +#define regS2A_DOORBELL_ENTRY_13_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_14_CTRL 0x7a8e +#define regS2A_DOORBELL_ENTRY_14_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_ENTRY_15_CTRL 0x7a8f +#define regS2A_DOORBELL_ENTRY_15_CTRL_BASE_IDX 5 +#define regS2A_DOORBELL_COMMON_CTRL_REG 0x7a90 +#define regS2A_DOORBELL_COMMON_CTRL_REG_BASE_IDX 5 + + +// addressBlock: aid_nbio_nbif0_gdc_GDCDEC +// base address: 0x1400000 +#define regGDC1_A2S_CNTL_CL0 0x0ea0 +#define regGDC1_A2S_CNTL_CL0_BASE_IDX 5 +#define regGDC1_A2S_CNTL_CL1 0x0ea1 +#define regGDC1_A2S_CNTL_CL1_BASE_IDX 5 +#define regGDC1_A2S_CNTL3_CL0 0x0eb8 +#define regGDC1_A2S_CNTL3_CL0_BASE_IDX 5 +#define regGDC1_A2S_CNTL3_CL1 0x0eb9 +#define regGDC1_A2S_CNTL3_CL1_BASE_IDX 5 +#define regGDC1_A2S_CNTL_SW0 0x0ed0 +#define regGDC1_A2S_CNTL_SW0_BASE_IDX 5 +#define regGDC1_A2S_CNTL_SW1 0x0ed1 +#define regGDC1_A2S_CNTL_SW1_BASE_IDX 5 +#define regGDC1_A2S_CNTL_SW2 0x0ed2 +#define regGDC1_A2S_CNTL_SW2_BASE_IDX 5 +#define regGDC1_A2S_TAG_ALLOC_0 0x0edd +#define regGDC1_A2S_TAG_ALLOC_0_BASE_IDX 5 +#define regGDC1_A2S_TAG_ALLOC_1 0x0ede +#define regGDC1_A2S_TAG_ALLOC_1_BASE_IDX 5 +#define regGDC1_A2S_MISC_CNTL 0x0ee1 +#define regGDC1_A2S_MISC_CNTL_BASE_IDX 5 +#define regGDC1_SHUB_REGS_IF_CTL 0x0ee3 +#define regGDC1_SHUB_REGS_IF_CTL_BASE_IDX 5 +#define regGDC1_NGDC_MGCG_CTRL 0x0eea +#define regGDC1_NGDC_MGCG_CTRL_BASE_IDX 5 +#define regGDC1_NGDC_RESERVED_0 0x0eeb +#define regGDC1_NGDC_RESERVED_0_BASE_IDX 5 +#define regGDC1_NGDC_RESERVED_1 0x0eec +#define regGDC1_NGDC_RESERVED_1_BASE_IDX 5 +#define regGDC1_NBIF_GFX_DOORBELL_STATUS 0x0eef +#define regGDC1_NBIF_GFX_DOORBELL_STATUS_BASE_IDX 5 +#define regGDC1_ATDMA_MISC_CNTL 0x0efd +#define regGDC1_ATDMA_MISC_CNTL_BASE_IDX 5 +#define regGDC1_S2A_MISC_CNTL 0x0eff +#define regGDC1_S2A_MISC_CNTL_BASE_IDX 5 +#define regGDC1_NGDC_EARLY_WAKEUP_CTRL 0x0f01 +#define regGDC1_NGDC_EARLY_WAKEUP_CTRL_BASE_IDX 5 +#define regGDC1_NGDC_PG_MISC_CTRL 0x0f18 +#define regGDC1_NGDC_PG_MISC_CTRL_BASE_IDX 5 +#define regGDC1_NGDC_PGMST_CTRL 0x0f19 +#define regGDC1_NGDC_PGMST_CTRL_BASE_IDX 5 +#define regGDC1_NGDC_PGSLV_CTRL 0x0f1a +#define regGDC1_NGDC_PGSLV_CTRL_BASE_IDX 5 + + +// addressBlock: aid_nbio_nbif0_gdc_sec_GDCSEC_DEC +// base address: 0x1400000 +#define regXCC_DOORBELL_FENCE 0x740c +#define regXCC_DOORBELL_FENCE_BASE_IDX 5 + + +// addressBlock: aid_nbio_nbif0_gdc_rst_GDCRST_DEC +// base address: 0x1400000 +#define regSHUB_PF_FLR_RST 0x7c00 +#define regSHUB_PF_FLR_RST_BASE_IDX 5 +#define regSHUB_GFX_DRV_VPU_RST 0x7c01 +#define regSHUB_GFX_DRV_VPU_RST_BASE_IDX 5 +#define regSHUB_LINK_RESET 0x7c02 +#define regSHUB_LINK_RESET_BASE_IDX 5 +#define regSHUB_HARD_RST_CTRL 0x7c10 +#define regSHUB_HARD_RST_CTRL_BASE_IDX 5 +#define regSHUB_SOFT_RST_CTRL 0x7c11 +#define regSHUB_SOFT_RST_CTRL_BASE_IDX 5 +#define regSHUB_SDP_PORT_RST 0x7c12 +#define regSHUB_SDP_PORT_RST_BASE_IDX 5 +#define regSHUB_RST_MISC_TRL 0x7c13 +#define regSHUB_RST_MISC_TRL_BASE_IDX 5 + + +// addressBlock: aid_nbio_nbif0_syshub_mmreg_syshubdirect +// base address: 0x1400000 +#define regHST_CLK0_SW0_CL0_CNTL 0x4140 +#define regHST_CLK0_SW0_CL0_CNTL_BASE_IDX 5 +#define regHST_CLK0_SW1_CL0_CNTL 0x4160 +#define regHST_CLK0_SW1_CL0_CNTL_BASE_IDX 5 +#define regHST_CLK0_SW1_CL1_CNTL 0x4161 +#define regHST_CLK0_SW1_CL1_CNTL_BASE_IDX 5 +#define regHST_CLK0_SW1_CL2_CNTL 0x4162 +#define regHST_CLK0_SW1_CL2_CNTL_BASE_IDX 5 +#define regDMA_CLK0_SW0_CL0_CNTL 0x4240 +#define regDMA_CLK0_SW0_CL0_CNTL_BASE_IDX 5 +#define regDMA_CLK0_SW0_CL1_CNTL 0x4241 +#define regDMA_CLK0_SW0_CL1_CNTL_BASE_IDX 5 +#define regNIC400_1_ASIB_0_FN_MOD 0xc042 +#define regNIC400_1_ASIB_0_FN_MOD_BASE_IDX 5 +#define regNIC400_1_IB_0_FN_MOD 0xfc42 +#define regNIC400_1_IB_0_FN_MOD_BASE_IDX 5 +#define regNIC400_2_ASIB_0_FN_MOD 0x10c42 +#define regNIC400_2_ASIB_0_FN_MOD_BASE_IDX 5 +#define regNIC400_2_ASIB_0_QOS_CNTL 0x10c43 +#define regNIC400_2_ASIB_0_QOS_CNTL_BASE_IDX 5 +#define regNIC400_2_ASIB_0_MAX_OT 0x10c44 +#define regNIC400_2_ASIB_0_MAX_OT_BASE_IDX 5 +#define regNIC400_2_ASIB_0_MAX_COMB_OT 0x10c45 +#define regNIC400_2_ASIB_0_MAX_COMB_OT_BASE_IDX 5 +#define regNIC400_2_ASIB_0_AW_P 0x10c46 +#define regNIC400_2_ASIB_0_AW_P_BASE_IDX 5 +#define regNIC400_2_ASIB_0_AW_B 0x10c47 +#define regNIC400_2_ASIB_0_AW_B_BASE_IDX 5 +#define regNIC400_2_ASIB_0_AW_R 0x10c48 +#define regNIC400_2_ASIB_0_AW_R_BASE_IDX 5 +#define regNIC400_2_ASIB_0_AR_P 0x10c49 +#define regNIC400_2_ASIB_0_AR_P_BASE_IDX 5 +#define regNIC400_2_ASIB_0_AR_B 0x10c4a +#define regNIC400_2_ASIB_0_AR_B_BASE_IDX 5 +#define regNIC400_2_ASIB_0_AR_R 0x10c4b +#define regNIC400_2_ASIB_0_AR_R_BASE_IDX 5 +#define regNIC400_2_ASIB_0_TARGET_FC 0x10c4c +#define regNIC400_2_ASIB_0_TARGET_FC_BASE_IDX 5 +#define regNIC400_2_ASIB_0_KI_FC 0x10c4d +#define regNIC400_2_ASIB_0_KI_FC_BASE_IDX 5 +#define regNIC400_2_ASIB_0_QOS_RANGE 0x10c4e +#define regNIC400_2_ASIB_0_QOS_RANGE_BASE_IDX 5 +#define regNIC400_2_ASIB_1_FN_MOD 0x11042 +#define regNIC400_2_ASIB_1_FN_MOD_BASE_IDX 5 +#define regNIC400_2_ASIB_1_QOS_CNTL 0x11043 +#define regNIC400_2_ASIB_1_QOS_CNTL_BASE_IDX 5 +#define regNIC400_2_ASIB_1_MAX_OT 0x11044 +#define regNIC400_2_ASIB_1_MAX_OT_BASE_IDX 5 +#define regNIC400_2_ASIB_1_MAX_COMB_OT 0x11045 +#define regNIC400_2_ASIB_1_MAX_COMB_OT_BASE_IDX 5 +#define regNIC400_2_ASIB_1_AW_P 0x11046 +#define regNIC400_2_ASIB_1_AW_P_BASE_IDX 5 +#define regNIC400_2_ASIB_1_AW_B 0x11047 +#define regNIC400_2_ASIB_1_AW_B_BASE_IDX 5 +#define regNIC400_2_ASIB_1_AW_R 0x11048 +#define regNIC400_2_ASIB_1_AW_R_BASE_IDX 5 +#define regNIC400_2_ASIB_1_AR_P 0x11049 +#define regNIC400_2_ASIB_1_AR_P_BASE_IDX 5 +#define regNIC400_2_ASIB_1_AR_B 0x1104a +#define regNIC400_2_ASIB_1_AR_B_BASE_IDX 5 +#define regNIC400_2_ASIB_1_AR_R 0x1104b +#define regNIC400_2_ASIB_1_AR_R_BASE_IDX 5 +#define regNIC400_2_ASIB_1_TARGET_FC 0x1104c +#define regNIC400_2_ASIB_1_TARGET_FC_BASE_IDX 5 +#define regNIC400_2_ASIB_1_KI_FC 0x1104d +#define regNIC400_2_ASIB_1_KI_FC_BASE_IDX 5 +#define regNIC400_2_ASIB_1_QOS_RANGE 0x1104e +#define regNIC400_2_ASIB_1_QOS_RANGE_BASE_IDX 5 +#define regNIC400_2_IB_0_FN_MOD 0x13c42 +#define regNIC400_2_IB_0_FN_MOD_BASE_IDX 5 + + +// addressBlock: aid_nbio_iohub_nb_nbcfg_nb_cfgdec +// base address: 0x13b00000 +#define regNB_NBCFG0_NBCFG_SCRATCH_4 0xe8001e +#define regNB_NBCFG0_NBCFG_SCRATCH_4_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_misc_misc_cfgdec +// base address: 0x13b10000 +#define regNB_CNTL 0xe84000 +#define regNB_CNTL_BASE_IDX 8 +#define regNB_SPARE1 0xe84003 +#define regNB_SPARE1_BASE_IDX 8 +#define regNB_SPARE2 0xe84004 +#define regNB_SPARE2_BASE_IDX 8 +#define regNB_REVID 0xe84005 +#define regNB_REVID_BASE_IDX 8 +#define regNBIO_LCLK_DS_MASK 0xe84009 +#define regNBIO_LCLK_DS_MASK_BASE_IDX 8 +#define regNB_BUS_NUM_CNTL 0xe84011 +#define regNB_BUS_NUM_CNTL_BASE_IDX 8 +#define regNB_MMIOBASE 0xe84017 +#define regNB_MMIOBASE_BASE_IDX 8 +#define regNB_MMIOLIMIT 0xe84018 +#define regNB_MMIOLIMIT_BASE_IDX 8 +#define regNB_LOWER_TOP_OF_DRAM2 0xe84019 +#define regNB_LOWER_TOP_OF_DRAM2_BASE_IDX 8 +#define regNB_UPPER_TOP_OF_DRAM2 0xe8401a +#define regNB_UPPER_TOP_OF_DRAM2_BASE_IDX 8 +#define regNB_LOWER_DRAM2_BASE 0xe8401b +#define regNB_LOWER_DRAM2_BASE_BASE_IDX 8 +#define regNB_UPPER_DRAM2_BASE 0xe8401c +#define regNB_UPPER_DRAM2_BASE_BASE_IDX 8 +#define regSB_LOCATION 0xe8401f +#define regSB_LOCATION_BASE_IDX 8 +#define regSW_US_LOCATION 0xe84020 +#define regSW_US_LOCATION_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr0 0xe8402e +#define regNB_PROG_DEVICE_REMAP_PBr0_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr1 0xe8402f +#define regNB_PROG_DEVICE_REMAP_PBr1_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr2 0xe84030 +#define regNB_PROG_DEVICE_REMAP_PBr2_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr3 0xe84031 +#define regNB_PROG_DEVICE_REMAP_PBr3_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr4 0xe84032 +#define regNB_PROG_DEVICE_REMAP_PBr4_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr5 0xe84033 +#define regNB_PROG_DEVICE_REMAP_PBr5_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr6 0xe84034 +#define regNB_PROG_DEVICE_REMAP_PBr6_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr7 0xe84035 +#define regNB_PROG_DEVICE_REMAP_PBr7_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr8 0xe84036 +#define regNB_PROG_DEVICE_REMAP_PBr8_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr10 0xe84038 +#define regNB_PROG_DEVICE_REMAP_PBr10_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr11 0xe84039 +#define regNB_PROG_DEVICE_REMAP_PBr11_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr12 0xe8403a +#define regNB_PROG_DEVICE_REMAP_PBr12_BASE_IDX 8 +#define regNB_PROG_DEVICE_REMAP_PBr13 0xe8403b +#define regNB_PROG_DEVICE_REMAP_PBr13_BASE_IDX 8 +#define regSW_NMI_CNTL 0xe84042 +#define regSW_NMI_CNTL_BASE_IDX 8 +#define regSW_SMI_CNTL 0xe84043 +#define regSW_SMI_CNTL_BASE_IDX 8 +#define regSW_SCI_CNTL 0xe84044 +#define regSW_SCI_CNTL_BASE_IDX 8 +#define regAPML_SW_STATUS 0xe84045 +#define regAPML_SW_STATUS_BASE_IDX 8 +#define regSW_GIC_SPI_CNTL 0xe84047 +#define regSW_GIC_SPI_CNTL_BASE_IDX 8 +#define regSW_SYNCFLOOD_CNTL 0xe84049 +#define regSW_SYNCFLOOD_CNTL_BASE_IDX 8 +#define regNB_TOP_OF_DRAM3 0xe8404e +#define regNB_TOP_OF_DRAM3_BASE_IDX 8 +#define regCAM_CONTROL 0xe84052 +#define regCAM_CONTROL_BASE_IDX 8 +#define regCAM_TARGET_INDEX_ADDR_BOTTOM 0xe84053 +#define regCAM_TARGET_INDEX_ADDR_BOTTOM_BASE_IDX 8 +#define regCAM_TARGET_INDEX_ADDR_TOP 0xe84054 +#define regCAM_TARGET_INDEX_ADDR_TOP_BASE_IDX 8 +#define regCAM_TARGET_INDEX_DATA 0xe84055 +#define regCAM_TARGET_INDEX_DATA_BASE_IDX 8 +#define regCAM_TARGET_INDEX_DATA_MASK 0xe84056 +#define regCAM_TARGET_INDEX_DATA_MASK_BASE_IDX 8 +#define regCAM_TARGET_DATA_ADDR_BOTTOM 0xe84057 +#define regCAM_TARGET_DATA_ADDR_BOTTOM_BASE_IDX 8 +#define regCAM_TARGET_DATA_ADDR_TOP 0xe84059 +#define regCAM_TARGET_DATA_ADDR_TOP_BASE_IDX 8 +#define regCAM_TARGET_DATA 0xe8405a +#define regCAM_TARGET_DATA_BASE_IDX 8 +#define regCAM_TARGET_DATA_MASK 0xe8405b +#define regCAM_TARGET_DATA_MASK_BASE_IDX 8 +#define regP_DMA_DROPPED_LOG_LOWER 0xe84060 +#define regP_DMA_DROPPED_LOG_LOWER_BASE_IDX 8 +#define regP_DMA_DROPPED_LOG_UPPER 0xe84061 +#define regP_DMA_DROPPED_LOG_UPPER_BASE_IDX 8 +#define regNP_DMA_DROPPED_LOG_LOWER 0xe84062 +#define regNP_DMA_DROPPED_LOG_LOWER_BASE_IDX 8 +#define regNP_DMA_DROPPED_LOG_UPPER 0xe84063 +#define regNP_DMA_DROPPED_LOG_UPPER_BASE_IDX 8 +#define regPCIE_VDM_NODE0_CTRL4 0xe84064 +#define regPCIE_VDM_NODE0_CTRL4_BASE_IDX 8 +#define regPCIE_VDM_CNTL2 0xe8408c +#define regPCIE_VDM_CNTL2_BASE_IDX 8 +#define regPCIE_VDM_CNTL3 0xe8408d +#define regPCIE_VDM_CNTL3_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT0_0 0xe84090 +#define regSTALL_CONTROL_XBARPORT0_0_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT0_1 0xe84091 +#define regSTALL_CONTROL_XBARPORT0_1_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT1_0 0xe84093 +#define regSTALL_CONTROL_XBARPORT1_0_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT1_1 0xe84094 +#define regSTALL_CONTROL_XBARPORT1_1_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT2_0 0xe84096 +#define regSTALL_CONTROL_XBARPORT2_0_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT2_1 0xe84097 +#define regSTALL_CONTROL_XBARPORT2_1_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT3_0 0xe84099 +#define regSTALL_CONTROL_XBARPORT3_0_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT3_1 0xe8409a +#define regSTALL_CONTROL_XBARPORT3_1_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT4_0 0xe8409c +#define regSTALL_CONTROL_XBARPORT4_0_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT4_1 0xe8409d +#define regSTALL_CONTROL_XBARPORT4_1_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT5_0 0xe8409f +#define regSTALL_CONTROL_XBARPORT5_0_BASE_IDX 8 +#define regSTALL_CONTROL_XBARPORT5_1 0xe840a0 +#define regSTALL_CONTROL_XBARPORT5_1_BASE_IDX 8 +#define regNB_DRAM3_BASE 0xe840b1 +#define regNB_DRAM3_BASE_BASE_IDX 8 +#define regPSP_BASE_ADDR_LO 0xe840b8 +#define regPSP_BASE_ADDR_LO_BASE_IDX 8 +#define regPSP_BASE_ADDR_HI 0xe840b9 +#define regPSP_BASE_ADDR_HI_BASE_IDX 8 +#define regSMU_BASE_ADDR_LO 0xe840ba +#define regSMU_BASE_ADDR_LO_BASE_IDX 8 +#define regSMU_BASE_ADDR_HI 0xe840bb +#define regSMU_BASE_ADDR_HI_BASE_IDX 8 +#define regSCRATCH_4 0xe840fc +#define regSCRATCH_4_BASE_IDX 8 +#define regSCRATCH_5 0xe840fd +#define regSCRATCH_5_BASE_IDX 8 +#define regSMU_BLOCK_CPU 0xe840fe +#define regSMU_BLOCK_CPU_BASE_IDX 8 +#define regSMU_BLOCK_CPU_STATUS 0xe840ff +#define regSMU_BLOCK_CPU_STATUS_BASE_IDX 8 +#define regTRAP_STATUS 0xe84100 +#define regTRAP_STATUS_BASE_IDX 8 +#define regTRAP_REQUEST0 0xe84101 +#define regTRAP_REQUEST0_BASE_IDX 8 +#define regTRAP_REQUEST1 0xe84102 +#define regTRAP_REQUEST1_BASE_IDX 8 +#define regTRAP_REQUEST2 0xe84103 +#define regTRAP_REQUEST2_BASE_IDX 8 +#define regTRAP_REQUEST3 0xe84104 +#define regTRAP_REQUEST3_BASE_IDX 8 +#define regTRAP_REQUEST4 0xe84105 +#define regTRAP_REQUEST4_BASE_IDX 8 +#define regTRAP_REQUEST5 0xe84106 +#define regTRAP_REQUEST5_BASE_IDX 8 +#define regTRAP_REQUEST_DATASTRB0 0xe84108 +#define regTRAP_REQUEST_DATASTRB0_BASE_IDX 8 +#define regTRAP_REQUEST_DATASTRB1 0xe84109 +#define regTRAP_REQUEST_DATASTRB1_BASE_IDX 8 +#define regTRAP_REQUEST_DATA0 0xe84110 +#define regTRAP_REQUEST_DATA0_BASE_IDX 8 +#define regTRAP_REQUEST_DATA1 0xe84111 +#define regTRAP_REQUEST_DATA1_BASE_IDX 8 +#define regTRAP_REQUEST_DATA2 0xe84112 +#define regTRAP_REQUEST_DATA2_BASE_IDX 8 +#define regTRAP_REQUEST_DATA3 0xe84113 +#define regTRAP_REQUEST_DATA3_BASE_IDX 8 +#define regTRAP_REQUEST_DATA4 0xe84114 +#define regTRAP_REQUEST_DATA4_BASE_IDX 8 +#define regTRAP_REQUEST_DATA5 0xe84115 +#define regTRAP_REQUEST_DATA5_BASE_IDX 8 +#define regTRAP_REQUEST_DATA6 0xe84116 +#define regTRAP_REQUEST_DATA6_BASE_IDX 8 +#define regTRAP_REQUEST_DATA7 0xe84117 +#define regTRAP_REQUEST_DATA7_BASE_IDX 8 +#define regTRAP_REQUEST_DATA8 0xe84118 +#define regTRAP_REQUEST_DATA8_BASE_IDX 8 +#define regTRAP_REQUEST_DATA9 0xe84119 +#define regTRAP_REQUEST_DATA9_BASE_IDX 8 +#define regTRAP_REQUEST_DATA10 0xe8411a +#define regTRAP_REQUEST_DATA10_BASE_IDX 8 +#define regTRAP_REQUEST_DATA11 0xe8411b +#define regTRAP_REQUEST_DATA11_BASE_IDX 8 +#define regTRAP_REQUEST_DATA12 0xe8411c +#define regTRAP_REQUEST_DATA12_BASE_IDX 8 +#define regTRAP_REQUEST_DATA13 0xe8411d +#define regTRAP_REQUEST_DATA13_BASE_IDX 8 +#define regTRAP_REQUEST_DATA14 0xe8411e +#define regTRAP_REQUEST_DATA14_BASE_IDX 8 +#define regTRAP_REQUEST_DATA15 0xe8411f +#define regTRAP_REQUEST_DATA15_BASE_IDX 8 +#define regTRAP_RESPONSE_CONTROL 0xe84130 +#define regTRAP_RESPONSE_CONTROL_BASE_IDX 8 +#define regTRAP_RESPONSE0 0xe84131 +#define regTRAP_RESPONSE0_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA0 0xe84140 +#define regTRAP_RESPONSE_DATA0_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA1 0xe84141 +#define regTRAP_RESPONSE_DATA1_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA2 0xe84142 +#define regTRAP_RESPONSE_DATA2_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA3 0xe84143 +#define regTRAP_RESPONSE_DATA3_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA4 0xe84144 +#define regTRAP_RESPONSE_DATA4_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA5 0xe84145 +#define regTRAP_RESPONSE_DATA5_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA6 0xe84146 +#define regTRAP_RESPONSE_DATA6_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA7 0xe84147 +#define regTRAP_RESPONSE_DATA7_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA8 0xe84148 +#define regTRAP_RESPONSE_DATA8_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA9 0xe84149 +#define regTRAP_RESPONSE_DATA9_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA10 0xe8414a +#define regTRAP_RESPONSE_DATA10_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA11 0xe8414b +#define regTRAP_RESPONSE_DATA11_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA12 0xe8414c +#define regTRAP_RESPONSE_DATA12_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA13 0xe8414d +#define regTRAP_RESPONSE_DATA13_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA14 0xe8414e +#define regTRAP_RESPONSE_DATA14_BASE_IDX 8 +#define regTRAP_RESPONSE_DATA15 0xe8414f +#define regTRAP_RESPONSE_DATA15_BASE_IDX 8 +#define regTRAP0_CONTROL0 0xe84200 +#define regTRAP0_CONTROL0_BASE_IDX 8 +#define regTRAP0_ADDRESS_LO 0xe84202 +#define regTRAP0_ADDRESS_LO_BASE_IDX 8 +#define regTRAP0_ADDRESS_HI 0xe84203 +#define regTRAP0_ADDRESS_HI_BASE_IDX 8 +#define regTRAP0_COMMAND 0xe84204 +#define regTRAP0_COMMAND_BASE_IDX 8 +#define regTRAP0_ADDRESS_LO_MASK 0xe84206 +#define regTRAP0_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP0_ADDRESS_HI_MASK 0xe84207 +#define regTRAP0_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP0_COMMAND_MASK 0xe84208 +#define regTRAP0_COMMAND_MASK_BASE_IDX 8 +#define regTRAP1_CONTROL0 0xe84210 +#define regTRAP1_CONTROL0_BASE_IDX 8 +#define regTRAP1_ADDRESS_LO 0xe84212 +#define regTRAP1_ADDRESS_LO_BASE_IDX 8 +#define regTRAP1_ADDRESS_HI 0xe84213 +#define regTRAP1_ADDRESS_HI_BASE_IDX 8 +#define regTRAP1_COMMAND 0xe84214 +#define regTRAP1_COMMAND_BASE_IDX 8 +#define regTRAP1_ADDRESS_LO_MASK 0xe84216 +#define regTRAP1_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP1_ADDRESS_HI_MASK 0xe84217 +#define regTRAP1_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP1_COMMAND_MASK 0xe84218 +#define regTRAP1_COMMAND_MASK_BASE_IDX 8 +#define regTRAP2_CONTROL0 0xe84220 +#define regTRAP2_CONTROL0_BASE_IDX 8 +#define regTRAP2_ADDRESS_LO 0xe84222 +#define regTRAP2_ADDRESS_LO_BASE_IDX 8 +#define regTRAP2_ADDRESS_HI 0xe84223 +#define regTRAP2_ADDRESS_HI_BASE_IDX 8 +#define regTRAP2_COMMAND 0xe84224 +#define regTRAP2_COMMAND_BASE_IDX 8 +#define regTRAP2_ADDRESS_LO_MASK 0xe84226 +#define regTRAP2_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP2_ADDRESS_HI_MASK 0xe84227 +#define regTRAP2_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP2_COMMAND_MASK 0xe84228 +#define regTRAP2_COMMAND_MASK_BASE_IDX 8 +#define regTRAP3_CONTROL0 0xe84230 +#define regTRAP3_CONTROL0_BASE_IDX 8 +#define regTRAP3_ADDRESS_LO 0xe84232 +#define regTRAP3_ADDRESS_LO_BASE_IDX 8 +#define regTRAP3_ADDRESS_HI 0xe84233 +#define regTRAP3_ADDRESS_HI_BASE_IDX 8 +#define regTRAP3_COMMAND 0xe84234 +#define regTRAP3_COMMAND_BASE_IDX 8 +#define regTRAP3_ADDRESS_LO_MASK 0xe84236 +#define regTRAP3_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP3_ADDRESS_HI_MASK 0xe84237 +#define regTRAP3_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP3_COMMAND_MASK 0xe84238 +#define regTRAP3_COMMAND_MASK_BASE_IDX 8 +#define regTRAP4_CONTROL0 0xe84240 +#define regTRAP4_CONTROL0_BASE_IDX 8 +#define regTRAP4_ADDRESS_LO 0xe84242 +#define regTRAP4_ADDRESS_LO_BASE_IDX 8 +#define regTRAP4_ADDRESS_HI 0xe84243 +#define regTRAP4_ADDRESS_HI_BASE_IDX 8 +#define regTRAP4_COMMAND 0xe84244 +#define regTRAP4_COMMAND_BASE_IDX 8 +#define regTRAP4_ADDRESS_LO_MASK 0xe84246 +#define regTRAP4_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP4_ADDRESS_HI_MASK 0xe84247 +#define regTRAP4_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP4_COMMAND_MASK 0xe84248 +#define regTRAP4_COMMAND_MASK_BASE_IDX 8 +#define regTRAP5_CONTROL0 0xe84250 +#define regTRAP5_CONTROL0_BASE_IDX 8 +#define regTRAP5_ADDRESS_LO 0xe84252 +#define regTRAP5_ADDRESS_LO_BASE_IDX 8 +#define regTRAP5_ADDRESS_HI 0xe84253 +#define regTRAP5_ADDRESS_HI_BASE_IDX 8 +#define regTRAP5_COMMAND 0xe84254 +#define regTRAP5_COMMAND_BASE_IDX 8 +#define regTRAP5_ADDRESS_LO_MASK 0xe84256 +#define regTRAP5_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP5_ADDRESS_HI_MASK 0xe84257 +#define regTRAP5_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP5_COMMAND_MASK 0xe84258 +#define regTRAP5_COMMAND_MASK_BASE_IDX 8 +#define regTRAP6_CONTROL0 0xe84260 +#define regTRAP6_CONTROL0_BASE_IDX 8 +#define regTRAP6_ADDRESS_LO 0xe84262 +#define regTRAP6_ADDRESS_LO_BASE_IDX 8 +#define regTRAP6_ADDRESS_HI 0xe84263 +#define regTRAP6_ADDRESS_HI_BASE_IDX 8 +#define regTRAP6_COMMAND 0xe84264 +#define regTRAP6_COMMAND_BASE_IDX 8 +#define regTRAP6_ADDRESS_LO_MASK 0xe84266 +#define regTRAP6_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP6_ADDRESS_HI_MASK 0xe84267 +#define regTRAP6_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP6_COMMAND_MASK 0xe84268 +#define regTRAP6_COMMAND_MASK_BASE_IDX 8 +#define regTRAP7_CONTROL0 0xe84270 +#define regTRAP7_CONTROL0_BASE_IDX 8 +#define regTRAP7_ADDRESS_LO 0xe84272 +#define regTRAP7_ADDRESS_LO_BASE_IDX 8 +#define regTRAP7_ADDRESS_HI 0xe84273 +#define regTRAP7_ADDRESS_HI_BASE_IDX 8 +#define regTRAP7_COMMAND 0xe84274 +#define regTRAP7_COMMAND_BASE_IDX 8 +#define regTRAP7_ADDRESS_LO_MASK 0xe84276 +#define regTRAP7_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP7_ADDRESS_HI_MASK 0xe84277 +#define regTRAP7_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP7_COMMAND_MASK 0xe84278 +#define regTRAP7_COMMAND_MASK_BASE_IDX 8 +#define regTRAP8_CONTROL0 0xe84280 +#define regTRAP8_CONTROL0_BASE_IDX 8 +#define regTRAP8_ADDRESS_LO 0xe84282 +#define regTRAP8_ADDRESS_LO_BASE_IDX 8 +#define regTRAP8_ADDRESS_HI 0xe84283 +#define regTRAP8_ADDRESS_HI_BASE_IDX 8 +#define regTRAP8_COMMAND 0xe84284 +#define regTRAP8_COMMAND_BASE_IDX 8 +#define regTRAP8_ADDRESS_LO_MASK 0xe84286 +#define regTRAP8_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP8_ADDRESS_HI_MASK 0xe84287 +#define regTRAP8_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP8_COMMAND_MASK 0xe84288 +#define regTRAP8_COMMAND_MASK_BASE_IDX 8 +#define regTRAP9_CONTROL0 0xe84290 +#define regTRAP9_CONTROL0_BASE_IDX 8 +#define regTRAP9_ADDRESS_LO 0xe84292 +#define regTRAP9_ADDRESS_LO_BASE_IDX 8 +#define regTRAP9_ADDRESS_HI 0xe84293 +#define regTRAP9_ADDRESS_HI_BASE_IDX 8 +#define regTRAP9_COMMAND 0xe84294 +#define regTRAP9_COMMAND_BASE_IDX 8 +#define regTRAP9_ADDRESS_LO_MASK 0xe84296 +#define regTRAP9_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP9_ADDRESS_HI_MASK 0xe84297 +#define regTRAP9_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP9_COMMAND_MASK 0xe84298 +#define regTRAP9_COMMAND_MASK_BASE_IDX 8 +#define regTRAP10_CONTROL0 0xe842a0 +#define regTRAP10_CONTROL0_BASE_IDX 8 +#define regTRAP10_ADDRESS_LO 0xe842a2 +#define regTRAP10_ADDRESS_LO_BASE_IDX 8 +#define regTRAP10_ADDRESS_HI 0xe842a3 +#define regTRAP10_ADDRESS_HI_BASE_IDX 8 +#define regTRAP10_COMMAND 0xe842a4 +#define regTRAP10_COMMAND_BASE_IDX 8 +#define regTRAP10_ADDRESS_LO_MASK 0xe842a6 +#define regTRAP10_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP10_ADDRESS_HI_MASK 0xe842a7 +#define regTRAP10_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP10_COMMAND_MASK 0xe842a8 +#define regTRAP10_COMMAND_MASK_BASE_IDX 8 +#define regTRAP11_CONTROL0 0xe842b0 +#define regTRAP11_CONTROL0_BASE_IDX 8 +#define regTRAP11_ADDRESS_LO 0xe842b2 +#define regTRAP11_ADDRESS_LO_BASE_IDX 8 +#define regTRAP11_ADDRESS_HI 0xe842b3 +#define regTRAP11_ADDRESS_HI_BASE_IDX 8 +#define regTRAP11_COMMAND 0xe842b4 +#define regTRAP11_COMMAND_BASE_IDX 8 +#define regTRAP11_ADDRESS_LO_MASK 0xe842b6 +#define regTRAP11_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP11_ADDRESS_HI_MASK 0xe842b7 +#define regTRAP11_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP11_COMMAND_MASK 0xe842b8 +#define regTRAP11_COMMAND_MASK_BASE_IDX 8 +#define regTRAP12_CONTROL0 0xe842c0 +#define regTRAP12_CONTROL0_BASE_IDX 8 +#define regTRAP12_ADDRESS_LO 0xe842c2 +#define regTRAP12_ADDRESS_LO_BASE_IDX 8 +#define regTRAP12_ADDRESS_HI 0xe842c3 +#define regTRAP12_ADDRESS_HI_BASE_IDX 8 +#define regTRAP12_COMMAND 0xe842c4 +#define regTRAP12_COMMAND_BASE_IDX 8 +#define regTRAP12_ADDRESS_LO_MASK 0xe842c6 +#define regTRAP12_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP12_ADDRESS_HI_MASK 0xe842c7 +#define regTRAP12_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP12_COMMAND_MASK 0xe842c8 +#define regTRAP12_COMMAND_MASK_BASE_IDX 8 +#define regTRAP13_CONTROL0 0xe842d0 +#define regTRAP13_CONTROL0_BASE_IDX 8 +#define regTRAP13_ADDRESS_LO 0xe842d2 +#define regTRAP13_ADDRESS_LO_BASE_IDX 8 +#define regTRAP13_ADDRESS_HI 0xe842d3 +#define regTRAP13_ADDRESS_HI_BASE_IDX 8 +#define regTRAP13_COMMAND 0xe842d4 +#define regTRAP13_COMMAND_BASE_IDX 8 +#define regTRAP13_ADDRESS_LO_MASK 0xe842d6 +#define regTRAP13_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP13_ADDRESS_HI_MASK 0xe842d7 +#define regTRAP13_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP13_COMMAND_MASK 0xe842d8 +#define regTRAP13_COMMAND_MASK_BASE_IDX 8 +#define regTRAP14_CONTROL0 0xe842e0 +#define regTRAP14_CONTROL0_BASE_IDX 8 +#define regTRAP14_ADDRESS_LO 0xe842e2 +#define regTRAP14_ADDRESS_LO_BASE_IDX 8 +#define regTRAP14_ADDRESS_HI 0xe842e3 +#define regTRAP14_ADDRESS_HI_BASE_IDX 8 +#define regTRAP14_COMMAND 0xe842e4 +#define regTRAP14_COMMAND_BASE_IDX 8 +#define regTRAP14_ADDRESS_LO_MASK 0xe842e6 +#define regTRAP14_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP14_ADDRESS_HI_MASK 0xe842e7 +#define regTRAP14_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP14_COMMAND_MASK 0xe842e8 +#define regTRAP14_COMMAND_MASK_BASE_IDX 8 +#define regTRAP15_CONTROL0 0xe842f0 +#define regTRAP15_CONTROL0_BASE_IDX 8 +#define regTRAP15_ADDRESS_LO 0xe842f2 +#define regTRAP15_ADDRESS_LO_BASE_IDX 8 +#define regTRAP15_ADDRESS_HI 0xe842f3 +#define regTRAP15_ADDRESS_HI_BASE_IDX 8 +#define regTRAP15_COMMAND 0xe842f4 +#define regTRAP15_COMMAND_BASE_IDX 8 +#define regTRAP15_ADDRESS_LO_MASK 0xe842f6 +#define regTRAP15_ADDRESS_LO_MASK_BASE_IDX 8 +#define regTRAP15_ADDRESS_HI_MASK 0xe842f7 +#define regTRAP15_ADDRESS_HI_MASK_BASE_IDX 8 +#define regTRAP15_COMMAND_MASK 0xe842f8 +#define regTRAP15_COMMAND_MASK_BASE_IDX 8 +#define regSB_COMMAND 0xe85000 +#define regSB_COMMAND_BASE_IDX 8 +#define regSB_SUB_BUS_NUMBER_LATENCY 0xe85001 +#define regSB_SUB_BUS_NUMBER_LATENCY_BASE_IDX 8 +#define regSB_IO_BASE_LIMIT 0xe85002 +#define regSB_IO_BASE_LIMIT_BASE_IDX 8 +#define regSB_MEM_BASE_LIMIT 0xe85003 +#define regSB_MEM_BASE_LIMIT_BASE_IDX 8 +#define regSB_PREF_BASE_LIMIT 0xe85004 +#define regSB_PREF_BASE_LIMIT_BASE_IDX 8 +#define regSB_PREF_BASE_UPPER 0xe85005 +#define regSB_PREF_BASE_UPPER_BASE_IDX 8 +#define regSB_PREF_LIMIT_UPPER 0xe85006 +#define regSB_PREF_LIMIT_UPPER_BASE_IDX 8 +#define regSB_IO_BASE_LIMIT_HI 0xe85007 +#define regSB_IO_BASE_LIMIT_HI_BASE_IDX 8 +#define regSB_IRQ_BRIDGE_CNTL 0xe85008 +#define regSB_IRQ_BRIDGE_CNTL_BASE_IDX 8 +#define regSB_EXT_BRIDGE_CNTL 0xe85009 +#define regSB_EXT_BRIDGE_CNTL_BASE_IDX 8 +#define regSB_PMI_STATUS_CNTL 0xe8500a +#define regSB_PMI_STATUS_CNTL_BASE_IDX 8 +#define regSB_SLOT_CAP 0xe8500b +#define regSB_SLOT_CAP_BASE_IDX 8 +#define regSB_ROOT_CNTL 0xe8500c +#define regSB_ROOT_CNTL_BASE_IDX 8 +#define regSB_DEVICE_CNTL2 0xe8500d +#define regSB_DEVICE_CNTL2_BASE_IDX 8 +#define regMCA_SMN_INT_REQ_ADDR 0xe85020 +#define regMCA_SMN_INT_REQ_ADDR_BASE_IDX 8 +#define regMCA_SMN_INT_MCM_ADDR 0xe85021 +#define regMCA_SMN_INT_MCM_ADDR_BASE_IDX 8 +#define regMCA_SMN_INT_APERTUREID 0xe85022 +#define regMCA_SMN_INT_APERTUREID_BASE_IDX 8 +#define regMCA_SMN_INT_CONTROL 0xe85023 +#define regMCA_SMN_INT_CONTROL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_rascfg_ras_cfgdec +// base address: 0x13b20000 +#define regPARITY_CONTROL_0 0xe88000 +#define regPARITY_CONTROL_0_BASE_IDX 8 +#define regPARITY_CONTROL_1 0xe88001 +#define regPARITY_CONTROL_1_BASE_IDX 8 +#define regPARITY_SEVERITY_CONTROL_UNCORR_0 0xe88002 +#define regPARITY_SEVERITY_CONTROL_UNCORR_0_BASE_IDX 8 +#define regPARITY_SEVERITY_CONTROL_CORR_0 0xe88004 +#define regPARITY_SEVERITY_CONTROL_CORR_0_BASE_IDX 8 +#define regPARITY_SEVERITY_CONTROL_UCP_0 0xe88006 +#define regPARITY_SEVERITY_CONTROL_UCP_0_BASE_IDX 8 +#define regRAS_GLOBAL_STATUS_LO 0xe88008 +#define regRAS_GLOBAL_STATUS_LO_BASE_IDX 8 +#define regRAS_GLOBAL_STATUS_HI 0xe88009 +#define regRAS_GLOBAL_STATUS_HI_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP0 0xe8800a +#define regPARITY_ERROR_STATUS_UNCORR_GRP0_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP1 0xe8800b +#define regPARITY_ERROR_STATUS_UNCORR_GRP1_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP2 0xe8800c +#define regPARITY_ERROR_STATUS_UNCORR_GRP2_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP3 0xe8800d +#define regPARITY_ERROR_STATUS_UNCORR_GRP3_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP4 0xe8800e +#define regPARITY_ERROR_STATUS_UNCORR_GRP4_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP5 0xe8800f +#define regPARITY_ERROR_STATUS_UNCORR_GRP5_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP6 0xe88010 +#define regPARITY_ERROR_STATUS_UNCORR_GRP6_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP7 0xe88011 +#define regPARITY_ERROR_STATUS_UNCORR_GRP7_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP10 0xe88014 +#define regPARITY_ERROR_STATUS_UNCORR_GRP10_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP11 0xe88015 +#define regPARITY_ERROR_STATUS_UNCORR_GRP11_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP12 0xe88016 +#define regPARITY_ERROR_STATUS_UNCORR_GRP12_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP13 0xe88017 +#define regPARITY_ERROR_STATUS_UNCORR_GRP13_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP14 0xe88018 +#define regPARITY_ERROR_STATUS_UNCORR_GRP14_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP15 0xe88019 +#define regPARITY_ERROR_STATUS_UNCORR_GRP15_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UNCORR_GRP16 0xe8801a +#define regPARITY_ERROR_STATUS_UNCORR_GRP16_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP0 0xe8801b +#define regPARITY_ERROR_STATUS_CORR_GRP0_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP1 0xe8801c +#define regPARITY_ERROR_STATUS_CORR_GRP1_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP2 0xe8801d +#define regPARITY_ERROR_STATUS_CORR_GRP2_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP3 0xe8801e +#define regPARITY_ERROR_STATUS_CORR_GRP3_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP4 0xe8801f +#define regPARITY_ERROR_STATUS_CORR_GRP4_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP5 0xe88020 +#define regPARITY_ERROR_STATUS_CORR_GRP5_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP6 0xe88021 +#define regPARITY_ERROR_STATUS_CORR_GRP6_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP7 0xe88022 +#define regPARITY_ERROR_STATUS_CORR_GRP7_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP10 0xe88025 +#define regPARITY_ERROR_STATUS_CORR_GRP10_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP11 0xe88026 +#define regPARITY_ERROR_STATUS_CORR_GRP11_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP12 0xe88027 +#define regPARITY_ERROR_STATUS_CORR_GRP12_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP13 0xe88028 +#define regPARITY_ERROR_STATUS_CORR_GRP13_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP14 0xe88029 +#define regPARITY_ERROR_STATUS_CORR_GRP14_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP15 0xe8802a +#define regPARITY_ERROR_STATUS_CORR_GRP15_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP16 0xe8802b +#define regPARITY_ERROR_STATUS_CORR_GRP16_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_CORR_GRP17 0xe8802c +#define regPARITY_ERROR_STATUS_CORR_GRP17_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP0 0xe8802d +#define regPARITY_COUNTER_CORR_GRP0_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP1 0xe8802e +#define regPARITY_COUNTER_CORR_GRP1_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP2 0xe8802f +#define regPARITY_COUNTER_CORR_GRP2_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP3 0xe88030 +#define regPARITY_COUNTER_CORR_GRP3_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP4 0xe88031 +#define regPARITY_COUNTER_CORR_GRP4_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP5 0xe88032 +#define regPARITY_COUNTER_CORR_GRP5_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP6 0xe88033 +#define regPARITY_COUNTER_CORR_GRP6_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP7 0xe88034 +#define regPARITY_COUNTER_CORR_GRP7_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP10 0xe88037 +#define regPARITY_COUNTER_CORR_GRP10_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP11 0xe88038 +#define regPARITY_COUNTER_CORR_GRP11_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP12 0xe88039 +#define regPARITY_COUNTER_CORR_GRP12_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP13 0xe8803a +#define regPARITY_COUNTER_CORR_GRP13_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP14 0xe8803b +#define regPARITY_COUNTER_CORR_GRP14_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP15 0xe8803c +#define regPARITY_COUNTER_CORR_GRP15_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP16 0xe8803d +#define regPARITY_COUNTER_CORR_GRP16_BASE_IDX 8 +#define regPARITY_COUNTER_CORR_GRP17 0xe8803e +#define regPARITY_COUNTER_CORR_GRP17_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP0 0xe8803f +#define regPARITY_ERROR_STATUS_UCP_GRP0_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP1 0xe88040 +#define regPARITY_ERROR_STATUS_UCP_GRP1_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP2 0xe88041 +#define regPARITY_ERROR_STATUS_UCP_GRP2_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP3 0xe88042 +#define regPARITY_ERROR_STATUS_UCP_GRP3_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP4 0xe88043 +#define regPARITY_ERROR_STATUS_UCP_GRP4_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP5 0xe88044 +#define regPARITY_ERROR_STATUS_UCP_GRP5_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP6 0xe88045 +#define regPARITY_ERROR_STATUS_UCP_GRP6_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP7 0xe88046 +#define regPARITY_ERROR_STATUS_UCP_GRP7_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP10 0xe88049 +#define regPARITY_ERROR_STATUS_UCP_GRP10_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP11 0xe8804a +#define regPARITY_ERROR_STATUS_UCP_GRP11_BASE_IDX 8 +#define regPARITY_ERROR_STATUS_UCP_GRP12 0xe8804b +#define regPARITY_ERROR_STATUS_UCP_GRP12_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP0 0xe8804c +#define regPARITY_COUNTER_UCP_GRP0_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP1 0xe8804d +#define regPARITY_COUNTER_UCP_GRP1_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP2 0xe8804e +#define regPARITY_COUNTER_UCP_GRP2_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP3 0xe8804f +#define regPARITY_COUNTER_UCP_GRP3_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP4 0xe88050 +#define regPARITY_COUNTER_UCP_GRP4_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP5 0xe88051 +#define regPARITY_COUNTER_UCP_GRP5_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP6 0xe88052 +#define regPARITY_COUNTER_UCP_GRP6_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP7 0xe88053 +#define regPARITY_COUNTER_UCP_GRP7_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP10 0xe88056 +#define regPARITY_COUNTER_UCP_GRP10_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP11 0xe88057 +#define regPARITY_COUNTER_UCP_GRP11_BASE_IDX 8 +#define regPARITY_COUNTER_UCP_GRP12 0xe88058 +#define regPARITY_COUNTER_UCP_GRP12_BASE_IDX 8 +#define regMISC_SEVERITY_CONTROL 0xe88059 +#define regMISC_SEVERITY_CONTROL_BASE_IDX 8 +#define regMISC_RAS_CONTROL 0xe8805a +#define regMISC_RAS_CONTROL_BASE_IDX 8 +#define regRAS_SCRATCH_0 0xe8805b +#define regRAS_SCRATCH_0_BASE_IDX 8 +#define regRAS_SCRATCH_1 0xe8805c +#define regRAS_SCRATCH_1_BASE_IDX 8 +#define regErrEvent_ACTION_CONTROL 0xe8805d +#define regErrEvent_ACTION_CONTROL_BASE_IDX 8 +#define regParitySerr_ACTION_CONTROL 0xe8805e +#define regParitySerr_ACTION_CONTROL_BASE_IDX 8 +#define regParityFatal_ACTION_CONTROL 0xe8805f +#define regParityFatal_ACTION_CONTROL_BASE_IDX 8 +#define regParityNonFatal_ACTION_CONTROL 0xe88060 +#define regParityNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regParityCorr_ACTION_CONTROL 0xe88061 +#define regParityCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortASerr_ACTION_CONTROL 0xe88062 +#define regPCIE0PortASerr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortAIntFatal_ACTION_CONTROL 0xe88063 +#define regPCIE0PortAIntFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortAIntNonFatal_ACTION_CONTROL 0xe88064 +#define regPCIE0PortAIntNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortAIntCorr_ACTION_CONTROL 0xe88065 +#define regPCIE0PortAIntCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortAExtFatal_ACTION_CONTROL 0xe88066 +#define regPCIE0PortAExtFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortAExtNonFatal_ACTION_CONTROL 0xe88067 +#define regPCIE0PortAExtNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortAExtCorr_ACTION_CONTROL 0xe88068 +#define regPCIE0PortAExtCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortAParityErr_ACTION_CONTROL 0xe88069 +#define regPCIE0PortAParityErr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortBSerr_ACTION_CONTROL 0xe8806a +#define regPCIE0PortBSerr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortBIntFatal_ACTION_CONTROL 0xe8806b +#define regPCIE0PortBIntFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortBIntNonFatal_ACTION_CONTROL 0xe8806c +#define regPCIE0PortBIntNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortBIntCorr_ACTION_CONTROL 0xe8806d +#define regPCIE0PortBIntCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortBExtFatal_ACTION_CONTROL 0xe8806e +#define regPCIE0PortBExtFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortBExtNonFatal_ACTION_CONTROL 0xe8806f +#define regPCIE0PortBExtNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortBExtCorr_ACTION_CONTROL 0xe88070 +#define regPCIE0PortBExtCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortBParityErr_ACTION_CONTROL 0xe88071 +#define regPCIE0PortBParityErr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortCSerr_ACTION_CONTROL 0xe88072 +#define regPCIE0PortCSerr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortCIntFatal_ACTION_CONTROL 0xe88073 +#define regPCIE0PortCIntFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortCIntNonFatal_ACTION_CONTROL 0xe88074 +#define regPCIE0PortCIntNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortCIntCorr_ACTION_CONTROL 0xe88075 +#define regPCIE0PortCIntCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortCExtFatal_ACTION_CONTROL 0xe88076 +#define regPCIE0PortCExtFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortCExtNonFatal_ACTION_CONTROL 0xe88077 +#define regPCIE0PortCExtNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortCExtCorr_ACTION_CONTROL 0xe88078 +#define regPCIE0PortCExtCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortCParityErr_ACTION_CONTROL 0xe88079 +#define regPCIE0PortCParityErr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortDSerr_ACTION_CONTROL 0xe8807a +#define regPCIE0PortDSerr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortDIntFatal_ACTION_CONTROL 0xe8807b +#define regPCIE0PortDIntFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortDIntNonFatal_ACTION_CONTROL 0xe8807c +#define regPCIE0PortDIntNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortDIntCorr_ACTION_CONTROL 0xe8807d +#define regPCIE0PortDIntCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortDExtFatal_ACTION_CONTROL 0xe8807e +#define regPCIE0PortDExtFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortDExtNonFatal_ACTION_CONTROL 0xe8807f +#define regPCIE0PortDExtNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortDExtCorr_ACTION_CONTROL 0xe88080 +#define regPCIE0PortDExtCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortDParityErr_ACTION_CONTROL 0xe88081 +#define regPCIE0PortDParityErr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortESerr_ACTION_CONTROL 0xe88082 +#define regPCIE0PortESerr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortEIntFatal_ACTION_CONTROL 0xe88083 +#define regPCIE0PortEIntFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortEIntNonFatal_ACTION_CONTROL 0xe88084 +#define regPCIE0PortEIntNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortEIntCorr_ACTION_CONTROL 0xe88085 +#define regPCIE0PortEIntCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortEExtFatal_ACTION_CONTROL 0xe88086 +#define regPCIE0PortEExtFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortEExtNonFatal_ACTION_CONTROL 0xe88087 +#define regPCIE0PortEExtNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortEExtCorr_ACTION_CONTROL 0xe88088 +#define regPCIE0PortEExtCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortEParityErr_ACTION_CONTROL 0xe88089 +#define regPCIE0PortEParityErr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortFSerr_ACTION_CONTROL 0xe8808a +#define regPCIE0PortFSerr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortFIntFatal_ACTION_CONTROL 0xe8808b +#define regPCIE0PortFIntFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortFIntNonFatal_ACTION_CONTROL 0xe8808c +#define regPCIE0PortFIntNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortFIntCorr_ACTION_CONTROL 0xe8808d +#define regPCIE0PortFIntCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortFExtFatal_ACTION_CONTROL 0xe8808e +#define regPCIE0PortFExtFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortFExtNonFatal_ACTION_CONTROL 0xe8808f +#define regPCIE0PortFExtNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortFExtCorr_ACTION_CONTROL 0xe88090 +#define regPCIE0PortFExtCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortFParityErr_ACTION_CONTROL 0xe88091 +#define regPCIE0PortFParityErr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortGSerr_ACTION_CONTROL 0xe88092 +#define regPCIE0PortGSerr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortGIntFatal_ACTION_CONTROL 0xe88093 +#define regPCIE0PortGIntFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortGIntNonFatal_ACTION_CONTROL 0xe88094 +#define regPCIE0PortGIntNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortGIntCorr_ACTION_CONTROL 0xe88095 +#define regPCIE0PortGIntCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortGExtFatal_ACTION_CONTROL 0xe88096 +#define regPCIE0PortGExtFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortGExtNonFatal_ACTION_CONTROL 0xe88097 +#define regPCIE0PortGExtNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortGExtCorr_ACTION_CONTROL 0xe88098 +#define regPCIE0PortGExtCorr_ACTION_CONTROL_BASE_IDX 8 +#define regPCIE0PortGParityErr_ACTION_CONTROL 0xe88099 +#define regPCIE0PortGParityErr_ACTION_CONTROL_BASE_IDX 8 +#define regNBIF1PortASerr_ACTION_CONTROL 0xe880ca +#define regNBIF1PortASerr_ACTION_CONTROL_BASE_IDX 8 +#define regNBIF1PortAIntFatal_ACTION_CONTROL 0xe880cb +#define regNBIF1PortAIntFatal_ACTION_CONTROL_BASE_IDX 8 +#define regNBIF1PortAIntNonFatal_ACTION_CONTROL 0xe880cc +#define regNBIF1PortAIntNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regNBIF1PortAIntCorr_ACTION_CONTROL 0xe880cd +#define regNBIF1PortAIntCorr_ACTION_CONTROL_BASE_IDX 8 +#define regNBIF1PortAExtFatal_ACTION_CONTROL 0xe880ce +#define regNBIF1PortAExtFatal_ACTION_CONTROL_BASE_IDX 8 +#define regNBIF1PortAExtNonFatal_ACTION_CONTROL 0xe880cf +#define regNBIF1PortAExtNonFatal_ACTION_CONTROL_BASE_IDX 8 +#define regNBIF1PortAExtCorr_ACTION_CONTROL 0xe880d0 +#define regNBIF1PortAExtCorr_ACTION_CONTROL_BASE_IDX 8 +#define regNBIF1PortAParityErr_ACTION_CONTROL 0xe880d1 +#define regNBIF1PortAParityErr_ACTION_CONTROL_BASE_IDX 8 +#define regSYNCFLOOD_STATUS 0xe88200 +#define regSYNCFLOOD_STATUS_BASE_IDX 8 +#define regNMI_STATUS 0xe88201 +#define regNMI_STATUS_BASE_IDX 8 +#define regPOISON_ACTION_CONTROL 0xe88205 +#define regPOISON_ACTION_CONTROL_BASE_IDX 8 +#define regINTERNAL_POISON_STATUS 0xe88206 +#define regINTERNAL_POISON_STATUS_BASE_IDX 8 +#define regINTERNAL_POISON_MASK 0xe88207 +#define regINTERNAL_POISON_MASK_BASE_IDX 8 +#define regEGRESS_POISON_STATUS_LO 0xe88208 +#define regEGRESS_POISON_STATUS_LO_BASE_IDX 8 +#define regEGRESS_POISON_STATUS_HI 0xe88209 +#define regEGRESS_POISON_STATUS_HI_BASE_IDX 8 +#define regEGRESS_POISON_MASK_LO 0xe8820a +#define regEGRESS_POISON_MASK_LO_BASE_IDX 8 +#define regEGRESS_POISON_MASK_HI 0xe8820b +#define regEGRESS_POISON_MASK_HI_BASE_IDX 8 +#define regEGRESS_POISON_SEVERITY_DOWN 0xe8820c +#define regEGRESS_POISON_SEVERITY_DOWN_BASE_IDX 8 +#define regEGRESS_POISON_SEVERITY_UPPER 0xe8820d +#define regEGRESS_POISON_SEVERITY_UPPER_BASE_IDX 8 +#define regAPML_STATUS 0xe88370 +#define regAPML_STATUS_BASE_IDX 8 +#define regAPML_CONTROL 0xe88371 +#define regAPML_CONTROL_BASE_IDX 8 +#define regAPML_TRIGGER 0xe88372 +#define regAPML_TRIGGER_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg0_devind_cfgdecp +// base address: 0x13b31000 +#define regNB_PCIE0DEVINDCFG0_STEERING_CNTL 0xe8c403 +#define regNB_PCIE0DEVINDCFG0_STEERING_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg1_devind_cfgdecp +// base address: 0x13b31400 +#define regNB_PCIE0DEVINDCFG1_STEERING_CNTL 0xe8c503 +#define regNB_PCIE0DEVINDCFG1_STEERING_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg2_devind_cfgdecp +// base address: 0x13b31800 +#define regNB_PCIE0DEVINDCFG2_STEERING_CNTL 0xe8c603 +#define regNB_PCIE0DEVINDCFG2_STEERING_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg3_devind_cfgdecp +// base address: 0x13b31c00 +#define regNB_PCIE0DEVINDCFG3_STEERING_CNTL 0xe8c703 +#define regNB_PCIE0DEVINDCFG3_STEERING_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg4_devind_cfgdecp +// base address: 0x13b32000 +#define regNB_PCIE0DEVINDCFG4_STEERING_CNTL 0xe8c803 +#define regNB_PCIE0DEVINDCFG4_STEERING_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg5_devind_cfgdecp +// base address: 0x13b32400 +#define regNB_PCIE0DEVINDCFG5_STEERING_CNTL 0xe8c903 +#define regNB_PCIE0DEVINDCFG5_STEERING_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0devindcfg6_devind_cfgdecp +// base address: 0x13b32800 +#define regNB_PCIE0DEVINDCFG6_STEERING_CNTL 0xe8ca03 +#define regNB_PCIE0DEVINDCFG6_STEERING_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_NBIF1devindcfg0_devind_cfgdecp +// base address: 0x13b38000 +#define regNB_NBIF1DEVINDCFG0_STEERING_CNTL 0xe8e003 +#define regNB_NBIF1DEVINDCFG0_STEERING_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_intSBdevindcfg0_devind_cfgdecp +// base address: 0x13b3c000 +#define regNB_INTSBDEVINDCFG0_STEERING_CNTL 0xe8f003 +#define regNB_INTSBDEVINDCFG0_STEERING_CNTL_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg0_pciercbdgind_cfgdec +// base address: 0x13b7d600 +#define regNB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION 0xe9f5b7 +#define regNB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX 0xe9f5b8 +#define regNB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA 0xe9f5b9 +#define regNB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg1_pciercbdgind_cfgdec +// base address: 0x13b7d700 +#define regNB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_EXTENSION 0xe9f5f7 +#define regNB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX 0xe9f5f8 +#define regNB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA 0xe9f5f9 +#define regNB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg2_pciercbdgind_cfgdec +// base address: 0x13b7d800 +#define regNB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_EXTENSION 0xe9f637 +#define regNB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX 0xe9f638 +#define regNB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA 0xe9f639 +#define regNB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg3_pciercbdgind_cfgdec +// base address: 0x13b7d900 +#define regNB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_EXTENSION 0xe9f677 +#define regNB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX 0xe9f678 +#define regNB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA 0xe9f679 +#define regNB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg4_pciercbdgind_cfgdec +// base address: 0x13b7da00 +#define regNB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_EXTENSION 0xe9f6b7 +#define regNB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX 0xe9f6b8 +#define regNB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA 0xe9f6b9 +#define regNB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg5_pciercbdgind_cfgdec +// base address: 0x13b7db00 +#define regNB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_EXTENSION 0xe9f6f7 +#define regNB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX 0xe9f6f8 +#define regNB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA 0xe9f6f9 +#define regNB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_PCIE0rcbdg_indcfg6_pciercbdgind_cfgdec +// base address: 0x13b7dc00 +#define regNB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_EXTENSION 0xe9f737 +#define regNB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX 0xe9f738 +#define regNB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_BASE_IDX 8 +#define regNB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA 0xe9f739 +#define regNB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_NBIF1rcbdg_indcfg0_pciercbdgind_cfgdec +// base address: 0x13b7f200 +#define regNB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION 0xe9fcb7 +#define regNB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_EXTENSION_BASE_IDX 8 +#define regNB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX 0xe9fcb8 +#define regNB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_BASE_IDX 8 +#define regNB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA 0xe9fcb9 +#define regNB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_iommu_l2a_l2acfg +// base address: 0x15700000 +#define regL2_PERF_CNTL_0 0x1580000 +#define regL2_PERF_CNTL_0_BASE_IDX 8 +#define regL2_PERF_COUNT_0 0x1580001 +#define regL2_PERF_COUNT_0_BASE_IDX 8 +#define regL2_PERF_COUNT_1 0x1580002 +#define regL2_PERF_COUNT_1_BASE_IDX 8 +#define regL2_PERF_CNTL_1 0x1580003 +#define regL2_PERF_CNTL_1_BASE_IDX 8 +#define regL2_PERF_COUNT_2 0x1580004 +#define regL2_PERF_COUNT_2_BASE_IDX 8 +#define regL2_PERF_COUNT_3 0x1580005 +#define regL2_PERF_COUNT_3_BASE_IDX 8 +#define regL2_STATUS_0 0x1580008 +#define regL2_STATUS_0_BASE_IDX 8 +#define regL2_CONTROL_0 0x158000c +#define regL2_CONTROL_0_BASE_IDX 8 +#define regL2_CONTROL_1 0x158000d +#define regL2_CONTROL_1_BASE_IDX 8 +#define regL2_DTC_CONTROL 0x1580010 +#define regL2_DTC_CONTROL_BASE_IDX 8 +#define regL2_DTC_HASH_CONTROL 0x1580011 +#define regL2_DTC_HASH_CONTROL_BASE_IDX 8 +#define regL2_DTC_WAY_CONTROL 0x1580012 +#define regL2_DTC_WAY_CONTROL_BASE_IDX 8 +#define regL2_ITC_CONTROL 0x1580014 +#define regL2_ITC_CONTROL_BASE_IDX 8 +#define regL2_ITC_HASH_CONTROL 0x1580015 +#define regL2_ITC_HASH_CONTROL_BASE_IDX 8 +#define regL2_ITC_WAY_CONTROL 0x1580016 +#define regL2_ITC_WAY_CONTROL_BASE_IDX 8 +#define regL2_PTC_A_CONTROL 0x1580018 +#define regL2_PTC_A_CONTROL_BASE_IDX 8 +#define regL2_PTC_A_HASH_CONTROL 0x1580019 +#define regL2_PTC_A_HASH_CONTROL_BASE_IDX 8 +#define regL2_PTC_A_WAY_CONTROL 0x158001a +#define regL2_PTC_A_WAY_CONTROL_BASE_IDX 8 +#define regL2A_UPDATE_FILTER_CNTL 0x1580022 +#define regL2A_UPDATE_FILTER_CNTL_BASE_IDX 8 +#define regL2_ERR_RULE_CONTROL_3 0x1580030 +#define regL2_ERR_RULE_CONTROL_3_BASE_IDX 8 +#define regL2_ERR_RULE_CONTROL_4 0x1580031 +#define regL2_ERR_RULE_CONTROL_4_BASE_IDX 8 +#define regL2_ERR_RULE_CONTROL_5 0x1580032 +#define regL2_ERR_RULE_CONTROL_5_BASE_IDX 8 +#define regL2_L2A_CK_GATE_CONTROL 0x1580033 +#define regL2_L2A_CK_GATE_CONTROL_BASE_IDX 8 +#define regL2_L2A_PGSIZE_CONTROL 0x1580034 +#define regL2_L2A_PGSIZE_CONTROL_BASE_IDX 8 +#define regL2_PWRGATE_CNTRL_REG_0 0x158003e +#define regL2_PWRGATE_CNTRL_REG_0_BASE_IDX 8 +#define regL2_PWRGATE_CNTRL_REG_3 0x1580041 +#define regL2_PWRGATE_CNTRL_REG_3_BASE_IDX 8 +#define regL2_ECO_CNTRL_0 0x1580042 +#define regL2_ECO_CNTRL_0_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_iommu_l2indx_l2indxcfg +// base address: 0x13f01000 +#define regL2_STATUS_1 0xf80448 +#define regL2_STATUS_1_BASE_IDX 8 +#define regL2_SB_LOCATION 0xf8044b +#define regL2_SB_LOCATION_BASE_IDX 8 +#define regL2_CONTROL_5 0xf8044c +#define regL2_CONTROL_5_BASE_IDX 8 +#define regL2_CONTROL_6 0xf8044f +#define regL2_CONTROL_6_BASE_IDX 8 +#define regL2_PDC_CONTROL 0xf80450 +#define regL2_PDC_CONTROL_BASE_IDX 8 +#define regL2_PDC_HASH_CONTROL 0xf80451 +#define regL2_PDC_HASH_CONTROL_BASE_IDX 8 +#define regL2_PDC_WAY_CONTROL 0xf80452 +#define regL2_PDC_WAY_CONTROL_BASE_IDX 8 +#define regL2B_UPDATE_FILTER_CNTL 0xf80453 +#define regL2B_UPDATE_FILTER_CNTL_BASE_IDX 8 +#define regL2_TW_CONTROL 0xf80454 +#define regL2_TW_CONTROL_BASE_IDX 8 +#define regL2_CP_CONTROL 0xf80456 +#define regL2_CP_CONTROL_BASE_IDX 8 +#define regL2_CP_CONTROL_1 0xf80457 +#define regL2_CP_CONTROL_1_BASE_IDX 8 +#define regL2_TW_CONTROL_1 0xf8045a +#define regL2_TW_CONTROL_1_BASE_IDX 8 +#define regL2_TW_CONTROL_2 0xf80461 +#define regL2_TW_CONTROL_2_BASE_IDX 8 +#define regL2_TW_CONTROL_3 0xf80462 +#define regL2_TW_CONTROL_3_BASE_IDX 8 +#define regL2_CREDIT_CONTROL_0 0xf80470 +#define regL2_CREDIT_CONTROL_0_BASE_IDX 8 +#define regL2_CREDIT_CONTROL_1 0xf80471 +#define regL2_CREDIT_CONTROL_1_BASE_IDX 8 +#define regL2_ERR_RULE_CONTROL_0 0xf80480 +#define regL2_ERR_RULE_CONTROL_0_BASE_IDX 8 +#define regL2_ERR_RULE_CONTROL_1 0xf80481 +#define regL2_ERR_RULE_CONTROL_1_BASE_IDX 8 +#define regL2_ERR_RULE_CONTROL_2 0xf80482 +#define regL2_ERR_RULE_CONTROL_2_BASE_IDX 8 +#define regL2_L2B_CK_GATE_CONTROL 0xf80490 +#define regL2_L2B_CK_GATE_CONTROL_BASE_IDX 8 +#define regPPR_CONTROL 0xf80492 +#define regPPR_CONTROL_BASE_IDX 8 +#define regL2_L2B_PGSIZE_CONTROL 0xf80494 +#define regL2_L2B_PGSIZE_CONTROL_BASE_IDX 8 +#define regL2_PERF_CNTL_2 0xf80499 +#define regL2_PERF_CNTL_2_BASE_IDX 8 +#define regL2_PERF_COUNT_4 0xf8049a +#define regL2_PERF_COUNT_4_BASE_IDX 8 +#define regL2_PERF_COUNT_5 0xf8049b +#define regL2_PERF_COUNT_5_BASE_IDX 8 +#define regL2_PERF_CNTL_3 0xf8049c +#define regL2_PERF_CNTL_3_BASE_IDX 8 +#define regL2_PERF_COUNT_6 0xf8049d +#define regL2_PERF_COUNT_6_BASE_IDX 8 +#define regL2_PERF_COUNT_7 0xf8049e +#define regL2_PERF_COUNT_7_BASE_IDX 8 +#define regL2B_SDP_PARITY_ERROR_EN 0xf804a2 +#define regL2B_SDP_PARITY_ERROR_EN_BASE_IDX 8 +#define regL2_ECO_CNTRL_1 0xf804a3 +#define regL2_ECO_CNTRL_1_BASE_IDX 8 +#define regL2_CP_CONTROL_2 0xf804bf +#define regL2_CP_CONTROL_2_BASE_IDX 8 +#define regL2_CP_CONTROL_3 0xf804c0 +#define regL2_CP_CONTROL_3_BASE_IDX 8 + + +// addressBlock: aid_nbio_iohub_nb_ioapiccfg_ioapic_cfgdec +// base address: 0x14300000 +#define regFEATURES_ENABLE 0x1080000 +#define regFEATURES_ENABLE_BASE_IDX 8 + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_RC_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_RC_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_RC_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_RC_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_RC_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_RC_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_RC_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_RC_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_RC_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_RC_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_RC_HEADER 0x000e +#define cfgBIF_CFG_DEV0_RC_BIST 0x000f +#define cfgBIF_CFG_DEV0_RC_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_RC_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_RC_SUB_BUS_NUMBER_LATENCY 0x0018 +#define cfgBIF_CFG_DEV0_RC_IO_BASE_LIMIT 0x001c +#define cfgBIF_CFG_DEV0_RC_SECONDARY_STATUS 0x001e +#define cfgBIF_CFG_DEV0_RC_MEM_BASE_LIMIT 0x0020 +#define cfgBIF_CFG_DEV0_RC_PREF_BASE_LIMIT 0x0024 +#define cfgBIF_CFG_DEV0_RC_PREF_BASE_UPPER 0x0028 +#define cfgBIF_CFG_DEV0_RC_PREF_LIMIT_UPPER 0x002c +#define cfgBIF_CFG_DEV0_RC_IO_BASE_LIMIT_HI 0x0030 +#define cfgBIF_CFG_DEV0_RC_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_RC_ROM_BASE_ADDR 0x0038 +#define cfgBIF_CFG_DEV0_RC_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_RC_INTERRUPT_PIN 0x003d +#define cfgIRQ_BRIDGE_CNTL 0x003e +#define cfgBIF_CFG_DEV0_RC_EXT_BRIDGE_CNTL 0x0040 +#define cfgBIF_CFG_DEV0_RC_PMI_CAP_LIST 0x0050 +#define cfgBIF_CFG_DEV0_RC_PMI_CAP 0x0052 +#define cfgBIF_CFG_DEV0_RC_PMI_STATUS_CNTL 0x0054 +#define cfgBIF_CFG_DEV0_RC_PCIE_CAP_LIST 0x0058 +#define cfgBIF_CFG_DEV0_RC_PCIE_CAP 0x005a +#define cfgBIF_CFG_DEV0_RC_DEVICE_CAP 0x005c +#define cfgBIF_CFG_DEV0_RC_DEVICE_CNTL 0x0060 +#define cfgBIF_CFG_DEV0_RC_DEVICE_STATUS 0x0062 +#define cfgBIF_CFG_DEV0_RC_LINK_CAP 0x0064 +#define cfgBIF_CFG_DEV0_RC_LINK_CNTL 0x0068 +#define cfgBIF_CFG_DEV0_RC_LINK_STATUS 0x006a +#define cfgBIF_CFG_DEV0_RC_SLOT_CAP 0x006c +#define cfgBIF_CFG_DEV0_RC_SLOT_CNTL 0x0070 +#define cfgBIF_CFG_DEV0_RC_SLOT_STATUS 0x0072 +#define cfgBIF_CFG_DEV0_RC_ROOT_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_RC_ROOT_CAP 0x0076 +#define cfgBIF_CFG_DEV0_RC_ROOT_STATUS 0x0078 +#define cfgBIF_CFG_DEV0_RC_DEVICE_CAP2 0x007c +#define cfgBIF_CFG_DEV0_RC_DEVICE_CNTL2 0x0080 +#define cfgBIF_CFG_DEV0_RC_DEVICE_STATUS2 0x0082 +#define cfgBIF_CFG_DEV0_RC_LINK_CAP2 0x0084 +#define cfgBIF_CFG_DEV0_RC_LINK_CNTL2 0x0088 +#define cfgBIF_CFG_DEV0_RC_LINK_STATUS2 0x008a +#define cfgBIF_CFG_DEV0_RC_SLOT_CAP2 0x008c +#define cfgBIF_CFG_DEV0_RC_SLOT_CNTL2 0x0090 +#define cfgBIF_CFG_DEV0_RC_SLOT_STATUS2 0x0092 +#define cfgBIF_CFG_DEV0_RC_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_RC_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_RC_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_RC_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_RC_SSID_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_RC_SSID_CAP 0x00c4 +#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST 0x0110 +#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1 0x0114 +#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2 0x0118 +#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL 0x011c +#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS 0x011e +#define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP 0x0120 +#define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL 0x0124 +#define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS 0x012a +#define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP 0x012c +#define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL 0x0130 +#define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS 0x0136 +#define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 +#define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1 0x0144 +#define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2 0x0148 +#define cfgBIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_RC_PCIE_ROOT_ERR_CMD 0x017c +#define cfgBIF_CFG_DEV0_RC_PCIE_ROOT_ERR_STATUS 0x0180 +#define cfgBIF_CFG_DEV0_RC_PCIE_ERR_SRC_ID 0x0184 +#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 +#define cfgBIF_CFG_DEV0_RC_PCIE_LINK_CNTL3 0x0274 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS 0x0278 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 +#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a +#define cfgBIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST 0x02a0 +#define cfgBIF_CFG_DEV0_RC_PCIE_ACS_CAP 0x02a4 +#define cfgBIF_CFG_DEV0_RC_PCIE_ACS_CNTL 0x02a6 +#define cfgBIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST 0x0400 +#define cfgBIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP 0x0404 +#define cfgBIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS 0x0408 +#define cfgBIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 +#define cfgBIF_CFG_DEV0_RC_LINK_CAP_16GT 0x0414 +#define cfgBIF_CFG_DEV0_RC_LINK_CNTL_16GT 0x0418 +#define cfgBIF_CFG_DEV0_RC_LINK_STATUS_16GT 0x041c +#define cfgBIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 +#define cfgBIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 +#define cfgBIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 +#define cfgBIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 +#define cfgBIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 +#define cfgBIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 +#define cfgBIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 +#define cfgBIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 +#define cfgBIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 +#define cfgBIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 +#define cfgBIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 +#define cfgBIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 +#define cfgBIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 +#define cfgBIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT 0x043a +#define cfgBIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT 0x043b +#define cfgBIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT 0x043c +#define cfgBIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT 0x043d +#define cfgBIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT 0x043e +#define cfgBIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT 0x043f +#define cfgBIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST 0x0450 +#define cfgBIF_CFG_DEV0_RC_MARGINING_PORT_CAP 0x0454 +#define cfgBIF_CFG_DEV0_RC_MARGINING_PORT_STATUS 0x0456 +#define cfgBIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL 0x0458 +#define cfgBIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS 0x045a +#define cfgBIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL 0x045c +#define cfgBIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS 0x045e +#define cfgBIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL 0x0460 +#define cfgBIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS 0x0462 +#define cfgBIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL 0x0464 +#define cfgBIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS 0x0466 +#define cfgBIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL 0x0468 +#define cfgBIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS 0x046a +#define cfgBIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL 0x046c +#define cfgBIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS 0x046e +#define cfgBIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL 0x0470 +#define cfgBIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS 0x0472 +#define cfgBIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL 0x0474 +#define cfgBIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS 0x0476 +#define cfgBIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL 0x0478 +#define cfgBIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS 0x047a +#define cfgBIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL 0x047c +#define cfgBIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS 0x047e +#define cfgBIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL 0x0480 +#define cfgBIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS 0x0482 +#define cfgBIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL 0x0484 +#define cfgBIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS 0x0486 +#define cfgBIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL 0x0488 +#define cfgBIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS 0x048a +#define cfgBIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL 0x048c +#define cfgBIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS 0x048e +#define cfgBIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL 0x0490 +#define cfgBIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS 0x0492 +#define cfgBIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL 0x0494 +#define cfgBIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS 0x0496 +#define cfgBIF_CFG_DEV0_RC_LINK_CAP_32GT 0x0504 +#define cfgBIF_CFG_DEV0_RC_LINK_CNTL_32GT 0x0508 +#define cfgBIF_CFG_DEV0_RC_LINK_STATUS_32GT 0x050c + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF0_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF0_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF0_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF0_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF0_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF0_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF0_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL 0x032e + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF1_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF1_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF1_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF1_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF1_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF1_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF1_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL 0x032e + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF2_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF2_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF2_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF2_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF2_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF2_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF2_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL 0x032e + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF3_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF3_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF3_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF3_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF3_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF3_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF3_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL 0x032e + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF4_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF4_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF4_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF4_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF4_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF4_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF4_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL 0x032e + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF5_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF5_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF5_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF5_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF5_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF5_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF5_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL 0x032e + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF6_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF6_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF6_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF6_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF6_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF6_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF6_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL 0x032e + + +// addressBlock: aid_nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp +// base address: 0x0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID 0x0000 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID 0x0002 +#define cfgBIF_CFG_DEV0_EPF0_VF7_COMMAND 0x0004 +#define cfgBIF_CFG_DEV0_EPF0_VF7_STATUS 0x0006 +#define cfgBIF_CFG_DEV0_EPF0_VF7_REVISION_ID 0x0008 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE 0x0009 +#define cfgBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS 0x000a +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS 0x000b +#define cfgBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE 0x000c +#define cfgBIF_CFG_DEV0_EPF0_VF7_LATENCY 0x000d +#define cfgBIF_CFG_DEV0_EPF0_VF7_HEADER 0x000e +#define cfgBIF_CFG_DEV0_EPF0_VF7_BIST 0x000f +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1 0x0010 +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2 0x0014 +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3 0x0018 +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4 0x001c +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5 0x0020 +#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6 0x0024 +#define cfgBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR 0x0028 +#define cfgBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID 0x002c +#define cfgBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR 0x0030 +#define cfgBIF_CFG_DEV0_EPF0_VF7_CAP_PTR 0x0034 +#define cfgBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE 0x003c +#define cfgBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN 0x003d +#define cfgBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT 0x003e +#define cfgBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY 0x003f +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST 0x0064 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP 0x0066 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP 0x0068 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL 0x006c +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS 0x006e +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CAP 0x0070 +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL 0x0074 +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS 0x0076 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2 0x0088 +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2 0x008c +#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2 0x008e +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2 0x0090 +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2 0x0094 +#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2 0x0096 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST 0x00a0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL 0x00a2 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO 0x00a4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA 0x00a8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA 0x00aa +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MASK 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64 0x00ac +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64 0x00ae +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING 0x00b0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64 0x00b4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST 0x00c0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL 0x00c2 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE 0x00c4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA 0x00c8 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR 0x0104 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1 0x0108 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2 0x010c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS 0x0154 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK 0x0158 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY 0x015c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS 0x0160 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK 0x0164 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL 0x0168 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0 0x016c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1 0x0170 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2 0x0174 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3 0x0178 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0 0x0188 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1 0x018c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2 0x0190 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3 0x0194 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST 0x02b0 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP 0x02b4 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL 0x02b6 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST 0x0328 +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP 0x032c +#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL 0x032e + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF0_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF0_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA_BASE_IDX 4 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF1_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF1_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA_BASE_IDX 4 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF2_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF2_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA_BASE_IDX 4 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF3_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF3_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA_BASE_IDX 4 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF4_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF4_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA_BASE_IDX 4 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF5_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF5_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA_BASE_IDX 4 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF6_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF6_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA_BASE_IDX 4 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS 0x00eb +#define regBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG 0x00ec +#define regBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 +#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 +#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 +#define regBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 +#define regBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 +#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL 0x00f9 +#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL 0x00fa +#define regBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ 0x0106 +#define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE 0x0107 +#define regBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING 0x0108 +#define regBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 +#define regBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 0x0136 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 0x0137 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 0x0138 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 0x0139 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 0x013a +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 0x013b +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 0x013c +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 0x013d +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL 0x013e +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL 0x013f +#define regBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_BASE_IDX 2 +#define regBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX 0x0140 +#define regBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC +// base address: 0x0 +#define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX 0x0000 +#define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF7_MM_DATA 0x0001 +#define regBIF_BX_DEV0_EPF0_VF7_MM_DATA_BASE_IDX 0 +#define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI 0x0006 +#define regBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_BASE_IDX 0 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG 0x0085 +#define regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN 0x00c0 +#define regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE 0x00c3 +#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED 0x00c4 +#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED_BASE_IDX 2 +#define regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER 0x00c5 +#define regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 + + +// addressBlock: aid_nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2 +// base address: 0x0 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO 0x0400 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI 0x0401 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA 0x0402 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL 0x0403 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO 0x0404 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI 0x0405 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA 0x0406 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL 0x0407 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO 0x0408 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI 0x0409 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA 0x040a +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL 0x040b +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO 0x040c +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI 0x040d +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA 0x040e +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL 0x040f +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL_BASE_IDX 4 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA 0x0800 +#define regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA_BASE_IDX 4 + + +#endif |