diff options
Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h')
| -rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 106 |
1 files changed, 39 insertions, 67 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index e6590302b3bf..71584cd56fd7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -19,47 +19,6 @@ */ #define MAX_BLOCKS 12 -#define DPU_HW_VER(MAJOR, MINOR, STEP) (((MAJOR & 0xF) << 28) |\ - ((MINOR & 0xFFF) << 16) |\ - (STEP & 0xFFFF)) - -#define DPU_HW_MAJOR(rev) ((rev) >> 28) -#define DPU_HW_MINOR(rev) (((rev) >> 16) & 0xFFF) -#define DPU_HW_STEP(rev) ((rev) & 0xFFFF) -#define DPU_HW_MAJOR_MINOR(rev) ((rev) >> 16) - -#define IS_DPU_MAJOR_MINOR_SAME(rev1, rev2) \ - (DPU_HW_MAJOR_MINOR((rev1)) == DPU_HW_MAJOR_MINOR((rev2))) - -#define DPU_HW_VER_170 DPU_HW_VER(1, 7, 0) /* 8996 v1.0 */ -#define DPU_HW_VER_171 DPU_HW_VER(1, 7, 1) /* 8996 v2.0 */ -#define DPU_HW_VER_172 DPU_HW_VER(1, 7, 2) /* 8996 v3.0 */ -#define DPU_HW_VER_300 DPU_HW_VER(3, 0, 0) /* 8998 v1.0 */ -#define DPU_HW_VER_301 DPU_HW_VER(3, 0, 1) /* 8998 v1.1 */ -#define DPU_HW_VER_400 DPU_HW_VER(4, 0, 0) /* sdm845 v1.0 */ -#define DPU_HW_VER_401 DPU_HW_VER(4, 0, 1) /* sdm845 v2.0 */ -#define DPU_HW_VER_410 DPU_HW_VER(4, 1, 0) /* sdm670 v1.0 */ -#define DPU_HW_VER_500 DPU_HW_VER(5, 0, 0) /* sm8150 v1.0 */ -#define DPU_HW_VER_501 DPU_HW_VER(5, 0, 1) /* sm8150 v2.0 */ -#define DPU_HW_VER_510 DPU_HW_VER(5, 1, 1) /* sc8180 */ -#define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */ -#define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */ -#define DPU_HW_VER_630 DPU_HW_VER(6, 3, 0) /* sm6115|sm4250 */ -#define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */ -#define DPU_HW_VER_700 DPU_HW_VER(7, 0, 0) /* sm8350 */ -#define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */ -#define DPU_HW_VER_800 DPU_HW_VER(8, 0, 0) /* sc8280xp */ -#define DPU_HW_VER_810 DPU_HW_VER(8, 1, 0) /* sm8450 */ -#define DPU_HW_VER_900 DPU_HW_VER(9, 0, 0) /* sm8550 */ - -#define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170) -#define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300) -#define IS_SDM845_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_400) -#define IS_SDM670_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_410) -#define IS_SDM855_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_500) -#define IS_SC7180_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_620) -#define IS_SC7280_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_720) - #define DPU_HW_BLK_NAME_LEN 16 #define MAX_IMG_WIDTH 0x3fff @@ -169,10 +128,12 @@ enum { * DSPP sub-blocks * @DPU_DSPP_PCC Panel color correction block * @DPU_DSPP_GC Gamma correction block + * @DPU_DSPP_IGC Inverse gamma correction block */ enum { DPU_DSPP_PCC = 0x1, DPU_DSPP_GC, + DPU_DSPP_IGC, DPU_DSPP_MAX }; @@ -200,6 +161,7 @@ enum { * @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs) * @DPU_CTL_VM_CFG: CTL config to support multiple VMs * @DPU_CTL_HAS_LAYER_EXT4: CTL has the CTL_LAYER_EXT4 register + * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush * @DPU_CTL_MAX */ enum { @@ -208,22 +170,25 @@ enum { DPU_CTL_FETCH_ACTIVE, DPU_CTL_VM_CFG, DPU_CTL_HAS_LAYER_EXT4, + DPU_CTL_DSPP_SUB_BLOCK_FLUSH, DPU_CTL_MAX }; /** * INTF sub-blocks - * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which - * pixel data arrives to this INTF - * @DPU_INTF_TE INTF block has TE configuration support - * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate - than video timing + * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which + * pixel data arrives to this INTF + * @DPU_INTF_TE INTF block has TE configuration support + * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate + * than video timing + * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register * @DPU_INTF_MAX */ enum { DPU_INTF_INPUT_CTRL = 0x1, DPU_INTF_TE, DPU_DATA_HCTL_EN, + DPU_INTF_STATUS_SUPPORTED, DPU_INTF_MAX }; @@ -393,8 +358,6 @@ struct dpu_rotation_cfg { * @max_mixer_blendstages max layer mixer blend stages or * supported z order * @qseed_type qseed2 or qseed3 support. - * @smart_dma_rev Supported version of SmartDMA feature. - * @ubwc_version UBWC feature version (0x0 for not supported) * @has_src_split source split feature status * @has_dim_layer dim layer feature status * @has_idle_pc indicate if idle power collapse feature is supported @@ -408,8 +371,6 @@ struct dpu_caps { u32 max_mixer_width; u32 max_mixer_blendstages; u32 qseed_type; - u32 smart_dma_rev; - u32 ubwc_version; bool has_src_split; bool has_dim_layer; bool has_idle_pc; @@ -538,15 +499,24 @@ struct dpu_clk_ctrl_reg { * @id: index identifying this block * @base: register base offset to mdss * @features bit mask identifying sub-blocks/features - * @highest_bank_bit: UBWC parameter - * @ubwc_swizzle: ubwc default swizzle setting * @clk_ctrls clock control register definition */ struct dpu_mdp_cfg { DPU_HW_BLK_INFO; + struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX]; +}; + +/** + * struct dpu_ubwc_cfg - UBWC and memory configuration + * + * @ubwc_version UBWC feature version (0x0 for not supported) + * @highest_bank_bit: UBWC parameter + * @ubwc_swizzle: ubwc default swizzle setting + */ +struct dpu_ubwc_cfg { + u32 ubwc_version; u32 highest_bank_bit; u32 ubwc_swizzle; - struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX]; }; /* struct dpu_ctl_cfg : MDP CTL instance info @@ -848,6 +818,8 @@ struct dpu_perf_cfg { struct dpu_mdss_cfg { const struct dpu_caps *caps; + const struct dpu_ubwc_cfg *ubwc; + u32 mdp_count; const struct dpu_mdp_cfg *mdp; @@ -867,7 +839,7 @@ struct dpu_mdss_cfg { const struct dpu_merge_3d_cfg *merge_3d; u32 dsc_count; - struct dpu_dsc_cfg *dsc; + const struct dpu_dsc_cfg *dsc; u32 intf_count; const struct dpu_intf_cfg *intf; @@ -896,18 +868,18 @@ struct dpu_mdss_cfg { unsigned long mdss_irqs; }; -struct dpu_mdss_hw_cfg_handler { - u32 hw_rev; - const struct dpu_mdss_cfg *dpu_cfg; -}; - -/** - * dpu_hw_catalog_init - dpu hardware catalog init API retrieves - * hardcoded target specific catalog information in config structure - * @hw_rev: caller needs provide the hardware revision. - * - * Return: dpu config structure - */ -const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev); +extern const struct dpu_mdss_cfg dpu_msm8998_cfg; +extern const struct dpu_mdss_cfg dpu_sdm845_cfg; +extern const struct dpu_mdss_cfg dpu_sm8150_cfg; +extern const struct dpu_mdss_cfg dpu_sc8180x_cfg; +extern const struct dpu_mdss_cfg dpu_sm8250_cfg; +extern const struct dpu_mdss_cfg dpu_sc7180_cfg; +extern const struct dpu_mdss_cfg dpu_sm6115_cfg; +extern const struct dpu_mdss_cfg dpu_qcm2290_cfg; +extern const struct dpu_mdss_cfg dpu_sm8350_cfg; +extern const struct dpu_mdss_cfg dpu_sc7280_cfg; +extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg; +extern const struct dpu_mdss_cfg dpu_sm8450_cfg; +extern const struct dpu_mdss_cfg dpu_sm8550_cfg; #endif /* _DPU_HW_CATALOG_H */ |