summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c')
-rw-r--r--drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c84
1 files changed, 16 insertions, 68 deletions
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index 8666da1c29e5..6300b92c65eb 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -103,15 +103,6 @@ struct dsi_pll_10nm {
struct dsi_pll_config pll_configuration;
struct dsi_pll_regs reg_setup;
- /* private clocks: */
- struct clk_hw *out_div_clk_hw;
- struct clk_hw *bit_clk_hw;
- struct clk_hw *byte_clk_hw;
- struct clk_hw *by_2_bit_clk_hw;
- struct clk_hw *post_out_div_clk_hw;
- struct clk_hw *pclk_mux_hw;
- struct clk_hw *out_dsiclk_hw;
-
struct pll_10nm_cached_state cached_state;
enum msm_dsi_phy_usecase uc;
@@ -614,22 +605,6 @@ static int dsi_pll_10nm_set_usecase(struct msm_dsi_pll *pll,
return 0;
}
-static void dsi_pll_10nm_destroy(struct msm_dsi_pll *pll)
-{
- struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
-
- DBG("DSI PLL%d", pll_10nm->id);
-
- clk_hw_unregister_divider(pll_10nm->out_dsiclk_hw);
- clk_hw_unregister_mux(pll_10nm->pclk_mux_hw);
- clk_hw_unregister_fixed_factor(pll_10nm->post_out_div_clk_hw);
- clk_hw_unregister_fixed_factor(pll_10nm->by_2_bit_clk_hw);
- clk_hw_unregister_fixed_factor(pll_10nm->byte_clk_hw);
- clk_hw_unregister_divider(pll_10nm->bit_clk_hw);
- clk_hw_unregister_divider(pll_10nm->out_div_clk_hw);
- clk_hw_unregister(&pll_10nm->base.clk_hw);
-}
-
/*
* The post dividers and mux clocks are created using the standard divider and
* mux API. Unlike the 14nm PHY, the slave PLL doesn't need its dividers/mux
@@ -656,30 +631,28 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov
snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->id);
pll_10nm->base.clk_hw.init = &vco_init;
- ret = clk_hw_register(dev, &pll_10nm->base.clk_hw);
+ ret = devm_clk_hw_register(dev, &pll_10nm->base.clk_hw);
if (ret)
return ret;
snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
snprintf(parent, 32, "dsi%dvco_clk", pll_10nm->id);
- hw = clk_hw_register_divider(dev, clk_name,
+ hw = devm_clk_hw_register_divider(dev, clk_name,
parent, CLK_SET_RATE_PARENT,
pll_10nm->mmio +
REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE,
0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto err_base_clk_hw;
+ goto fail;
}
- pll_10nm->out_div_clk_hw = hw;
-
snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
/* BIT CLK: DIV_CTRL_3_0 */
- hw = clk_hw_register_divider(dev, clk_name, parent,
+ hw = devm_clk_hw_register_divider(dev, clk_name, parent,
CLK_SET_RATE_PARENT,
pll_10nm->phy_cmn_mmio +
REG_DSI_10nm_PHY_CMN_CLK_CFG0,
@@ -687,56 +660,49 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov
&pll_10nm->postdiv_lock);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto err_out_div_clk_hw;
+ goto fail;
}
- pll_10nm->bit_clk_hw = hw;
-
snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_10nm->id);
snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
/* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
- hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
+ hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
CLK_SET_RATE_PARENT, 1, 8);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto err_bit_clk_hw;
+ goto fail;
}
- pll_10nm->byte_clk_hw = hw;
provided_clocks[DSI_BYTE_PLL_CLK] = hw;
snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id);
snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
- hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
+ hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
0, 1, 2);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto err_byte_clk_hw;
+ goto fail;
}
- pll_10nm->by_2_bit_clk_hw = hw;
-
snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id);
snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
- hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
+ hw = devm_clk_hw_register_fixed_factor(dev, clk_name, parent,
0, 1, 4);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto err_by_2_bit_clk_hw;
+ goto fail;
}
- pll_10nm->post_out_div_clk_hw = hw;
-
snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_10nm->id);
snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id);
snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id);
- hw = clk_hw_register_mux(dev, clk_name,
+ hw = devm_clk_hw_register_mux(dev, clk_name,
((const char *[]){
parent, parent2, parent3, parent4
}), 4, 0, pll_10nm->phy_cmn_mmio +
@@ -744,44 +710,28 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov
0, 2, 0, NULL);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto err_post_out_div_clk_hw;
+ goto fail;
}
- pll_10nm->pclk_mux_hw = hw;
-
snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_10nm->id);
snprintf(parent, 32, "dsi%d_pclk_mux", pll_10nm->id);
/* PIX CLK DIV : DIV_CTRL_7_4*/
- hw = clk_hw_register_divider(dev, clk_name, parent,
+ hw = devm_clk_hw_register_divider(dev, clk_name, parent,
0, pll_10nm->phy_cmn_mmio +
REG_DSI_10nm_PHY_CMN_CLK_CFG0,
4, 4, CLK_DIVIDER_ONE_BASED,
&pll_10nm->postdiv_lock);
if (IS_ERR(hw)) {
ret = PTR_ERR(hw);
- goto err_pclk_mux_hw;
+ goto fail;
}
- pll_10nm->out_dsiclk_hw = hw;
provided_clocks[DSI_PIXEL_PLL_CLK] = hw;
return 0;
-err_pclk_mux_hw:
- clk_hw_unregister_mux(pll_10nm->pclk_mux_hw);
-err_post_out_div_clk_hw:
- clk_hw_unregister_fixed_factor(pll_10nm->post_out_div_clk_hw);
-err_by_2_bit_clk_hw:
- clk_hw_unregister_fixed_factor(pll_10nm->by_2_bit_clk_hw);
-err_byte_clk_hw:
- clk_hw_unregister_fixed_factor(pll_10nm->byte_clk_hw);
-err_bit_clk_hw:
- clk_hw_unregister_divider(pll_10nm->bit_clk_hw);
-err_out_div_clk_hw:
- clk_hw_unregister_divider(pll_10nm->out_div_clk_hw);
-err_base_clk_hw:
- clk_hw_unregister(&pll_10nm->base.clk_hw);
+fail:
return ret;
}
@@ -1060,7 +1010,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs = {
.pll_init = dsi_pll_10nm_init,
},
.pll_ops = {
- .destroy = dsi_pll_10nm_destroy,
.save_state = dsi_pll_10nm_save_state,
.restore_state = dsi_pll_10nm_restore_state,
},
@@ -1085,7 +1034,6 @@ const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs = {
.pll_init = dsi_pll_10nm_init,
},
.pll_ops = {
- .destroy = dsi_pll_10nm_destroy,
.save_state = dsi_pll_10nm_save_state,
.restore_state = dsi_pll_10nm_restore_state,
},
generated by cgit v1.2.3 (git 2.46.0) at 2025-08-23 11:45:49 +0000