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path: root/sound/soc/fsl/fsl_spdif.c
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Diffstat (limited to 'sound/soc/fsl/fsl_spdif.c')
-rw-r--r--sound/soc/fsl/fsl_spdif.c97
1 files changed, 74 insertions, 23 deletions
diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c
index d178b479c8bd..42d11aca38a1 100644
--- a/sound/soc/fsl/fsl_spdif.c
+++ b/sound/soc/fsl/fsl_spdif.c
@@ -50,6 +50,7 @@ static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb };
* @shared_root_clock: flag of sharing a clock source with others;
* so the driver shouldn't set root clock rate
* @raw_capture_mode: if raw capture mode support
+ * @cchannel_192b: if there are registers for 192bits C channel data
* @interrupts: interrupt number
* @tx_burst: tx maxburst size
* @rx_burst: rx maxburst size
@@ -59,6 +60,7 @@ struct fsl_spdif_soc_data {
bool imx;
bool shared_root_clock;
bool raw_capture_mode;
+ bool cchannel_192b;
u32 interrupts;
u32 tx_burst;
u32 rx_burst;
@@ -125,7 +127,7 @@ struct fsl_spdif_priv {
u16 sysclk_df[SPDIF_TXRATE_MAX];
u8 txclk_src[SPDIF_TXRATE_MAX];
u8 rxclk_src;
- struct clk *txclk[SPDIF_TXRATE_MAX];
+ struct clk *txclk[STC_TXCLK_SRC_MAX];
struct clk *rxclk;
struct clk *coreclk;
struct clk *sysclk;
@@ -196,6 +198,7 @@ static struct fsl_spdif_soc_data fsl_spdif_imx8ulp = {
.tx_burst = 2, /* Applied for EDMA */
.rx_burst = 2, /* Applied for EDMA */
.tx_formats = SNDRV_PCM_FMTBIT_S24_LE, /* Applied for EDMA */
+ .cchannel_192b = true,
};
/* Check if clk is a root clock that does not share clock source with others */
@@ -441,6 +444,23 @@ static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv)
regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);
dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);
+
+ if (spdif_priv->soc->cchannel_192b) {
+ ch_status = (bitrev8(ctrl->ch_status[0]) << 24) |
+ (bitrev8(ctrl->ch_status[1]) << 16) |
+ (bitrev8(ctrl->ch_status[2]) << 8) |
+ bitrev8(ctrl->ch_status[3]);
+
+ regmap_update_bits(regmap, REG_SPDIF_SCR, 0x1000000, 0x1000000);
+
+ /*
+ * The first 32bit should be in REG_SPDIF_STCCA_31_0 register,
+ * but here we need to set REG_SPDIF_STCCA_191_160 on 8ULP
+ * then can get correct result with HDMI analyzer capture.
+ * There is a hardware bug here.
+ */
+ regmap_write(regmap, REG_SPDIF_STCCA_191_160, ch_status);
+ }
}
/* Set SPDIF PhaseConfig register for rx clock */
@@ -526,7 +546,7 @@ static int spdif_set_sample_rate(struct snd_pcm_substream *substream,
goto clk_set_bypass;
/* The S/PDIF block needs a clock of 64 * fs * txclk_df */
- ret = clk_set_rate(spdif_priv->txclk[rate],
+ ret = clk_set_rate(spdif_priv->txclk[clk],
64 * sample_rate * txclk_df);
if (ret) {
dev_err(&pdev->dev, "failed to set tx clock rate\n");
@@ -537,7 +557,7 @@ clk_set_bypass:
dev_dbg(&pdev->dev, "expected clock rate = %d\n",
(64 * sample_rate * txclk_df * sysclk_df));
dev_dbg(&pdev->dev, "actual clock rate = %ld\n",
- clk_get_rate(spdif_priv->txclk[rate]));
+ clk_get_rate(spdif_priv->txclk[clk]));
/* set fs field in consumer channel status */
spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs);
@@ -610,6 +630,8 @@ static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
SCR_TXFIFO_FSEL_MASK;
+ /* Disable TX clock */
+ regmap_update_bits(regmap, REG_SPDIF_STC, STC_TXCLK_ALL_EN_MASK, 0);
} else {
scr = SCR_RXFIFO_OFF | SCR_RXFIFO_CTL_ZERO;
mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
@@ -1227,6 +1249,8 @@ static const struct reg_default fsl_spdif_reg_defaults[] = {
{REG_SPDIF_STR, 0x00000000},
{REG_SPDIF_STCSCH, 0x00000000},
{REG_SPDIF_STCSCL, 0x00000000},
+ {REG_SPDIF_STCSPH, 0x00000000},
+ {REG_SPDIF_STCSPL, 0x00000000},
{REG_SPDIF_STC, 0x00020f00},
};
@@ -1246,8 +1270,22 @@ static bool fsl_spdif_readable_reg(struct device *dev, unsigned int reg)
case REG_SPDIF_SRQ:
case REG_SPDIF_STCSCH:
case REG_SPDIF_STCSCL:
+ case REG_SPDIF_STCSPH:
+ case REG_SPDIF_STCSPL:
case REG_SPDIF_SRFM:
case REG_SPDIF_STC:
+ case REG_SPDIF_SRCCA_31_0:
+ case REG_SPDIF_SRCCA_63_32:
+ case REG_SPDIF_SRCCA_95_64:
+ case REG_SPDIF_SRCCA_127_96:
+ case REG_SPDIF_SRCCA_159_128:
+ case REG_SPDIF_SRCCA_191_160:
+ case REG_SPDIF_STCCA_31_0:
+ case REG_SPDIF_STCCA_63_32:
+ case REG_SPDIF_STCCA_95_64:
+ case REG_SPDIF_STCCA_127_96:
+ case REG_SPDIF_STCCA_159_128:
+ case REG_SPDIF_STCCA_191_160:
return true;
default:
return false;
@@ -1266,6 +1304,12 @@ static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg)
case REG_SPDIF_SRU:
case REG_SPDIF_SRQ:
case REG_SPDIF_SRFM:
+ case REG_SPDIF_SRCCA_31_0:
+ case REG_SPDIF_SRCCA_63_32:
+ case REG_SPDIF_SRCCA_95_64:
+ case REG_SPDIF_SRCCA_127_96:
+ case REG_SPDIF_SRCCA_159_128:
+ case REG_SPDIF_SRCCA_191_160:
return true;
default:
return false;
@@ -1284,7 +1328,15 @@ static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg)
case REG_SPDIF_STR:
case REG_SPDIF_STCSCH:
case REG_SPDIF_STCSCL:
+ case REG_SPDIF_STCSPH:
+ case REG_SPDIF_STCSPL:
case REG_SPDIF_STC:
+ case REG_SPDIF_STCCA_31_0:
+ case REG_SPDIF_STCCA_63_32:
+ case REG_SPDIF_STCCA_95_64:
+ case REG_SPDIF_STCCA_127_96:
+ case REG_SPDIF_STCCA_159_128:
+ case REG_SPDIF_STCCA_191_160:
return true;
default:
return false;
@@ -1296,7 +1348,7 @@ static const struct regmap_config fsl_spdif_regmap_config = {
.reg_stride = 4,
.val_bits = 32,
- .max_register = REG_SPDIF_STC,
+ .max_register = REG_SPDIF_STCCA_191_160,
.reg_defaults = fsl_spdif_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(fsl_spdif_reg_defaults),
.readable_reg = fsl_spdif_readable_reg,
@@ -1376,12 +1428,10 @@ static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv,
struct device *dev = &pdev->dev;
u64 savesub = 100000, ret;
struct clk *clk;
- char tmp[16];
int i;
for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
- sprintf(tmp, "rxtx%d", i);
- clk = devm_clk_get(dev, tmp);
+ clk = spdif_priv->txclk[i];
if (IS_ERR(clk)) {
dev_err(dev, "no rxtx%d clock in devicetree\n", i);
return PTR_ERR(clk);
@@ -1395,7 +1445,6 @@ static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv,
continue;
savesub = ret;
- spdif_priv->txclk[index] = clk;
spdif_priv->txclk_src[index] = i;
/* To quick catch a divisor, we allow a 0.1% deviation */
@@ -1407,7 +1456,7 @@ static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv,
spdif_priv->txclk_src[index], rate[index]);
dev_dbg(dev, "use txclk df %d for %dHz sample rate\n",
spdif_priv->txclk_df[index], rate[index]);
- if (clk_is_match(spdif_priv->txclk[index], spdif_priv->sysclk))
+ if (clk_is_match(spdif_priv->txclk[spdif_priv->txclk_src[index]], spdif_priv->sysclk))
dev_dbg(dev, "use sysclk df %d for %dHz sample rate\n",
spdif_priv->sysclk_df[index], rate[index]);
dev_dbg(dev, "the best rate for %dHz sample rate is %dHz\n",
@@ -1423,6 +1472,7 @@ static int fsl_spdif_probe(struct platform_device *pdev)
struct resource *res;
void __iomem *regs;
int irq, ret, i;
+ char tmp[16];
spdif_priv = devm_kzalloc(&pdev->dev, sizeof(*spdif_priv), GFP_KERNEL);
if (!spdif_priv)
@@ -1462,8 +1512,17 @@ static int fsl_spdif_probe(struct platform_device *pdev)
}
}
+ for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
+ sprintf(tmp, "rxtx%d", i);
+ spdif_priv->txclk[i] = devm_clk_get(&pdev->dev, tmp);
+ if (IS_ERR(spdif_priv->txclk[i])) {
+ dev_err(&pdev->dev, "no rxtx%d clock in devicetree\n", i);
+ return PTR_ERR(spdif_priv->txclk[i]);
+ }
+ }
+
/* Get system clock for rx clock rate calculation */
- spdif_priv->sysclk = devm_clk_get(&pdev->dev, "rxtx5");
+ spdif_priv->sysclk = spdif_priv->txclk[5];
if (IS_ERR(spdif_priv->sysclk)) {
dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n");
return PTR_ERR(spdif_priv->sysclk);
@@ -1481,7 +1540,7 @@ static int fsl_spdif_probe(struct platform_device *pdev)
dev_warn(&pdev->dev, "no spba clock in devicetree\n");
/* Select clock source for rx/tx clock */
- spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1");
+ spdif_priv->rxclk = spdif_priv->txclk[1];
if (IS_ERR(spdif_priv->rxclk)) {
dev_err(&pdev->dev, "no rxtx1 clock in devicetree\n");
return PTR_ERR(spdif_priv->rxclk);
@@ -1522,7 +1581,7 @@ static int fsl_spdif_probe(struct platform_device *pdev)
* Register platform component before registering cpu dai for there
* is not defer probe for platform component in snd_soc_add_pcm_runtime().
*/
- ret = imx_pcm_dma_init(pdev, IMX_SPDIF_DMABUF_SIZE);
+ ret = imx_pcm_dma_init(pdev);
if (ret) {
dev_err_probe(&pdev->dev, ret, "imx_pcm_dma_init failed\n");
goto err_pm_disable;
@@ -1562,9 +1621,7 @@ static int fsl_spdif_runtime_suspend(struct device *dev)
&spdif_priv->regcache_srpc);
regcache_cache_only(spdif_priv->regmap, true);
- clk_disable_unprepare(spdif_priv->rxclk);
-
- for (i = 0; i < SPDIF_TXRATE_MAX; i++)
+ for (i = 0; i < STC_TXCLK_SRC_MAX; i++)
clk_disable_unprepare(spdif_priv->txclk[i]);
if (!IS_ERR(spdif_priv->spbaclk))
@@ -1594,16 +1651,12 @@ static int fsl_spdif_runtime_resume(struct device *dev)
}
}
- for (i = 0; i < SPDIF_TXRATE_MAX; i++) {
+ for (i = 0; i < STC_TXCLK_SRC_MAX; i++) {
ret = clk_prepare_enable(spdif_priv->txclk[i]);
if (ret)
goto disable_tx_clk;
}
- ret = clk_prepare_enable(spdif_priv->rxclk);
- if (ret)
- goto disable_tx_clk;
-
regcache_cache_only(spdif_priv->regmap, false);
regcache_mark_dirty(spdif_priv->regmap);
@@ -1613,12 +1666,10 @@ static int fsl_spdif_runtime_resume(struct device *dev)
ret = regcache_sync(spdif_priv->regmap);
if (ret)
- goto disable_rx_clk;
+ goto disable_tx_clk;
return 0;
-disable_rx_clk:
- clk_disable_unprepare(spdif_priv->rxclk);
disable_tx_clk:
for (i--; i >= 0; i--)
clk_disable_unprepare(spdif_priv->txclk[i]);
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-18 07:51:52 +0000