summaryrefslogtreecommitdiff
path: root/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml
blob: 2491cb100b3388f25b43e1936eb622f95ac6a2ed (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,sm6115-mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SM6115 Display MDSS

maintainers:
  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

description:
  Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
  sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
  are mentioned for SM6115 target.

$ref: /schemas/display/msm/mdss-common.yaml#

properties:
  compatible:
    const: qcom,sm6115-mdss

  clocks:
    items:
      - description: Display AHB clock from gcc
      - description: Display AXI clock
      - description: Display core clock

  iommus:
    maxItems: 2

patternProperties:
  "^display-controller@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        const: qcom,sm6115-dpu

  "^dsi@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        const: qcom,dsi-ctrl-6g-qcm2290

  "^phy@[0-9a-f]+$":
    type: object
    properties:
      compatible:
        const: qcom,dsi-phy-14nm-2290

required:
  - compatible

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
    #include <dt-bindings/clock/qcom,gcc-sm6115.h>
    #include <dt-bindings/clock/qcom,rpmcc.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/qcom-rpmpd.h>

    display-subsystem@5e00000 {
        #address-cells = <1>;
        #size-cells = <1>;
        compatible = "qcom,sm6115-mdss";
        reg = <0x05e00000 0x1000>;
        reg-names = "mdss";
        power-domains = <&dispcc MDSS_GDSC>;
        clocks = <&gcc GCC_DISP_AHB_CLK>,
                 <&gcc GCC_DISP_HF_AXI_CLK>,
                 <&dispcc DISP_CC_MDSS_MDP_CLK>;

        interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <1>;

        iommus = <&apps_smmu 0x420 0x2>,
                 <&apps_smmu 0x421 0x0>;
        ranges;

        display-controller@5e01000 {
            compatible = "qcom,sm6115-dpu";
            reg = <0x05e01000 0x8f000>,
                  <0x05eb0000 0x2008>;
            reg-names = "mdp", "vbif";

            clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&dispcc DISP_CC_MDSS_MDP_CLK>,
                     <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
                     <&dispcc DISP_CC_MDSS_ROT_CLK>,
                     <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
            clock-names = "bus", "iface", "core", "lut", "rot", "vsync";

            operating-points-v2 = <&mdp_opp_table>;
            power-domains = <&rpmpd SM6115_VDDCX>;

            interrupt-parent = <&mdss>;
            interrupts = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dpu_intf1_out: endpoint {
                        remote-endpoint = <&dsi0_in>;
                    };
                };
            };
        };

        dsi@5e94000 {
            compatible = "qcom,dsi-ctrl-6g-qcm2290";
            reg = <0x05e94000 0x400>;
            reg-names = "dsi_ctrl";

            interrupt-parent = <&mdss>;
            interrupts = <4>;

            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
                     <&gcc GCC_DISP_HF_AXI_CLK>;
            clock-names = "byte",
                          "byte_intf",
                          "pixel",
                          "core",
                          "iface",
                          "bus";
            assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
            assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;

            operating-points-v2 = <&dsi_opp_table>;
            power-domains = <&rpmpd SM6115_VDDCX>;
            phys = <&dsi0_phy>;

            #address-cells = <1>;
            #size-cells = <0>;

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    dsi0_in: endpoint {
                        remote-endpoint = <&dpu_intf1_out>;
                    };
                };

                port@1 {
                    reg = <1>;
                    dsi0_out: endpoint {
                    };
                };
            };
        };

        dsi0_phy: phy@5e94400 {
            compatible = "qcom,dsi-phy-14nm-2290";
            reg = <0x05e94400 0x100>,
                  <0x05e94500 0x300>,
                  <0x05e94800 0x188>;
            reg-names = "dsi_phy",
                        "dsi_phy_lane",
                        "dsi_pll";

            #clock-cells = <1>;
            #phy-cells = <0>;

            clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
            clock-names = "iface", "ref";
        };
    };
...