blob: 7a03c6ae2afa8d71af0ea32d1fa2af46127af17e (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
|
/*
* MLBAccInt.h
*
* DSP-BIOS Bridge driver support functions for TI OMAP processors.
*
* Copyright (C) 2007 Texas Instruments, Inc.
*
* This package is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
* WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
*/
#ifndef _MLB_ACC_INT_H
#define _MLB_ACC_INT_H
/* Mappings of level 1 EASI function numbers to function names */
#define EASIL1_MLBMAILBOX_SYSCONFIGReadRegister32 (MLB_BASE_EASIL1 + 3)
#define EASIL1_MLBMAILBOX_SYSCONFIGWriteRegister32 (MLB_BASE_EASIL1 + 4)
#define EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeRead32 (MLB_BASE_EASIL1 + 7)
#define EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeWrite32 (MLB_BASE_EASIL1 + 17)
#define EASIL1_MLBMAILBOX_SYSCONFIGSoftResetWrite32 (MLB_BASE_EASIL1 + 29)
#define EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleRead32 \
(MLB_BASE_EASIL1 + 33)
#define EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleWrite32 (MLB_BASE_EASIL1 + 39)
#define EASIL1_MLBMAILBOX_SYSSTATUSResetDoneRead32 (MLB_BASE_EASIL1 + 44)
#define EASIL1_MLBMAILBOX_MESSAGE___0_15ReadRegister32 \
(MLB_BASE_EASIL1 + 50)
#define EASIL1_MLBMAILBOX_MESSAGE___0_15WriteRegister32 \
(MLB_BASE_EASIL1 + 51)
#define EASIL1_MLBMAILBOX_FIFOSTATUS___0_15ReadRegister32 \
(MLB_BASE_EASIL1 + 56)
#define EASIL1_MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32 \
(MLB_BASE_EASIL1 + 57)
#define EASIL1_MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32 \
(MLB_BASE_EASIL1 + 60)
#define EASIL1_MLBMAILBOX_IRQSTATUS___0_3ReadRegister32 \
(MLB_BASE_EASIL1 + 62)
#define EASIL1_MLBMAILBOX_IRQSTATUS___0_3WriteRegister32 \
(MLB_BASE_EASIL1 + 63)
#define EASIL1_MLBMAILBOX_IRQENABLE___0_3ReadRegister32 \
(MLB_BASE_EASIL1 + 192)
#define EASIL1_MLBMAILBOX_IRQENABLE___0_3WriteRegister32 \
(MLB_BASE_EASIL1 + 193)
/* Register set MAILBOX_MESSAGE___REGSET_0_15 address offset, bank address
* increment and number of banks */
#define MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET (u32)(0x0040)
#define MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP (u32)(0x0004)
/* Register offset address definitions relative to register set
* MAILBOX_MESSAGE___REGSET_0_15 */
#define MLB_MAILBOX_MESSAGE___0_15_OFFSET (u32)(0x0)
/* Register set MAILBOX_FIFOSTATUS___REGSET_0_15 address offset, bank address
* increment and number of banks */
#define MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET (u32)(0x0080)
#define MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP (u32)(0x0004)
/* Register offset address definitions relative to register set
* MAILBOX_FIFOSTATUS___REGSET_0_15 */
#define MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET (u32)(0x0)
/* Register set MAILBOX_MSGSTATUS___REGSET_0_15 address offset, bank address
* increment and number of banks */
#define MLB_MAILBOX_MSGSTATUS___REGSET_0_15_OFFSET (u32)(0x00c0)
#define MLB_MAILBOX_MSGSTATUS___REGSET_0_15_STEP (u32)(0x0004)
/* Register offset address definitions relative to register set
* MAILBOX_MSGSTATUS___REGSET_0_15 */
#define MLB_MAILBOX_MSGSTATUS___0_15_OFFSET (u32)(0x0)
/* Register set MAILBOX_IRQSTATUS___REGSET_0_3 address offset, bank address
* increment and number of banks */
#define MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET (u32)(0x0100)
#define MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP (u32)(0x0008)
/* Register offset address definitions relative to register set
* MAILBOX_IRQSTATUS___REGSET_0_3 */
#define MLB_MAILBOX_IRQSTATUS___0_3_OFFSET (u32)(0x0)
/* Register set MAILBOX_IRQENABLE___REGSET_0_3 address offset, bank address
* increment and number of banks */
#define MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET (u32)(0x0104)
#define MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP (u32)(0x0008)
/* Register offset address definitions relative to register set
* MAILBOX_IRQENABLE___REGSET_0_3 */
#define MLB_MAILBOX_IRQENABLE___0_3_OFFSET (u32)(0x0)
/* Register offset address definitions */
#define MLB_MAILBOX_SYSCONFIG_OFFSET (u32)(0x10)
#define MLB_MAILBOX_SYSSTATUS_OFFSET (u32)(0x14)
/* Bitfield mask and offset declarations */
#define MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK (u32)(0x18)
#define MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET (u32)(3)
#define MLB_MAILBOX_SYSCONFIG_SoftReset_MASK (u32)(0x2)
#define MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET (u32)(1)
#define MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK (u32)(0x1)
#define MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET (u32)(0)
#define MLB_MAILBOX_SYSSTATUS_ResetDone_MASK (u32)(0x1)
#define MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET (u32)(0)
#define MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_MASK (u32)(0x1)
#define MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_OFFSET (u32)(0)
#define MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_MASK (u32)(0x7f)
#define MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_OFFSET (u32)(0)
#endif /* _MLB_ACC_INT_H */
|
