summaryrefslogtreecommitdiff
path: root/sound/soc/qcom/lpass-lpaif-reg.h
blob: 6d9d9d1f6a4d94905639dbea4a02b5cc3273365e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
 */

#ifndef __LPASS_LPAIF_REG_H__
#define __LPASS_LPAIF_REG_H__

/* LPAIF I2S */

#define LPAIF_I2SCTL_REG_ADDR(v, addr, port) \
	(v->i2sctrl_reg_base + (addr) + v->i2sctrl_reg_stride * (port))

#define LPAIF_I2SCTL_REG(v, port)	LPAIF_I2SCTL_REG_ADDR(v, 0x0, (port))

#define LPAIF_I2SCTL_LOOPBACK_DISABLE	0
#define LPAIF_I2SCTL_LOOPBACK_ENABLE	1

#define LPAIF_I2SCTL_SPKEN_DISABLE	0
#define LPAIF_I2SCTL_SPKEN_ENABLE	1

#define LPAIF_I2SCTL_MODE_NONE		0
#define LPAIF_I2SCTL_MODE_SD0		1
#define LPAIF_I2SCTL_MODE_SD1		2
#define LPAIF_I2SCTL_MODE_SD2		3
#define LPAIF_I2SCTL_MODE_SD3		4
#define LPAIF_I2SCTL_MODE_QUAD01	5
#define LPAIF_I2SCTL_MODE_QUAD23	6
#define LPAIF_I2SCTL_MODE_6CH		7
#define LPAIF_I2SCTL_MODE_8CH		8
#define LPAIF_I2SCTL_MODE_10CH		9
#define LPAIF_I2SCTL_MODE_12CH		10
#define LPAIF_I2SCTL_MODE_14CH		11
#define LPAIF_I2SCTL_MODE_16CH		12
#define LPAIF_I2SCTL_MODE_SD4		13
#define LPAIF_I2SCTL_MODE_SD5		14
#define LPAIF_I2SCTL_MODE_SD6		15
#define LPAIF_I2SCTL_MODE_SD7		16
#define LPAIF_I2SCTL_MODE_QUAD45	17
#define LPAIF_I2SCTL_MODE_QUAD47	18
#define LPAIF_I2SCTL_MODE_8CH_2		19

#define LPAIF_I2SCTL_SPKMODE(mode)	mode

#define LPAIF_I2SCTL_SPKMONO_STEREO	0
#define LPAIF_I2SCTL_SPKMONO_MONO	1

#define LPAIF_I2SCTL_MICEN_DISABLE	0
#define LPAIF_I2SCTL_MICEN_ENABLE	1

#define LPAIF_I2SCTL_MICMODE(mode)	mode

#define LPAIF_I2SCTL_MICMONO_STEREO	0
#define LPAIF_I2SCTL_MICMONO_MONO	1

#define LPAIF_I2SCTL_WSSRC_INTERNAL	0
#define LPAIF_I2SCTL_WSSRC_EXTERNAL	1

#define LPAIF_I2SCTL_BITWIDTH_16	0
#define LPAIF_I2SCTL_BITWIDTH_24	1
#define LPAIF_I2SCTL_BITWIDTH_32	2

#define LPAIF_I2SCTL_RESET_STATE	0x003C0004
#define LPAIF_DMACTL_RESET_STATE	0x00200000


/* LPAIF IRQ */
#define LPAIF_IRQ_REG_ADDR(v, addr, port) \
	(v->irq_reg_base + (addr) + v->irq_reg_stride * (port))

#define LPAIF_IRQ_PORT_HOST		0

#define LPAIF_IRQEN_REG(v, port)	LPAIF_IRQ_REG_ADDR(v, 0x0, (port))
#define LPAIF_IRQSTAT_REG(v, port)	LPAIF_IRQ_REG_ADDR(v, 0x4, (port))
#define LPAIF_IRQCLEAR_REG(v, port)	LPAIF_IRQ_REG_ADDR(v, 0xC, (port))

/* LPAIF RXTX IRQ */
#define LPAIF_RXTX_IRQ_REG_ADDR(v, addr, port) \
		(v->rxtx_irq_reg_base + (addr) + v->rxtx_irq_reg_stride * (port))

#define LPAIF_RXTX_IRQEN_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0x0, port)
#define LPAIF_RXTX_IRQSTAT_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0x4, port)
#define LPAIF_RXTX_IRQCLEAR_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0xC, port)

/* LPAIF VA IRQ */
#define LPAIF_VA_IRQ_REG_ADDR(v, addr, port) \
		(v->va_irq_reg_base + (addr) + v->va_irq_reg_stride * (port))

#define LPAIF_VA_IRQEN_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0x0, port)
#define LPAIF_VA_IRQSTAT_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0x4, port)
#define LPAIF_VA_IRQCLEAR_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0xC, port)

#define LPASS_HDMITX_APP_IRQ_REG_ADDR(v, addr)  \
	((v->hdmi_irq_reg_base) + (addr))

#define LPASS_HDMITX_APP_IRQEN_REG(v)			LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0x4)
#define LPASS_HDMITX_APP_IRQSTAT_REG(v)			LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0x8)
#define LPASS_HDMITX_APP_IRQCLEAR_REG(v)		LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0xC)

#define LPAIF_IRQ_BITSTRIDE		3

#define LPAIF_IRQ_PER(chan)		(1 << (LPAIF_IRQ_BITSTRIDE * (chan)))
#define LPAIF_IRQ_XRUN(chan)		(2 << (LPAIF_IRQ_BITSTRIDE * (chan)))
#define LPAIF_IRQ_ERR(chan)		(4 << (LPAIF_IRQ_BITSTRIDE * (chan)))

#define LPAIF_IRQ_ALL(chan)		(7 << (LPAIF_IRQ_BITSTRIDE * (chan)))
#define LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(chan)	(1 << (14 + chan))
#define LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(chan)	(1 << (24 + chan))
#define LPAIF_IRQ_HDMI_METADONE		BIT(23)

/* LPAIF DMA */
#define LPAIF_HDMI_RDMA_REG_ADDR(v, addr, chan) \
	(v->hdmi_rdma_reg_base + (addr) + v->hdmi_rdma_reg_stride * (chan))

#define LPAIF_HDMI_RDMACTL_AUDINTF(id)	(id << LPAIF_RDMACTL_AUDINTF_SHIFT)

#define LPAIF_HDMI_RDMACTL_REG(v, chan)		LPAIF_HDMI_RDMA_REG_ADDR(v, 0x00, (chan))
#define LPAIF_HDMI_RDMABASE_REG(v, chan)	LPAIF_HDMI_RDMA_REG_ADDR(v, 0x04, (chan))
#define	LPAIF_HDMI_RDMABUFF_REG(v, chan)	LPAIF_HDMI_RDMA_REG_ADDR(v, 0x08, (chan))
#define LPAIF_HDMI_RDMACURR_REG(v, chan)	LPAIF_HDMI_RDMA_REG_ADDR(v, 0x0C, (chan))
#define	LPAIF_HDMI_RDMAPER_REG(v, chan)		LPAIF_HDMI_RDMA_REG_ADDR(v, 0x10, (chan))
#define	LPAIF_HDMI_RDMAPERCNT_REG(v, chan)	LPAIF_HDMI_RDMA_REG_ADDR(v, 0x14, (chan))

#define LPAIF_RDMA_REG_ADDR(v, addr, chan) \
	(v->rdma_reg_base + (addr) + v->rdma_reg_stride * (chan))

#define LPAIF_RDMACTL_AUDINTF(id)	(id << LPAIF_RDMACTL_AUDINTF_SHIFT)

#define LPAIF_RDMACTL_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x00, (chan))
#define LPAIF_RDMABASE_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x04, (chan))
#define	LPAIF_RDMABUFF_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x08, (chan))
#define LPAIF_RDMACURR_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x0C, (chan))
#define	LPAIF_RDMAPER_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x10, (chan))
#define	LPAIF_RDMAPERCNT_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x14, (chan))

#define LPAIF_WRDMA_REG_ADDR(v, addr, chan) \
	(v->wrdma_reg_base + (addr) + \
	 v->wrdma_reg_stride * (chan - v->wrdma_channel_start))

#define LPAIF_WRDMACTL_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x00, (chan))
#define LPAIF_WRDMABASE_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x04, (chan))
#define	LPAIF_WRDMABUFF_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x08, (chan))
#define LPAIF_WRDMACURR_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x0C, (chan))
#define	LPAIF_WRDMAPER_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x10, (chan))
#define	LPAIF_WRDMAPERCNT_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x14, (chan))

#define LPAIF_INTFDMA_REG(v, chan, reg, dai_id)  \
	((dai_id ==  LPASS_DP_RX) ? \
		LPAIF_HDMI_RDMA##reg##_REG(v, chan) : \
		 LPAIF_RDMA##reg##_REG(v, chan))

#define __LPAIF_DMA_REG(v, chan, dir, reg, dai_id)  \
	((dir ==  SNDRV_PCM_STREAM_PLAYBACK) ? \
		(LPAIF_INTFDMA_REG(v, chan, reg, dai_id)) : \
		LPAIF_WRDMA##reg##_REG(v, chan))

#define LPAIF_DMACTL_REG(v, chan, dir, dai_id) \
	(is_cdc_dma_port(dai_id) ? \
	__LPAIF_CDC_DMA_REG(v, chan, dir, CTL, dai_id) : \
	__LPAIF_DMA_REG(v, chan, dir, CTL, dai_id))
#define LPAIF_DMABASE_REG(v, chan, dir, dai_id) \
	(is_cdc_dma_port(dai_id) ? \
	__LPAIF_CDC_DMA_REG(v, chan, dir, BASE, dai_id) : \
	__LPAIF_DMA_REG(v, chan, dir, BASE, dai_id))
#define LPAIF_DMABUFF_REG(v, chan, dir, dai_id) \
	(is_cdc_dma_port(dai_id) ? \
	__LPAIF_CDC_DMA_REG(v, chan, dir, BUFF, dai_id) : \
	__LPAIF_DMA_REG(v, chan, dir, BUFF, dai_id))
#define LPAIF_DMACURR_REG(v, chan, dir, dai_id) \
	(is_cdc_dma_port(dai_id) ? \
	__LPAIF_CDC_DMA_REG(v, chan, dir, CURR, dai_id) : \
	__LPAIF_DMA_REG(v, chan, dir, CURR, dai_id))
#define LPAIF_DMAPER_REG(v, chan, dir, dai_id)  \
	(is_cdc_dma_port(dai_id) ? \
	__LPAIF_CDC_DMA_REG(v, chan, dir, PER, dai_id) : \
	__LPAIF_DMA_REG(v, chan, dir, PER, dai_id))
#define LPAIF_DMAPERCNT_REG(v, chan, dir, dai_id) \
	(is_cdc_dma_port(dai_id) ? \
	__LPAIF_CDC_DMA_REG(v, chan, dir, PERCNT, dai_id) : \
	__LPAIF_DMA_REG(v, chan, dir, PERCNT, dai_id))

#define LPAIF_CDC_RDMA_REG_ADDR(v, addr, chan, dai_id) \
	(is_rxtx_cdc_dma_port(dai_id) ? \
	(v->rxtx_rdma_reg_base + (addr) + v->rxtx_rdma_reg_stride * (chan)) : \
	(v->va_rdma_reg_base + (addr) + v->va_rdma_reg_stride * (chan)))

#define LPAIF_CDC_RXTX_RDMACTL_REG(v, chan, dai_id) \
		LPAIF_CDC_RDMA_REG_ADDR(v, 0x00, (chan), dai_id)
#define LPAIF_CDC_RXTX_RDMABASE_REG(v, chan, dai_id) \
		LPAIF_CDC_RDMA_REG_ADDR(v, 0x04, (chan), dai_id)
#define LPAIF_CDC_RXTX_RDMABUFF_REG(v, chan, dai_id) \
		LPAIF_CDC_RDMA_REG_ADDR(v, 0x08, (chan), dai_id)
#define LPAIF_CDC_RXTX_RDMACURR_REG(v, chan, dai_id) \
		LPAIF_CDC_RDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
#define LPAIF_CDC_RXTX_RDMAPER_REG(v, chan, dai_id) \
		LPAIF_CDC_RDMA_REG_ADDR(v, 0x10, (chan), dai_id)
#define LPAIF_CDC_RXTX_RDMA_INTF_REG(v, chan, dai_id) \
	LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan), dai_id)

#define LPAIF_CDC_VA_RDMACTL_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x00, (chan), dai_id)
#define LPAIF_CDC_VA_RDMABASE_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x04, (chan), dai_id)
#define LPAIF_CDC_VA_RDMABUFF_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x08, (chan), dai_id)
#define LPAIF_CDC_VA_RDMACURR_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
#define LPAIF_CDC_VA_RDMAPER_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x10, (chan), dai_id)
#define LPAIF_CDC_VA_RDMA_INTF_REG(v, chan, dai_id) \
	LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan), dai_id)

#define LPAIF_CDC_WRDMA_REG_ADDR(v, addr, chan, dai_id) \
	(is_rxtx_cdc_dma_port(dai_id) ? \
	(v->rxtx_wrdma_reg_base + (addr) + \
		v->rxtx_wrdma_reg_stride * (chan - v->rxtx_wrdma_channel_start)) : \
	(v->va_wrdma_reg_base + (addr) + \
		v->va_wrdma_reg_stride * (chan - v->va_wrdma_channel_start)))

#define LPAIF_CDC_RXTX_WRDMACTL_REG(v, chan, dai_id) \
	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (chan), dai_id)
#define LPAIF_CDC_RXTX_WRDMABASE_REG(v, chan, dai_id) \
	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (chan), dai_id)
#define LPAIF_CDC_RXTX_WRDMABUFF_REG(v, chan, dai_id) \
	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (chan), dai_id)
#define LPAIF_CDC_RXTX_WRDMACURR_REG(v, chan, dai_id) \
	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
#define LPAIF_CDC_RXTX_WRDMAPER_REG(v, chan, dai_id) \
	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (chan), dai_id)
#define LPAIF_CDC_RXTX_WRDMA_INTF_REG(v, chan, dai_id) \
	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (chan), dai_id)

#define LPAIF_CDC_VA_WRDMACTL_REG(v, chan, dai_id) \
	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (chan), dai_id)
#define LPAIF_CDC_VA_WRDMABASE_REG(v, chan, dai_id) \
	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (chan), dai_id)
#define LPAIF_CDC_VA_WRDMABUFF_REG(v, chan, dai_id) \
	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (chan), dai_id)
#define LPAIF_CDC_VA_WRDMACURR_REG(v, chan, dai_id) \
	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
#define LPAIF_CDC_VA_WRDMAPER_REG(v, chan, dai_id) \
	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (chan), dai_id)
#define LPAIF_CDC_VA_WRDMA_INTF_REG(v, chan, dai_id) \
	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (chan), dai_id)

#define __LPAIF_CDC_RDDMA_REG(v, chan, dir, reg, dai_id) \
		(is_rxtx_cdc_dma_port(dai_id) ? LPAIF_CDC_RXTX_RDMA##reg##_REG(v, chan, dai_id) : \
			LPAIF_CDC_VA_RDMA##reg##_REG(v, chan, dai_id))

#define __LPAIF_CDC_WRDMA_REG(v, chan, dir, reg, dai_id) \
		(is_rxtx_cdc_dma_port(dai_id) ? LPAIF_CDC_RXTX_WRDMA##reg##_REG(v, chan, dai_id) : \
			LPAIF_CDC_VA_WRDMA##reg##_REG(v, chan, dai_id))

#define __LPAIF_CDC_DMA_REG(v, chan, dir, reg, dai_id) \
		((dir ==  SNDRV_PCM_STREAM_PLAYBACK) ? \
			__LPAIF_CDC_RDDMA_REG(v, chan, dir, reg, dai_id) : \
			__LPAIF_CDC_WRDMA_REG(v, chan, dir, reg, dai_id))

#define LPAIF_CDC_INTF_REG(v, chan, dir, dai_id) \
		((dir ==  SNDRV_PCM_STREAM_PLAYBACK) ? \
		LPAIF_CDC_RDMA_INTF_REG(v, chan, dai_id) : \
		LPAIF_CDC_WRDMA_INTF_REG(v, chan, dai_id))

#define LPAIF_INTF_REG(v, chan, dir, dai_id) \
		(is_cdc_dma_port(dai_id) ? \
		LPAIF_CDC_INTF_REG(v, chan, dir, dai_id) : \
		LPAIF_DMACTL_REG(v, chan, dir, dai_id))

#define LPAIF_DMACTL_BURSTEN_SINGLE	0
#define LPAIF_DMACTL_BURSTEN_INCR4	1

#define LPAIF_DMACTL_WPSCNT_ONE		0
#define LPAIF_DMACTL_WPSCNT_TWO		1
#define LPAIF_DMACTL_WPSCNT_THREE	2
#define LPAIF_DMACTL_WPSCNT_FOUR	3
#define LPAIF_DMACTL_WPSCNT_SIX		5
#define LPAIF_DMACTL_WPSCNT_EIGHT	7
#define LPAIF_DMACTL_WPSCNT_TEN		9
#define LPAIF_DMACTL_WPSCNT_TWELVE	11
#define LPAIF_DMACTL_WPSCNT_FOURTEEN	13
#define LPAIF_DMACTL_WPSCNT_SIXTEEN	15

#define LPAIF_DMACTL_AUDINTF(id)	id

#define LPAIF_DMACTL_FIFOWM_1		0
#define LPAIF_DMACTL_FIFOWM_2		1
#define LPAIF_DMACTL_FIFOWM_3		2
#define LPAIF_DMACTL_FIFOWM_4		3
#define LPAIF_DMACTL_FIFOWM_5		4
#define LPAIF_DMACTL_FIFOWM_6		5
#define LPAIF_DMACTL_FIFOWM_7		6
#define LPAIF_DMACTL_FIFOWM_8		7
#define LPAIF_DMACTL_FIFOWM_9		8
#define LPAIF_DMACTL_FIFOWM_10		9
#define LPAIF_DMACTL_FIFOWM_11		10
#define LPAIF_DMACTL_FIFOWM_12		11
#define LPAIF_DMACTL_FIFOWM_13		12
#define LPAIF_DMACTL_FIFOWM_14		13
#define LPAIF_DMACTL_FIFOWM_15		14
#define LPAIF_DMACTL_FIFOWM_16		15
#define LPAIF_DMACTL_FIFOWM_17		16
#define LPAIF_DMACTL_FIFOWM_18		17
#define LPAIF_DMACTL_FIFOWM_19		18
#define LPAIF_DMACTL_FIFOWM_20		19
#define LPAIF_DMACTL_FIFOWM_21		20
#define LPAIF_DMACTL_FIFOWM_22		21
#define LPAIF_DMACTL_FIFOWM_23		22
#define LPAIF_DMACTL_FIFOWM_24		23
#define LPAIF_DMACTL_FIFOWM_25		24
#define LPAIF_DMACTL_FIFOWM_26		25
#define LPAIF_DMACTL_FIFOWM_27		26
#define LPAIF_DMACTL_FIFOWM_28		27
#define LPAIF_DMACTL_FIFOWM_29		28
#define LPAIF_DMACTL_FIFOWM_30		29
#define LPAIF_DMACTL_FIFOWM_31		30
#define LPAIF_DMACTL_FIFOWM_32		31

#define LPAIF_DMACTL_ENABLE_OFF		0
#define LPAIF_DMACTL_ENABLE_ON		1

#define LPAIF_DMACTL_DYNCLK_OFF		0
#define LPAIF_DMACTL_DYNCLK_ON		1

#endif /* __LPASS_LPAIF_REG_H__ */