Merge tag 'arc-4.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc

Pull ARC updates from Vineet Gupta:

 - ARCv2 support for native 64-bit atomics using LLOCK/SCONDD
   instructions

 - Support for upcoming 3.0 release of HS38 cores

 - Dwarf unwindinder improvements:
   - enable unwinding of hand written assembler code using CFI
     pseudo-ops
   - switch to .eh_frame (as opposed to historic .debug_frame)
   - get rid of a bunch of adhoc band-aids in the process

 - Misc fixes:
   - perf supporting generic cache-references and cache-misses (Alexey)
   - default NODE_SHIFT (Noam Camus)
   - usage of KFLAG instruction to set IE (Yuriy)

 - Platforms:
   - Add "model" property across the DT (Alexey)
   - Enable MODULE_* in defconfigs

* tag 'arc-4.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
  ARC: [plat*] enables MODULE*
  ARCv2: fix local_save_flags
  ARC: CONFIG_NODES_SHIFT fix default values
  ARCv2: intc: Use kflag if STATUS32.IE must be reset
  ARC: .exit.* sections can be discarded in .eh_frame regime
  ARC: dw2 unwind: enable cfi pseudo ops in string lib
  ARC: dw2 unwind: add infrastructure for adding cfi pseudo ops to asm
  ARC: entry: make ret_from_system_call local label
  ARC: dw2 unwind: don't force dwarf 2
  ARC: dw2 unwind: switch to .eh_frame based unwinding
  ARC: dw2 unwind: factor CIE specifics for .eh_frame/.debug_frame
  ARC: module: support R_ARC_32_PCREL relocation
  arc: perf: Enable generic "cache-references" and "cache-misses" events
  ARC: [plat-eznps] add missing atomic_fetch_xxx operations
  ARCv2: Implement atomic64 based on LLOCKD/SCONDD instructions
  ARCv2: Support dynamic peripheral address space in HS38 rel 3.0 cores
  ARCv2: identify HS38 rel 3.0 cores
  ARCv2: Add support for ZeBu Emulation platform for HS cores
  arc: Add "model" properly in device tree description of all boards

1 files changed, 18 insertions, 5 deletions

diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index 0b10efe3a6a7..97dddbefb86a 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -25,6 +25,7 @@ static int l2_line_sz;
 int ioc_exists;
 volatile int slc_enable = 1, ioc_enable = 1;
 unsigned long perip_base = ARC_UNCACHED_ADDR_SPACE; /* legacy value for boot */
+unsigned long perip_end = 0xFFFFFFFF; /* legacy value */
 
 void (*_cache_line_loop_ic_fn)(phys_addr_t paddr, unsigned long vaddr,
 			       unsigned long sz, const int cacheop);
@@ -76,7 +77,6 @@ char *arc_cache_mumbojumbo(int c, char *buf, int len)
 static void read_decode_cache_bcr_arcv2(int cpu)
 {
 	struct cpuinfo_arc_cache *p_slc = &cpuinfo_arc700[cpu].slc;
-	struct bcr_generic uncached_space;
 	struct bcr_generic sbcr;
 
 	struct bcr_slc_cfg {
@@ -95,6 +95,15 @@ static void read_decode_cache_bcr_arcv2(int cpu)
 #endif
 	} cbcr;
 
+	struct bcr_volatile {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+		unsigned int start:4, limit:4, pad:22, order:1, disable:1;
+#else
+		unsigned int disable:1, order:1, pad:22, limit:4, start:4;
+#endif
+	} vol;
+
+
 	READ_BCR(ARC_REG_SLC_BCR, sbcr);
 	if (sbcr.ver) {
 		READ_BCR(ARC_REG_SLC_CFG, slc_cfg);
@@ -107,10 +116,14 @@ static void read_decode_cache_bcr_arcv2(int cpu)
 	if (cbcr.c && ioc_enable)
 		ioc_exists = 1;
 
-	/* Legacy Data Uncached BCR is deprecated from v3 onwards */
-	READ_BCR(ARC_REG_D_UNCACH_BCR, uncached_space);
-	if (uncached_space.ver > 2)
-		perip_base = read_aux_reg(AUX_NON_VOL) & 0xF0000000;
+	/* HS 2.0 didn't have AUX_VOL */
+	if (cpuinfo_arc700[cpu].core.family > 0x51) {
+		READ_BCR(AUX_VOL, vol);
+		perip_base = vol.start << 28;
+		/* HS 3.0 has limit and strict-ordering fields */
+		if (cpuinfo_arc700[cpu].core.family > 0x52)
+			perip_end = (vol.limit << 28) - 1;
+	}
 }
 
 void read_decode_cache_bcr(void)