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| author | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2015-12-21 03:14:03 +0100 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2015-12-21 03:14:03 +0100 |
| commit | e219aafe50fd546b8686582ddbafd24c3c2eda04 (patch) | |
| tree | a665e08ca8d42f20ac8e5dcc8565d666cffb26bd /arch/arm/mach-omap2/vc.c | |
| parent | ffe12855a5f7f195589130197558e6a5c276caa4 (diff) | |
| parent | 24c96dc79c5e76d3cff7a33f955a4d3244644766 (diff) | |
Merge back earlier 'pm-domains' material for v4.5.
Diffstat (limited to 'arch/arm/mach-omap2/vc.c')
| -rw-r--r-- | arch/arm/mach-omap2/vc.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c index d44d311704ba..2028167fff31 100644 --- a/arch/arm/mach-omap2/vc.c +++ b/arch/arm/mach-omap2/vc.c @@ -280,10 +280,6 @@ void omap3_vc_set_pmic_signaling(int core_next_state) } } -#define PRM_POLCTRL_TWL_MASK (OMAP3430_PRM_POLCTRL_CLKREQ_POL | \ - OMAP3430_PRM_POLCTRL_CLKREQ_POL) -#define PRM_POLCTRL_TWL_VAL OMAP3430_PRM_POLCTRL_CLKREQ_POL - /* * Configure signal polarity for sys_clkreq and sys_off_mode pins * as the default values are wrong and can cause the system to hang |