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| author | Paul Mundt <lethal@linux-sh.org> | 2009-12-21 11:59:55 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2009-12-21 11:59:55 +0900 |
| commit | 76e7461a21dfe13565b2a323b53c8cc963541126 (patch) | |
| tree | 8e399c71b38bb80c00d8a82310021b55ab6e8e33 /arch/arm/mm/cache-v4wt.S | |
| parent | d0b873fc73b793277c8a0824ce986b5bfeaef157 (diff) | |
| parent | dd59f6c76b265ed2ff18b497d6105a9511b1feb1 (diff) | |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'arch/arm/mm/cache-v4wt.S')
| -rw-r--r-- | arch/arm/mm/cache-v4wt.S | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S index c54fa2cc40e6..b3b7410270b4 100644 --- a/arch/arm/mm/cache-v4wt.S +++ b/arch/arm/mm/cache-v4wt.S @@ -117,17 +117,18 @@ ENTRY(v4wt_coherent_user_range) mov pc, lr /* - * flush_kern_dcache_page(void *page) + * flush_kern_dcache_area(void *addr, size_t size) * * Ensure no D cache aliasing occurs, either with itself or * the I cache * - * - addr - page aligned address + * - addr - kernel address + * - size - region size */ -ENTRY(v4wt_flush_kern_dcache_page) +ENTRY(v4wt_flush_kern_dcache_area) mov r2, #0 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache - add r1, r0, #PAGE_SZ + add r1, r0, r1 /* fallthrough */ /* @@ -180,7 +181,7 @@ ENTRY(v4wt_cache_fns) .long v4wt_flush_user_cache_range .long v4wt_coherent_kern_range .long v4wt_coherent_user_range - .long v4wt_flush_kern_dcache_page + .long v4wt_flush_kern_dcache_area .long v4wt_dma_inv_range .long v4wt_dma_clean_range .long v4wt_dma_flush_range |