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| author | Michal Marek <mmarek@suse.cz> | 2011-06-07 15:37:51 +0200 |
|---|---|---|
| committer | Michal Marek <mmarek@suse.cz> | 2011-06-07 15:37:51 +0200 |
| commit | 2e483528cebad089d0bb3f9aebb0ada22d968ffa (patch) | |
| tree | d701405826b271e819a9a8500838cebd37b1364a /arch/arm/mm/cache-v7.S | |
| parent | 163d3fe6a2357aba7b18b938d6ae6ce9570324e4 (diff) | |
| parent | 55922c9d1b84b89cb946c777fddccb3247e7df2c (diff) | |
Merge commit 'v3.0-rc1' into kbuild/kbuild
Diffstat (limited to 'arch/arm/mm/cache-v7.S')
| -rw-r--r-- | arch/arm/mm/cache-v7.S | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 6136e68ce953..d32f02b61866 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -96,7 +96,7 @@ ENDPROC(v7_flush_dcache_all) * Flush the entire cache system. * The data cache flush is now achieved using atomic clean / invalidates * working outwards from L1 cache. This is done using Set/Way based cache - * maintainance instructions. + * maintenance instructions. * The instruction cache can still be invalidated back to the point of * unification in a single instruction. * @@ -221,6 +221,8 @@ ENDPROC(v7_coherent_user_range) ENTRY(v7_flush_kern_dcache_area) dcache_line_size r2, r3 add r1, r0, r1 + sub r3, r2, #1 + bic r0, r0, r3 1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line add r0, r0, r2 |