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| author | James Morris <james.l.morris@oracle.com> | 2012-06-10 22:52:10 +1000 |
|---|---|---|
| committer | James Morris <james.l.morris@oracle.com> | 2012-06-10 22:52:10 +1000 |
| commit | 66dd07b88a1c9d446f32253da606b87324fa620e (patch) | |
| tree | 4e0971bdd543585c7ab46716ae808a7fd82f9c35 /arch/arm/mm/cache-v7.S | |
| parent | f52c44cd27b4a0be37ef97f0466e4095ebebef3f (diff) | |
| parent | cfaf025112d3856637ff34a767ef785ef5cf2ca9 (diff) | |
Merge commit 'v3.5-rc2' into next
Diffstat (limited to 'arch/arm/mm/cache-v7.S')
| -rw-r--r-- | arch/arm/mm/cache-v7.S | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index a655d3da386d..39e3fb3db801 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -13,6 +13,7 @@ #include <linux/linkage.h> #include <linux/init.h> #include <asm/assembler.h> +#include <asm/errno.h> #include <asm/unwind.h> #include "proc-macros.S" @@ -198,7 +199,6 @@ ENTRY(v7_coherent_user_range) add r12, r12, r2 cmp r12, r1 blo 2b -3: mov r0, #0 ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB @@ -208,13 +208,11 @@ ENTRY(v7_coherent_user_range) /* * Fault handling for the cache operation above. If the virtual address in r0 - * isn't mapped, just try the next page. + * isn't mapped, fail with -EFAULT. */ 9001: - mov r12, r12, lsr #12 - mov r12, r12, lsl #12 - add r12, r12, #4096 - b 3b + mov r0, #-EFAULT + mov pc, lr UNWIND(.fnend ) ENDPROC(v7_coherent_kern_range) ENDPROC(v7_coherent_user_range) |