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| author | Grant Likely <grant.likely@secretlab.ca> | 2010-12-22 00:10:01 -0700 |
|---|---|---|
| committer | Grant Likely <grant.likely@secretlab.ca> | 2010-12-22 00:10:01 -0700 |
| commit | 752a4a95e3c96a8e8d3405b16d292f13e8c7856b (patch) | |
| tree | 838e43696fdc45b83f082eef7230d79cfe699497 /arch/arm/mm/proc-macros.S | |
| parent | bc3f67a3e1b20756d4bfa5886a6b8fd0c068e6a4 (diff) | |
| parent | 90a8a73c06cc32b609a880d48449d7083327e11a (diff) | |
Merge commit 'v2.6.37-rc7' into spi/next
Diffstat (limited to 'arch/arm/mm/proc-macros.S')
| -rw-r--r-- | arch/arm/mm/proc-macros.S | 22 |
1 files changed, 16 insertions, 6 deletions
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index 7d63beaf9745..b795afd0a2c6 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -61,17 +61,27 @@ .endm /* - * cache_line_size - get the cache line size from the CSIDR register - * (available on ARMv7+). It assumes that the CSSR register was configured - * to access the L1 data cache CSIDR. + * dcache_line_size - get the minimum D-cache line size from the CTR register + * on ARMv7. */ .macro dcache_line_size, reg, tmp - mrc p15, 1, \tmp, c0, c0, 0 @ read CSIDR - and \tmp, \tmp, #7 @ cache line size encoding - mov \reg, #16 @ size offset + mrc p15, 0, \tmp, c0, c0, 1 @ read ctr + lsr \tmp, \tmp, #16 + and \tmp, \tmp, #0xf @ cache line size encoding + mov \reg, #4 @ bytes per word mov \reg, \reg, lsl \tmp @ actual cache line size .endm +/* + * icache_line_size - get the minimum I-cache line size from the CTR register + * on ARMv7. + */ + .macro icache_line_size, reg, tmp + mrc p15, 0, \tmp, c0, c0, 1 @ read ctr + and \tmp, \tmp, #0xf @ cache line size encoding + mov \reg, #4 @ bytes per word + mov \reg, \reg, lsl \tmp @ actual cache line size + .endm /* * Sanity check the PTE configuration for the code below - which makes |