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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2011-08-29 16:33:32 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2011-08-29 16:33:32 -0700 |
| commit | 3ae627b5a6c8f6bf992eee6a3399a1854641a476 (patch) | |
| tree | 9babf0fb90fdc1369b72aa381495826bf4e80494 /arch/arm/plat-s5p/irq-gpioint.c | |
| parent | d4d7b2a11c423a8d4088bb0090e4c8d626d043bc (diff) | |
| parent | 039920ccdde7b678adcc554cbb39f185080ce2e5 (diff) | |
Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc
* 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc:
ARM: mach-footbridge: add missing header file <video/vga.h>
ARM: mach-orion5x: add missing header file <linux/vga.h>
arm: fix compile failure in orion5x/dns323-setup.c
at91: at91sam9261.c: fix typo in t2_clk alias for atmel_tcb.0
ARM: S5P: fix bug in spdif_clk_get_rate
ARM: EXYNOS4: Add restart hook for proper reboot
ARM: EXYNOS4: Increase reset delay for USB HOST PHY
ARM: S5P: add required chained_irq_enter/exit to gpio-int code
ARM: EXYNOS4: add required chained_irq_enter/exit to eint code
ARM: SAMSUNG: Add chained enrty/exit call to timer interrupt handler
ARM: S3C64XX: Fix build break in PM debug
ARM: S5PV210: Fix build warning
ARM: EXYNOS4: Fix the IRQ definitions for MIPI CSIS device
ARM: EXYNOS4: remove duplicated inclusion
ARM: EXYNOS4: Fix wrong devname to support clkdev
ARM: EXYNOS4: Use the correct regulator names on universal_c210
ARM: SAMSUNG: Fix Section mismatch in samsung_bl_set()
ARM: S5P64X0: Replace irq_gc_ack() with irq_gc_ack_set_bit()
Diffstat (limited to 'arch/arm/plat-s5p/irq-gpioint.c')
| -rw-r--r-- | arch/arm/plat-s5p/irq-gpioint.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c index 327ab9f662e8..f71078ef6bb5 100644 --- a/arch/arm/plat-s5p/irq-gpioint.c +++ b/arch/arm/plat-s5p/irq-gpioint.c @@ -23,6 +23,8 @@ #include <plat/gpio-core.h> #include <plat/gpio-cfg.h> +#include <asm/mach/irq.h> + #define GPIO_BASE(chip) (((unsigned long)(chip)->base) & 0xFFFFF000u) #define CON_OFFSET 0x700 @@ -81,6 +83,9 @@ static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc) int group, pend_offset, mask_offset; unsigned int pend, mask; + struct irq_chip *chip = irq_get_chip(irq); + chained_irq_enter(chip, desc); + for (group = 0; group < bank->nr_groups; group++) { struct s3c_gpio_chip *chip = bank->chips[group]; if (!chip) @@ -102,6 +107,7 @@ static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc) pend &= ~BIT(offset); } } + chained_irq_exit(chip, desc); } static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip) |