diff options
| author | Ingo Molnar <mingo@elte.hu> | 2008-09-10 14:05:45 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-09-10 14:05:45 +0200 |
| commit | 3ce9bcb583536c45a46c7302747029450e22279c (patch) | |
| tree | 7a4167189ffc6dc909151d1a5d040f9f0656a9f4 /arch/blackfin/include/asm/cache.h | |
| parent | 26fd10517e810dd59ea050b052de24a75ee6dc07 (diff) | |
| parent | f7d0b926ac8c8ec0c7a83ee69409bd2e6bb39f81 (diff) | |
Merge branch 'core/xen' into x86/xen
Diffstat (limited to 'arch/blackfin/include/asm/cache.h')
| -rw-r--r-- | arch/blackfin/include/asm/cache.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h new file mode 100644 index 000000000000..023d72133b5a --- /dev/null +++ b/arch/blackfin/include/asm/cache.h @@ -0,0 +1,29 @@ +/* + * include/asm-blackfin/cache.h + */ +#ifndef __ARCH_BLACKFIN_CACHE_H +#define __ARCH_BLACKFIN_CACHE_H + +/* + * Bytes per L1 cache line + * Blackfin loads 32 bytes for cache + */ +#define L1_CACHE_SHIFT 5 +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) +#define SMP_CACHE_BYTES L1_CACHE_BYTES + +/* + * Put cacheline_aliged data to L1 data memory + */ +#ifdef CONFIG_CACHELINE_ALIGNED_L1 +#define __cacheline_aligned \ + __attribute__((__aligned__(L1_CACHE_BYTES), \ + __section__(".data_l1.cacheline_aligned"))) +#endif + +/* + * largest L1 which this arch supports + */ +#define L1_CACHE_SHIFT_MAX 5 + +#endif |