diff options
| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-03-19 09:47:30 +0100 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-03-19 09:47:30 +0100 |
| commit | 0d4a42f6bd298e826620585e766a154ab460617a (patch) | |
| tree | 406d8f7778691d858dbe3e48e4bbb10e99c0a58a /arch/microblaze/pci/xilinx_pci.c | |
| parent | d62b4892f3d9f7dd2002e5309be10719d6805b0f (diff) | |
| parent | a937536b868b8369b98967929045f1df54234323 (diff) | |
Merge tag 'v3.9-rc3' into drm-intel-next-queued
Backmerge so that I can merge Imre Deak's coalesced sg entries fixes,
which depend upon the new for_each_sg_page introduce in
commit a321e91b6d73ed011ffceed384c40d2785cf723b
Author: Imre Deak <imre.deak@intel.com>
Date: Wed Feb 27 17:02:56 2013 -0800
lib/scatterlist: add simple page iterator
The merge itself is just two trivial conflicts:
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'arch/microblaze/pci/xilinx_pci.c')
| -rw-r--r-- | arch/microblaze/pci/xilinx_pci.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/microblaze/pci/xilinx_pci.c b/arch/microblaze/pci/xilinx_pci.c index 0687a42a5bd4..14c7da5fd039 100644 --- a/arch/microblaze/pci/xilinx_pci.c +++ b/arch/microblaze/pci/xilinx_pci.c @@ -18,7 +18,7 @@ #include <linux/of.h> #include <linux/of_address.h> #include <linux/pci.h> -#include <asm/io.h> +#include <linux/io.h> #define XPLB_PCI_ADDR 0x10c #define XPLB_PCI_DATA 0x110 @@ -82,7 +82,7 @@ xilinx_pci_exclude_device(struct pci_controller *hose, u_char bus, u8 devfn) * * List pci devices in very early phase. */ -void __init xilinx_early_pci_scan(struct pci_controller *hose) +static void __init xilinx_early_pci_scan(struct pci_controller *hose) { u32 bus = 0; u32 val, dev, func, offset; @@ -91,27 +91,27 @@ void __init xilinx_early_pci_scan(struct pci_controller *hose) for (dev = 0; dev < 2; dev++) { /* List only first function number - up-to 8 functions */ for (func = 0; func < 1; func++) { - printk(KERN_INFO "%02x:%02x:%02x", bus, dev, func); + pr_info("%02x:%02x:%02x", bus, dev, func); /* read the first 64 standardized bytes */ /* Up-to 192 bytes can be list of capabilities */ for (offset = 0; offset < 64; offset += 4) { early_read_config_dword(hose, bus, PCI_DEVFN(dev, func), offset, &val); if (offset == 0 && val == 0xFFFFFFFF) { - printk(KERN_CONT "\nABSENT"); + pr_cont("\nABSENT"); break; } if (!(offset % 0x10)) - printk(KERN_CONT "\n%04x: ", offset); + pr_cont("\n%04x: ", offset); - printk(KERN_CONT "%08x ", val); + pr_cont("%08x ", val); } - printk(KERN_INFO "\n"); + pr_info("\n"); } } } #else -void __init xilinx_early_pci_scan(struct pci_controller *hose) +static void __init xilinx_early_pci_scan(struct pci_controller *hose) { } #endif |