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| author | Ingo Molnar <mingo@kernel.org> | 2015-03-05 20:52:18 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2015-03-05 20:52:18 +0100 |
| commit | 33ca8a53f262b4af40611bea331b8c87d133af72 (patch) | |
| tree | d6468c820a556c4915bcb5b761204a0fb19e8225 /arch/mips/mm/sc-mips.c | |
| parent | db2dcb4f91d5fec5c346a82c309187ee821e2495 (diff) | |
| parent | 13a7a6ac0a11197edcd0f756a035f472b42cdf8b (diff) | |
Merge tag 'v4.0-rc2' into irq/core, to refresh the tree before applying new changes
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/mips/mm/sc-mips.c')
| -rw-r--r-- | arch/mips/mm/sc-mips.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c index 99eb8fabab60..4ceafd13870c 100644 --- a/arch/mips/mm/sc-mips.c +++ b/arch/mips/mm/sc-mips.c @@ -81,6 +81,7 @@ static inline int mips_sc_is_activated(struct cpuinfo_mips *c) case CPU_PROAPTIV: case CPU_P5600: case CPU_BMIPS5000: + case CPU_QEMU_GENERIC: if (config2 & (1 << 12)) return 0; } @@ -104,7 +105,8 @@ static inline int __init mips_sc_probe(void) /* Ignore anything but MIPSxx processors */ if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | - MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2))) + MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 | + MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6))) return 0; /* Does this MIPS32/MIPS64 CPU have a config2 register? */ |