summaryrefslogtreecommitdiff
path: root/arch/mips/pci/ops-sni.c
diff options
context:
space:
mode:
authorDaniel Vetter <daniel.vetter@ffwll.ch>2013-03-19 09:47:30 +0100
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-03-19 09:47:30 +0100
commit0d4a42f6bd298e826620585e766a154ab460617a (patch)
tree406d8f7778691d858dbe3e48e4bbb10e99c0a58a /arch/mips/pci/ops-sni.c
parentd62b4892f3d9f7dd2002e5309be10719d6805b0f (diff)
parenta937536b868b8369b98967929045f1df54234323 (diff)
Merge tag 'v3.9-rc3' into drm-intel-next-queued
Backmerge so that I can merge Imre Deak's coalesced sg entries fixes, which depend upon the new for_each_sg_page introduce in commit a321e91b6d73ed011ffceed384c40d2785cf723b Author: Imre Deak <imre.deak@intel.com> Date: Wed Feb 27 17:02:56 2013 -0800 lib/scatterlist: add simple page iterator The merge itself is just two trivial conflicts: Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'arch/mips/pci/ops-sni.c')
-rw-r--r--arch/mips/pci/ops-sni.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/mips/pci/ops-sni.c b/arch/mips/pci/ops-sni.c
index 97ed25b92edf..35daa7fe6571 100644
--- a/arch/mips/pci/ops-sni.c
+++ b/arch/mips/pci/ops-sni.c
@@ -14,8 +14,8 @@
/*
* It seems that on the RM200 only lower 3 bits of the 5 bit PCI device
- * address are decoded. We therefore manually have to reject attempts at
- * reading outside this range. Being on the paranoid side we only do this
+ * address are decoded. We therefore manually have to reject attempts at
+ * reading outside this range. Being on the paranoid side we only do this
* test for bus 0 and hope forwarding and decoding work properly for any
* subordinated busses.
*
@@ -31,8 +31,8 @@ static int set_config_address(unsigned int busno, unsigned int devfn, int reg)
*(volatile u32 *)PCIMT_CONFIG_ADDRESS =
((busno & 0xff) << 16) |
- ((devfn & 0xff) << 8) |
- (reg & 0xfc);
+ ((devfn & 0xff) << 8) |
+ (reg & 0xfc);
return PCIBIOS_SUCCESSFUL;
}