diff options
| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-03-19 09:47:30 +0100 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-03-19 09:47:30 +0100 |
| commit | 0d4a42f6bd298e826620585e766a154ab460617a (patch) | |
| tree | 406d8f7778691d858dbe3e48e4bbb10e99c0a58a /arch/openrisc/kernel/entry.S | |
| parent | d62b4892f3d9f7dd2002e5309be10719d6805b0f (diff) | |
| parent | a937536b868b8369b98967929045f1df54234323 (diff) | |
Merge tag 'v3.9-rc3' into drm-intel-next-queued
Backmerge so that I can merge Imre Deak's coalesced sg entries fixes,
which depend upon the new for_each_sg_page introduce in
commit a321e91b6d73ed011ffceed384c40d2785cf723b
Author: Imre Deak <imre.deak@intel.com>
Date: Wed Feb 27 17:02:56 2013 -0800
lib/scatterlist: add simple page iterator
The merge itself is just two trivial conflicts:
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'arch/openrisc/kernel/entry.S')
| -rw-r--r-- | arch/openrisc/kernel/entry.S | 20 |
1 files changed, 13 insertions, 7 deletions
diff --git a/arch/openrisc/kernel/entry.S b/arch/openrisc/kernel/entry.S index 5e5b30601bbf..d8a455ede5a7 100644 --- a/arch/openrisc/kernel/entry.S +++ b/arch/openrisc/kernel/entry.S @@ -201,12 +201,17 @@ EXCEPTION_ENTRY(_bus_fault_handler) l.nop /* ---[ 0x300: Data Page Fault exception ]------------------------------- */ +EXCEPTION_ENTRY(_dtlb_miss_page_fault_handler) + l.and r5,r5,r0 + l.j 1f + l.nop EXCEPTION_ENTRY(_data_page_fault_handler) /* set up parameters for do_page_fault */ + l.ori r5,r0,0x300 // exception vector +1: l.addi r3,r1,0 // pt_regs /* r4 set be EXCEPTION_HANDLE */ // effective address of fault - l.ori r5,r0,0x300 // exception vector /* * __PHX__: TODO @@ -276,12 +281,17 @@ EXCEPTION_ENTRY(_data_page_fault_handler) l.nop /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */ +EXCEPTION_ENTRY(_itlb_miss_page_fault_handler) + l.and r5,r5,r0 + l.j 1f + l.nop EXCEPTION_ENTRY(_insn_page_fault_handler) /* set up parameters for do_page_fault */ + l.ori r5,r0,0x400 // exception vector +1: l.addi r3,r1,0 // pt_regs /* r4 set be EXCEPTION_HANDLE */ // effective address of fault - l.ori r5,r0,0x400 // exception vector l.ori r6,r0,0x0 // !write access /* call fault.c handler in or32/mm/fault.c */ @@ -1040,7 +1050,7 @@ ENTRY(_switch) * we are expected to have set up the arg to schedule_tail already, * hence we do so here unconditionally: */ - l.lwz r3,TI_STACK(r3) /* Load 'prev' as schedule_tail arg */ + l.lwz r3,TI_TASK(r3) /* Load 'prev' as schedule_tail arg */ l.jr r9 l.nop @@ -1083,10 +1093,6 @@ ENTRY(__sys_fork) l.j _fork_save_extra_regs_and_call l.addi r3,r1,0 -ENTRY(sys_sigaltstack) - l.j _sys_sigaltstack - l.addi r5,r1,0 - ENTRY(sys_rt_sigreturn) l.j _sys_rt_sigreturn l.addi r3,r1,0 |