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authorDaniel Vetter <daniel.vetter@ffwll.ch>2013-03-19 09:47:30 +0100
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-03-19 09:47:30 +0100
commit0d4a42f6bd298e826620585e766a154ab460617a (patch)
tree406d8f7778691d858dbe3e48e4bbb10e99c0a58a /arch/openrisc/kernel/head.S
parentd62b4892f3d9f7dd2002e5309be10719d6805b0f (diff)
parenta937536b868b8369b98967929045f1df54234323 (diff)
Merge tag 'v3.9-rc3' into drm-intel-next-queued
Backmerge so that I can merge Imre Deak's coalesced sg entries fixes, which depend upon the new for_each_sg_page introduce in commit a321e91b6d73ed011ffceed384c40d2785cf723b Author: Imre Deak <imre.deak@intel.com> Date: Wed Feb 27 17:02:56 2013 -0800 lib/scatterlist: add simple page iterator The merge itself is just two trivial conflicts: Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'arch/openrisc/kernel/head.S')
-rw-r--r--arch/openrisc/kernel/head.S13
1 files changed, 6 insertions, 7 deletions
diff --git a/arch/openrisc/kernel/head.S b/arch/openrisc/kernel/head.S
index 1088b5fca3bd..1d3c9c28ac25 100644
--- a/arch/openrisc/kernel/head.S
+++ b/arch/openrisc/kernel/head.S
@@ -19,6 +19,7 @@
#include <linux/threads.h>
#include <linux/errno.h>
#include <linux/init.h>
+#include <linux/serial_reg.h>
#include <asm/processor.h>
#include <asm/page.h>
#include <asm/mmu.h>
@@ -291,9 +292,9 @@
/* Jump to .init code at _start which lives in the .head section
* and will be discarded after boot.
*/
- LOAD_SYMBOL_2_GPR(r4, _start)
- tophys (r3,r4) /* MMU disabled */
- l.jr r3
+ LOAD_SYMBOL_2_GPR(r15, _start)
+ tophys (r13,r15) /* MMU disabled */
+ l.jr r13
l.nop
/* ---[ 0x200: BUS exception ]------------------------------------------- */
@@ -1069,8 +1070,7 @@ d_pte_not_present:
EXCEPTION_LOAD_GPR4
EXCEPTION_LOAD_GPR5
EXCEPTION_LOAD_GPR6
- l.j _dispatch_do_dpage_fault
- l.nop
+ EXCEPTION_HANDLE(_dtlb_miss_page_fault_handler)
/* ==============================================[ ITLB miss handler ]=== */
ENTRY(itlb_miss_handler)
@@ -1192,8 +1192,7 @@ i_pte_not_present:
EXCEPTION_LOAD_GPR4
EXCEPTION_LOAD_GPR5
EXCEPTION_LOAD_GPR6
- l.j _dispatch_do_ipage_fault
- l.nop
+ EXCEPTION_HANDLE(_itlb_miss_page_fault_handler)
/* ==============================================[ boot tlb handlers ]=== */