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| author | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2015-12-21 03:14:03 +0100 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2015-12-21 03:14:03 +0100 |
| commit | e219aafe50fd546b8686582ddbafd24c3c2eda04 (patch) | |
| tree | a665e08ca8d42f20ac8e5dcc8565d666cffb26bd /arch/parisc/include/asm/cache.h | |
| parent | ffe12855a5f7f195589130197558e6a5c276caa4 (diff) | |
| parent | 24c96dc79c5e76d3cff7a33f955a4d3244644766 (diff) | |
Merge back earlier 'pm-domains' material for v4.5.
Diffstat (limited to 'arch/parisc/include/asm/cache.h')
| -rw-r--r-- | arch/parisc/include/asm/cache.h | 18 |
1 files changed, 5 insertions, 13 deletions
diff --git a/arch/parisc/include/asm/cache.h b/arch/parisc/include/asm/cache.h index 47f11c707b65..3d0e17bcc8e9 100644 --- a/arch/parisc/include/asm/cache.h +++ b/arch/parisc/include/asm/cache.h @@ -7,20 +7,12 @@ /* - * PA 2.0 processors have 64-byte cachelines; PA 1.1 processors have - * 32-byte cachelines. The default configuration is not for SMP anyway, - * so if you're building for SMP, you should select the appropriate - * processor type. There is a potential livelock danger when running - * a machine with this value set too small, but it's more probable you'll - * just ruin performance. + * PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors + * have 32-byte cachelines. The L1 length appears to be 16 bytes but this + * is not clearly documented. */ -#ifdef CONFIG_PA20 -#define L1_CACHE_BYTES 64 -#define L1_CACHE_SHIFT 6 -#else -#define L1_CACHE_BYTES 32 -#define L1_CACHE_SHIFT 5 -#endif +#define L1_CACHE_BYTES 16 +#define L1_CACHE_SHIFT 4 #ifndef __ASSEMBLY__ |