diff options
| author | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2015-12-21 03:14:03 +0100 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2015-12-21 03:14:03 +0100 |
| commit | e219aafe50fd546b8686582ddbafd24c3c2eda04 (patch) | |
| tree | a665e08ca8d42f20ac8e5dcc8565d666cffb26bd /arch/powerpc/include/asm/exception-64e.h | |
| parent | ffe12855a5f7f195589130197558e6a5c276caa4 (diff) | |
| parent | 24c96dc79c5e76d3cff7a33f955a4d3244644766 (diff) | |
Merge back earlier 'pm-domains' material for v4.5.
Diffstat (limited to 'arch/powerpc/include/asm/exception-64e.h')
| -rw-r--r-- | arch/powerpc/include/asm/exception-64e.h | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/arch/powerpc/include/asm/exception-64e.h b/arch/powerpc/include/asm/exception-64e.h index a8b52b61043f..a703452d67b6 100644 --- a/arch/powerpc/include/asm/exception-64e.h +++ b/arch/powerpc/include/asm/exception-64e.h @@ -69,13 +69,14 @@ #define EX_TLB_ESR ( 9 * 8) /* Level 0 and 2 only */ #define EX_TLB_SRR0 (10 * 8) #define EX_TLB_SRR1 (11 * 8) +#define EX_TLB_R7 (12 * 8) #ifdef CONFIG_BOOK3E_MMU_TLB_STATS -#define EX_TLB_R8 (12 * 8) -#define EX_TLB_R9 (13 * 8) -#define EX_TLB_LR (14 * 8) -#define EX_TLB_SIZE (15 * 8) +#define EX_TLB_R8 (13 * 8) +#define EX_TLB_R9 (14 * 8) +#define EX_TLB_LR (15 * 8) +#define EX_TLB_SIZE (16 * 8) #else -#define EX_TLB_SIZE (12 * 8) +#define EX_TLB_SIZE (13 * 8) #endif #define START_EXCEPTION(label) \ @@ -204,8 +205,8 @@ exc_##label##_book3e: #endif #define SET_IVOR(vector_number, vector_offset) \ - li r3,vector_offset@l; \ - ori r3,r3,interrupt_base_book3e@l; \ + LOAD_REG_ADDR(r3,interrupt_base_book3e);\ + ori r3,r3,vector_offset@l; \ mtspr SPRN_IVOR##vector_number,r3; #endif /* _ASM_POWERPC_EXCEPTION_64E_H */ |