diff options
| author | Mauro Carvalho Chehab <mchehab@redhat.com> | 2012-11-28 07:22:38 -0200 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2012-11-28 07:22:38 -0200 |
| commit | d033a308d81ec83908760a15a841c2bd0d5e0ea3 (patch) | |
| tree | 647abd67987fe4d7fee80105fc823edf3f53b4f6 /arch/sh/include/uapi/asm/cachectl.h | |
| parent | c6c22955f80f2db9614b01fe5a3d1cfcd8b3d848 (diff) | |
| parent | e23739b4ade80a3a7f87198f008f6c44a7cbc9fd (diff) | |
Merge remote-tracking branch 'linus/master' into staging/for_v3.8
* linus/master: (1428 commits)
futex: avoid wake_futex() for a PI futex_q
watchdog: using u64 in get_sample_period()
writeback: put unused inodes to LRU after writeback completion
mm: vmscan: check for fatal signals iff the process was throttled
Revert "mm: remove __GFP_NO_KSWAPD"
proc: check vma->vm_file before dereferencing
UAPI: strip the _UAPI prefix from header guards during header installation
include/linux/bug.h: fix sparse warning related to BUILD_BUG_ON_INVALID
Linux 3.7-rc7
powerpc/eeh: Do not invalidate PE properly
ALSA: hda - Fix build without CONFIG_PM
of/address: sparc: Declare of_iomap as an extern function for sparc again
PM / QoS: fix wrong error-checking condition
bnx2x: remove redundant warning log
vxlan: fix command usage in its doc
8139cp: revert "set ring address before enabling receiver"
MPI: Fix compilation on MIPS with GCC 4.4 and newer
MIPS: Fix crash that occurs when function tracing is enabled
MIPS: Merge overlapping bootmem ranges
jbd: Fix lock ordering bug in journal_unmap_buffer()
...
Diffstat (limited to 'arch/sh/include/uapi/asm/cachectl.h')
| -rw-r--r-- | arch/sh/include/uapi/asm/cachectl.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/sh/include/uapi/asm/cachectl.h b/arch/sh/include/uapi/asm/cachectl.h new file mode 100644 index 000000000000..6ffb4b7a212e --- /dev/null +++ b/arch/sh/include/uapi/asm/cachectl.h @@ -0,0 +1,19 @@ +#ifndef _SH_CACHECTL_H +#define _SH_CACHECTL_H + +/* Definitions for the cacheflush system call. */ + +#define CACHEFLUSH_D_INVAL 0x1 /* invalidate (without write back) */ +#define CACHEFLUSH_D_WB 0x2 /* write back (without invalidate) */ +#define CACHEFLUSH_D_PURGE 0x3 /* writeback and invalidate */ + +#define CACHEFLUSH_I 0x4 + +/* + * Options for cacheflush system call + */ +#define ICACHE CACHEFLUSH_I /* flush instruction cache */ +#define DCACHE CACHEFLUSH_D_PURGE /* writeback and flush data cache */ +#define BCACHE (ICACHE|DCACHE) /* flush both caches */ + +#endif /* _SH_CACHECTL_H */ |