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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2009-01-08 16:24:38 +1100 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2009-01-08 16:24:38 +1100 |
| commit | 24f030175d30f019be41766cdf88c2ff03de19ff (patch) | |
| tree | 354232a84e82d5a721ed7b1a9af580ff2a59be8f /arch/xtensa/include/asm/cache.h | |
| parent | 4aa12f7b927c3cac0e0cf3503642597527d0ece0 (diff) | |
| parent | 9e42d0cf5020aaf217433cad1a224745241d212a (diff) | |
Merge commit 'origin/master' into next
Diffstat (limited to 'arch/xtensa/include/asm/cache.h')
| -rw-r--r-- | arch/xtensa/include/asm/cache.h | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/xtensa/include/asm/cache.h b/arch/xtensa/include/asm/cache.h new file mode 100644 index 000000000000..f04c9891142f --- /dev/null +++ b/arch/xtensa/include/asm/cache.h @@ -0,0 +1,33 @@ +/* + * include/asm-xtensa/cache.h + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * (C) 2001 - 2005 Tensilica Inc. + */ + +#ifndef _XTENSA_CACHE_H +#define _XTENSA_CACHE_H + +#include <variant/core.h> + +#define L1_CACHE_SHIFT XCHAL_DCACHE_LINEWIDTH +#define L1_CACHE_BYTES XCHAL_DCACHE_LINESIZE +#define SMP_CACHE_BYTES L1_CACHE_BYTES + +#define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS) +#define ICACHE_WAY_SIZE (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS) +#define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH) +#define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH) + +/* Maximum cache size per way. */ +#if DCACHE_WAY_SIZE >= ICACHE_WAY_SIZE +# define CACHE_WAY_SIZE DCACHE_WAY_SIZE +#else +# define CACHE_WAY_SIZE ICACHE_WAY_SIZE +#endif + + +#endif /* _XTENSA_CACHE_H */ |