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| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-03-19 09:47:30 +0100 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-03-19 09:47:30 +0100 |
| commit | 0d4a42f6bd298e826620585e766a154ab460617a (patch) | |
| tree | 406d8f7778691d858dbe3e48e4bbb10e99c0a58a /arch/xtensa/include/asm/traps.h | |
| parent | d62b4892f3d9f7dd2002e5309be10719d6805b0f (diff) | |
| parent | a937536b868b8369b98967929045f1df54234323 (diff) | |
Merge tag 'v3.9-rc3' into drm-intel-next-queued
Backmerge so that I can merge Imre Deak's coalesced sg entries fixes,
which depend upon the new for_each_sg_page introduce in
commit a321e91b6d73ed011ffceed384c40d2785cf723b
Author: Imre Deak <imre.deak@intel.com>
Date: Wed Feb 27 17:02:56 2013 -0800
lib/scatterlist: add simple page iterator
The merge itself is just two trivial conflicts:
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'arch/xtensa/include/asm/traps.h')
| -rw-r--r-- | arch/xtensa/include/asm/traps.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/xtensa/include/asm/traps.h b/arch/xtensa/include/asm/traps.h index 54f70440185e..b5464ef3cf66 100644 --- a/arch/xtensa/include/asm/traps.h +++ b/arch/xtensa/include/asm/traps.h @@ -20,4 +20,28 @@ extern void * __init trap_set_handler(int cause, void *handler); extern void do_unhandled(struct pt_regs *regs, unsigned long exccause); +static inline void spill_registers(void) +{ + unsigned int a0, ps; + + __asm__ __volatile__ ( + "movi a14, " __stringify(PS_EXCM_BIT | LOCKLEVEL) "\n\t" + "mov a12, a0\n\t" + "rsr a13, sar\n\t" + "xsr a14, ps\n\t" + "movi a0, _spill_registers\n\t" + "rsync\n\t" + "callx0 a0\n\t" + "mov a0, a12\n\t" + "wsr a13, sar\n\t" + "wsr a14, ps\n\t" + : : "a" (&a0), "a" (&ps) +#if defined(CONFIG_FRAME_POINTER) + : "a2", "a3", "a4", "a11", "a12", "a13", "a14", "a15", +#else + : "a2", "a3", "a4", "a7", "a11", "a12", "a13", "a14", "a15", +#endif + "memory"); +} + #endif /* _XTENSA_TRAPS_H */ |